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23b5e15a SG |
1 | /* |
2 | * Copyright 2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #ifndef __MXS_CLK_H | |
13 | #define __MXS_CLK_H | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/clk-provider.h> | |
17 | #include <linux/spinlock.h> | |
18 | ||
19 | #define SET 0x4 | |
20 | #define CLR 0x8 | |
21 | ||
22 | extern spinlock_t mxs_lock; | |
23 | ||
24 | int mxs_clk_wait(void __iomem *reg, u8 shift); | |
25 | ||
26 | struct clk *mxs_clk_pll(const char *name, const char *parent_name, | |
27 | void __iomem *base, u8 power, unsigned long rate); | |
28 | ||
29 | struct clk *mxs_clk_ref(const char *name, const char *parent_name, | |
30 | void __iomem *reg, u8 idx); | |
31 | ||
32 | struct clk *mxs_clk_div(const char *name, const char *parent_name, | |
33 | void __iomem *reg, u8 shift, u8 width, u8 busy); | |
34 | ||
35 | struct clk *mxs_clk_frac(const char *name, const char *parent_name, | |
36 | void __iomem *reg, u8 shift, u8 width, u8 busy); | |
37 | ||
38 | static inline struct clk *mxs_clk_fixed(const char *name, int rate) | |
39 | { | |
40 | return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); | |
41 | } | |
42 | ||
43 | static inline struct clk *mxs_clk_gate(const char *name, | |
44 | const char *parent_name, void __iomem *reg, u8 shift) | |
45 | { | |
46 | return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT, | |
47 | reg, shift, CLK_GATE_SET_TO_DISABLE, | |
48 | &mxs_lock); | |
49 | } | |
50 | ||
51 | static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, | |
52 | u8 shift, u8 width, const char **parent_names, int num_parents) | |
53 | { | |
54 | return clk_register_mux(NULL, name, parent_names, num_parents, | |
55 | CLK_SET_RATE_PARENT, reg, shift, width, | |
56 | 0, &mxs_lock); | |
57 | } | |
58 | ||
59 | static inline struct clk *mxs_clk_fixed_factor(const char *name, | |
60 | const char *parent_name, unsigned int mult, unsigned int div) | |
61 | { | |
62 | return clk_register_fixed_factor(NULL, name, parent_name, | |
63 | CLK_SET_RATE_PARENT, mult, div); | |
64 | } | |
65 | ||
66 | #endif /* __MXS_CLK_H */ |