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1 | /* |
2 | * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. | |
3 | * Copyright (c) BayLibre, SAS. | |
4 | * Author : Neil Armstrong <narmstrong@baylibre.com> | |
5 | * | |
6 | * This software is licensed under the terms of the GNU General Public | |
7 | * License version 2, as published by the Free Software Foundation, and | |
8 | * may be copied, distributed, and modified under those terms. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/bitops.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/clk-provider.h> | |
24 | #include <linux/regmap.h> | |
25 | #include <linux/reset-controller.h> | |
26 | ||
27 | #include <dt-bindings/clock/qcom,gcc-mdm9615.h> | |
28 | #include <dt-bindings/reset/qcom,gcc-mdm9615.h> | |
29 | ||
30 | #include "common.h" | |
31 | #include "clk-regmap.h" | |
32 | #include "clk-pll.h" | |
33 | #include "clk-rcg.h" | |
34 | #include "clk-branch.h" | |
35 | #include "reset.h" | |
36 | ||
37 | static struct clk_fixed_factor cxo = { | |
38 | .mult = 1, | |
39 | .div = 1, | |
40 | .hw.init = &(struct clk_init_data){ | |
41 | .name = "cxo", | |
42 | .parent_names = (const char *[]){ "cxo_board" }, | |
43 | .num_parents = 1, | |
44 | .ops = &clk_fixed_factor_ops, | |
45 | }, | |
46 | }; | |
47 | ||
48 | static struct clk_pll pll0 = { | |
49 | .l_reg = 0x30c4, | |
50 | .m_reg = 0x30c8, | |
51 | .n_reg = 0x30cc, | |
52 | .config_reg = 0x30d4, | |
53 | .mode_reg = 0x30c0, | |
54 | .status_reg = 0x30d8, | |
55 | .status_bit = 16, | |
56 | .clkr.hw.init = &(struct clk_init_data){ | |
57 | .name = "pll0", | |
58 | .parent_names = (const char *[]){ "cxo" }, | |
59 | .num_parents = 1, | |
60 | .ops = &clk_pll_ops, | |
61 | }, | |
62 | }; | |
63 | ||
64 | static struct clk_regmap pll0_vote = { | |
65 | .enable_reg = 0x34c0, | |
66 | .enable_mask = BIT(0), | |
67 | .hw.init = &(struct clk_init_data){ | |
68 | .name = "pll0_vote", | |
69 | .parent_names = (const char *[]){ "pll8" }, | |
70 | .num_parents = 1, | |
71 | .ops = &clk_pll_vote_ops, | |
72 | }, | |
73 | }; | |
74 | ||
75 | static struct clk_regmap pll4_vote = { | |
76 | .enable_reg = 0x34c0, | |
77 | .enable_mask = BIT(4), | |
78 | .hw.init = &(struct clk_init_data){ | |
79 | .name = "pll4_vote", | |
80 | .parent_names = (const char *[]){ "pll4" }, | |
81 | .num_parents = 1, | |
82 | .ops = &clk_pll_vote_ops, | |
83 | }, | |
84 | }; | |
85 | ||
86 | static struct clk_pll pll8 = { | |
87 | .l_reg = 0x3144, | |
88 | .m_reg = 0x3148, | |
89 | .n_reg = 0x314c, | |
90 | .config_reg = 0x3154, | |
91 | .mode_reg = 0x3140, | |
92 | .status_reg = 0x3158, | |
93 | .status_bit = 16, | |
94 | .clkr.hw.init = &(struct clk_init_data){ | |
95 | .name = "pll8", | |
96 | .parent_names = (const char *[]){ "cxo" }, | |
97 | .num_parents = 1, | |
98 | .ops = &clk_pll_ops, | |
99 | }, | |
100 | }; | |
101 | ||
102 | static struct clk_regmap pll8_vote = { | |
103 | .enable_reg = 0x34c0, | |
104 | .enable_mask = BIT(8), | |
105 | .hw.init = &(struct clk_init_data){ | |
106 | .name = "pll8_vote", | |
107 | .parent_names = (const char *[]){ "pll8" }, | |
108 | .num_parents = 1, | |
109 | .ops = &clk_pll_vote_ops, | |
110 | }, | |
111 | }; | |
112 | ||
113 | static struct clk_pll pll14 = { | |
114 | .l_reg = 0x31c4, | |
115 | .m_reg = 0x31c8, | |
116 | .n_reg = 0x31cc, | |
117 | .config_reg = 0x31d4, | |
118 | .mode_reg = 0x31c0, | |
119 | .status_reg = 0x31d8, | |
120 | .status_bit = 16, | |
121 | .clkr.hw.init = &(struct clk_init_data){ | |
122 | .name = "pll14", | |
123 | .parent_names = (const char *[]){ "cxo" }, | |
124 | .num_parents = 1, | |
125 | .ops = &clk_pll_ops, | |
126 | }, | |
127 | }; | |
128 | ||
129 | static struct clk_regmap pll14_vote = { | |
130 | .enable_reg = 0x34c0, | |
131 | .enable_mask = BIT(11), | |
132 | .hw.init = &(struct clk_init_data){ | |
133 | .name = "pll14_vote", | |
134 | .parent_names = (const char *[]){ "pll14" }, | |
135 | .num_parents = 1, | |
136 | .ops = &clk_pll_vote_ops, | |
137 | }, | |
138 | }; | |
139 | ||
140 | enum { | |
141 | P_CXO, | |
142 | P_PLL8, | |
143 | P_PLL14, | |
144 | }; | |
145 | ||
146 | static const struct parent_map gcc_cxo_pll8_map[] = { | |
147 | { P_CXO, 0 }, | |
148 | { P_PLL8, 3 } | |
149 | }; | |
150 | ||
151 | static const char * const gcc_cxo_pll8[] = { | |
152 | "cxo", | |
153 | "pll8_vote", | |
154 | }; | |
155 | ||
156 | static const struct parent_map gcc_cxo_pll14_map[] = { | |
157 | { P_CXO, 0 }, | |
158 | { P_PLL14, 4 } | |
159 | }; | |
160 | ||
161 | static const char * const gcc_cxo_pll14[] = { | |
162 | "cxo", | |
163 | "pll14_vote", | |
164 | }; | |
165 | ||
166 | static const struct parent_map gcc_cxo_map[] = { | |
167 | { P_CXO, 0 }, | |
168 | }; | |
169 | ||
170 | static const char * const gcc_cxo[] = { | |
171 | "cxo", | |
172 | }; | |
173 | ||
174 | static struct freq_tbl clk_tbl_gsbi_uart[] = { | |
175 | { 1843200, P_PLL8, 2, 6, 625 }, | |
176 | { 3686400, P_PLL8, 2, 12, 625 }, | |
177 | { 7372800, P_PLL8, 2, 24, 625 }, | |
178 | { 14745600, P_PLL8, 2, 48, 625 }, | |
179 | { 16000000, P_PLL8, 4, 1, 6 }, | |
180 | { 24000000, P_PLL8, 4, 1, 4 }, | |
181 | { 32000000, P_PLL8, 4, 1, 3 }, | |
182 | { 40000000, P_PLL8, 1, 5, 48 }, | |
183 | { 46400000, P_PLL8, 1, 29, 240 }, | |
184 | { 48000000, P_PLL8, 4, 1, 2 }, | |
185 | { 51200000, P_PLL8, 1, 2, 15 }, | |
186 | { 56000000, P_PLL8, 1, 7, 48 }, | |
187 | { 58982400, P_PLL8, 1, 96, 625 }, | |
188 | { 64000000, P_PLL8, 2, 1, 3 }, | |
189 | { } | |
190 | }; | |
191 | ||
192 | static struct clk_rcg gsbi1_uart_src = { | |
193 | .ns_reg = 0x29d4, | |
194 | .md_reg = 0x29d0, | |
195 | .mn = { | |
196 | .mnctr_en_bit = 8, | |
197 | .mnctr_reset_bit = 7, | |
198 | .mnctr_mode_shift = 5, | |
199 | .n_val_shift = 16, | |
200 | .m_val_shift = 16, | |
201 | .width = 16, | |
202 | }, | |
203 | .p = { | |
204 | .pre_div_shift = 3, | |
205 | .pre_div_width = 2, | |
206 | }, | |
207 | .s = { | |
208 | .src_sel_shift = 0, | |
209 | .parent_map = gcc_cxo_pll8_map, | |
210 | }, | |
211 | .freq_tbl = clk_tbl_gsbi_uart, | |
212 | .clkr = { | |
213 | .enable_reg = 0x29d4, | |
214 | .enable_mask = BIT(11), | |
215 | .hw.init = &(struct clk_init_data){ | |
216 | .name = "gsbi1_uart_src", | |
217 | .parent_names = gcc_cxo_pll8, | |
218 | .num_parents = 2, | |
219 | .ops = &clk_rcg_ops, | |
220 | .flags = CLK_SET_PARENT_GATE, | |
221 | }, | |
222 | }, | |
223 | }; | |
224 | ||
225 | static struct clk_branch gsbi1_uart_clk = { | |
226 | .halt_reg = 0x2fcc, | |
227 | .halt_bit = 10, | |
228 | .clkr = { | |
229 | .enable_reg = 0x29d4, | |
230 | .enable_mask = BIT(9), | |
231 | .hw.init = &(struct clk_init_data){ | |
232 | .name = "gsbi1_uart_clk", | |
233 | .parent_names = (const char *[]){ | |
234 | "gsbi1_uart_src", | |
235 | }, | |
236 | .num_parents = 1, | |
237 | .ops = &clk_branch_ops, | |
238 | .flags = CLK_SET_RATE_PARENT, | |
239 | }, | |
240 | }, | |
241 | }; | |
242 | ||
243 | static struct clk_rcg gsbi2_uart_src = { | |
244 | .ns_reg = 0x29f4, | |
245 | .md_reg = 0x29f0, | |
246 | .mn = { | |
247 | .mnctr_en_bit = 8, | |
248 | .mnctr_reset_bit = 7, | |
249 | .mnctr_mode_shift = 5, | |
250 | .n_val_shift = 16, | |
251 | .m_val_shift = 16, | |
252 | .width = 16, | |
253 | }, | |
254 | .p = { | |
255 | .pre_div_shift = 3, | |
256 | .pre_div_width = 2, | |
257 | }, | |
258 | .s = { | |
259 | .src_sel_shift = 0, | |
260 | .parent_map = gcc_cxo_pll8_map, | |
261 | }, | |
262 | .freq_tbl = clk_tbl_gsbi_uart, | |
263 | .clkr = { | |
264 | .enable_reg = 0x29f4, | |
265 | .enable_mask = BIT(11), | |
266 | .hw.init = &(struct clk_init_data){ | |
267 | .name = "gsbi2_uart_src", | |
268 | .parent_names = gcc_cxo_pll8, | |
269 | .num_parents = 2, | |
270 | .ops = &clk_rcg_ops, | |
271 | .flags = CLK_SET_PARENT_GATE, | |
272 | }, | |
273 | }, | |
274 | }; | |
275 | ||
276 | static struct clk_branch gsbi2_uart_clk = { | |
277 | .halt_reg = 0x2fcc, | |
278 | .halt_bit = 6, | |
279 | .clkr = { | |
280 | .enable_reg = 0x29f4, | |
281 | .enable_mask = BIT(9), | |
282 | .hw.init = &(struct clk_init_data){ | |
283 | .name = "gsbi2_uart_clk", | |
284 | .parent_names = (const char *[]){ | |
285 | "gsbi2_uart_src", | |
286 | }, | |
287 | .num_parents = 1, | |
288 | .ops = &clk_branch_ops, | |
289 | .flags = CLK_SET_RATE_PARENT, | |
290 | }, | |
291 | }, | |
292 | }; | |
293 | ||
294 | static struct clk_rcg gsbi3_uart_src = { | |
295 | .ns_reg = 0x2a14, | |
296 | .md_reg = 0x2a10, | |
297 | .mn = { | |
298 | .mnctr_en_bit = 8, | |
299 | .mnctr_reset_bit = 7, | |
300 | .mnctr_mode_shift = 5, | |
301 | .n_val_shift = 16, | |
302 | .m_val_shift = 16, | |
303 | .width = 16, | |
304 | }, | |
305 | .p = { | |
306 | .pre_div_shift = 3, | |
307 | .pre_div_width = 2, | |
308 | }, | |
309 | .s = { | |
310 | .src_sel_shift = 0, | |
311 | .parent_map = gcc_cxo_pll8_map, | |
312 | }, | |
313 | .freq_tbl = clk_tbl_gsbi_uart, | |
314 | .clkr = { | |
315 | .enable_reg = 0x2a14, | |
316 | .enable_mask = BIT(11), | |
317 | .hw.init = &(struct clk_init_data){ | |
318 | .name = "gsbi3_uart_src", | |
319 | .parent_names = gcc_cxo_pll8, | |
320 | .num_parents = 2, | |
321 | .ops = &clk_rcg_ops, | |
322 | .flags = CLK_SET_PARENT_GATE, | |
323 | }, | |
324 | }, | |
325 | }; | |
326 | ||
327 | static struct clk_branch gsbi3_uart_clk = { | |
328 | .halt_reg = 0x2fcc, | |
329 | .halt_bit = 2, | |
330 | .clkr = { | |
331 | .enable_reg = 0x2a14, | |
332 | .enable_mask = BIT(9), | |
333 | .hw.init = &(struct clk_init_data){ | |
334 | .name = "gsbi3_uart_clk", | |
335 | .parent_names = (const char *[]){ | |
336 | "gsbi3_uart_src", | |
337 | }, | |
338 | .num_parents = 1, | |
339 | .ops = &clk_branch_ops, | |
340 | .flags = CLK_SET_RATE_PARENT, | |
341 | }, | |
342 | }, | |
343 | }; | |
344 | ||
345 | static struct clk_rcg gsbi4_uart_src = { | |
346 | .ns_reg = 0x2a34, | |
347 | .md_reg = 0x2a30, | |
348 | .mn = { | |
349 | .mnctr_en_bit = 8, | |
350 | .mnctr_reset_bit = 7, | |
351 | .mnctr_mode_shift = 5, | |
352 | .n_val_shift = 16, | |
353 | .m_val_shift = 16, | |
354 | .width = 16, | |
355 | }, | |
356 | .p = { | |
357 | .pre_div_shift = 3, | |
358 | .pre_div_width = 2, | |
359 | }, | |
360 | .s = { | |
361 | .src_sel_shift = 0, | |
362 | .parent_map = gcc_cxo_pll8_map, | |
363 | }, | |
364 | .freq_tbl = clk_tbl_gsbi_uart, | |
365 | .clkr = { | |
366 | .enable_reg = 0x2a34, | |
367 | .enable_mask = BIT(11), | |
368 | .hw.init = &(struct clk_init_data){ | |
369 | .name = "gsbi4_uart_src", | |
370 | .parent_names = gcc_cxo_pll8, | |
371 | .num_parents = 2, | |
372 | .ops = &clk_rcg_ops, | |
373 | .flags = CLK_SET_PARENT_GATE, | |
374 | }, | |
375 | }, | |
376 | }; | |
377 | ||
378 | static struct clk_branch gsbi4_uart_clk = { | |
379 | .halt_reg = 0x2fd0, | |
380 | .halt_bit = 26, | |
381 | .clkr = { | |
382 | .enable_reg = 0x2a34, | |
383 | .enable_mask = BIT(9), | |
384 | .hw.init = &(struct clk_init_data){ | |
385 | .name = "gsbi4_uart_clk", | |
386 | .parent_names = (const char *[]){ | |
387 | "gsbi4_uart_src", | |
388 | }, | |
389 | .num_parents = 1, | |
390 | .ops = &clk_branch_ops, | |
391 | .flags = CLK_SET_RATE_PARENT, | |
392 | }, | |
393 | }, | |
394 | }; | |
395 | ||
396 | static struct clk_rcg gsbi5_uart_src = { | |
397 | .ns_reg = 0x2a54, | |
398 | .md_reg = 0x2a50, | |
399 | .mn = { | |
400 | .mnctr_en_bit = 8, | |
401 | .mnctr_reset_bit = 7, | |
402 | .mnctr_mode_shift = 5, | |
403 | .n_val_shift = 16, | |
404 | .m_val_shift = 16, | |
405 | .width = 16, | |
406 | }, | |
407 | .p = { | |
408 | .pre_div_shift = 3, | |
409 | .pre_div_width = 2, | |
410 | }, | |
411 | .s = { | |
412 | .src_sel_shift = 0, | |
413 | .parent_map = gcc_cxo_pll8_map, | |
414 | }, | |
415 | .freq_tbl = clk_tbl_gsbi_uart, | |
416 | .clkr = { | |
417 | .enable_reg = 0x2a54, | |
418 | .enable_mask = BIT(11), | |
419 | .hw.init = &(struct clk_init_data){ | |
420 | .name = "gsbi5_uart_src", | |
421 | .parent_names = gcc_cxo_pll8, | |
422 | .num_parents = 2, | |
423 | .ops = &clk_rcg_ops, | |
424 | .flags = CLK_SET_PARENT_GATE, | |
425 | }, | |
426 | }, | |
427 | }; | |
428 | ||
429 | static struct clk_branch gsbi5_uart_clk = { | |
430 | .halt_reg = 0x2fd0, | |
431 | .halt_bit = 22, | |
432 | .clkr = { | |
433 | .enable_reg = 0x2a54, | |
434 | .enable_mask = BIT(9), | |
435 | .hw.init = &(struct clk_init_data){ | |
436 | .name = "gsbi5_uart_clk", | |
437 | .parent_names = (const char *[]){ | |
438 | "gsbi5_uart_src", | |
439 | }, | |
440 | .num_parents = 1, | |
441 | .ops = &clk_branch_ops, | |
442 | .flags = CLK_SET_RATE_PARENT, | |
443 | }, | |
444 | }, | |
445 | }; | |
446 | ||
447 | static struct freq_tbl clk_tbl_gsbi_qup[] = { | |
448 | { 960000, P_CXO, 4, 1, 5 }, | |
449 | { 4800000, P_CXO, 4, 0, 1 }, | |
450 | { 9600000, P_CXO, 2, 0, 1 }, | |
451 | { 15060000, P_PLL8, 1, 2, 51 }, | |
452 | { 24000000, P_PLL8, 4, 1, 4 }, | |
453 | { 25600000, P_PLL8, 1, 1, 15 }, | |
454 | { 48000000, P_PLL8, 4, 1, 2 }, | |
455 | { 51200000, P_PLL8, 1, 2, 15 }, | |
456 | { } | |
457 | }; | |
458 | ||
459 | static struct clk_rcg gsbi1_qup_src = { | |
460 | .ns_reg = 0x29cc, | |
461 | .md_reg = 0x29c8, | |
462 | .mn = { | |
463 | .mnctr_en_bit = 8, | |
464 | .mnctr_reset_bit = 7, | |
465 | .mnctr_mode_shift = 5, | |
466 | .n_val_shift = 16, | |
467 | .m_val_shift = 16, | |
468 | .width = 8, | |
469 | }, | |
470 | .p = { | |
471 | .pre_div_shift = 3, | |
472 | .pre_div_width = 2, | |
473 | }, | |
474 | .s = { | |
475 | .src_sel_shift = 0, | |
476 | .parent_map = gcc_cxo_pll8_map, | |
477 | }, | |
478 | .freq_tbl = clk_tbl_gsbi_qup, | |
479 | .clkr = { | |
480 | .enable_reg = 0x29cc, | |
481 | .enable_mask = BIT(11), | |
482 | .hw.init = &(struct clk_init_data){ | |
483 | .name = "gsbi1_qup_src", | |
484 | .parent_names = gcc_cxo_pll8, | |
485 | .num_parents = 2, | |
486 | .ops = &clk_rcg_ops, | |
487 | .flags = CLK_SET_PARENT_GATE, | |
488 | }, | |
489 | }, | |
490 | }; | |
491 | ||
492 | static struct clk_branch gsbi1_qup_clk = { | |
493 | .halt_reg = 0x2fcc, | |
494 | .halt_bit = 9, | |
495 | .clkr = { | |
496 | .enable_reg = 0x29cc, | |
497 | .enable_mask = BIT(9), | |
498 | .hw.init = &(struct clk_init_data){ | |
499 | .name = "gsbi1_qup_clk", | |
500 | .parent_names = (const char *[]){ "gsbi1_qup_src" }, | |
501 | .num_parents = 1, | |
502 | .ops = &clk_branch_ops, | |
503 | .flags = CLK_SET_RATE_PARENT, | |
504 | }, | |
505 | }, | |
506 | }; | |
507 | ||
508 | static struct clk_rcg gsbi2_qup_src = { | |
509 | .ns_reg = 0x29ec, | |
510 | .md_reg = 0x29e8, | |
511 | .mn = { | |
512 | .mnctr_en_bit = 8, | |
513 | .mnctr_reset_bit = 7, | |
514 | .mnctr_mode_shift = 5, | |
515 | .n_val_shift = 16, | |
516 | .m_val_shift = 16, | |
517 | .width = 8, | |
518 | }, | |
519 | .p = { | |
520 | .pre_div_shift = 3, | |
521 | .pre_div_width = 2, | |
522 | }, | |
523 | .s = { | |
524 | .src_sel_shift = 0, | |
525 | .parent_map = gcc_cxo_pll8_map, | |
526 | }, | |
527 | .freq_tbl = clk_tbl_gsbi_qup, | |
528 | .clkr = { | |
529 | .enable_reg = 0x29ec, | |
530 | .enable_mask = BIT(11), | |
531 | .hw.init = &(struct clk_init_data){ | |
532 | .name = "gsbi2_qup_src", | |
533 | .parent_names = gcc_cxo_pll8, | |
534 | .num_parents = 2, | |
535 | .ops = &clk_rcg_ops, | |
536 | .flags = CLK_SET_PARENT_GATE, | |
537 | }, | |
538 | }, | |
539 | }; | |
540 | ||
541 | static struct clk_branch gsbi2_qup_clk = { | |
542 | .halt_reg = 0x2fcc, | |
543 | .halt_bit = 4, | |
544 | .clkr = { | |
545 | .enable_reg = 0x29ec, | |
546 | .enable_mask = BIT(9), | |
547 | .hw.init = &(struct clk_init_data){ | |
548 | .name = "gsbi2_qup_clk", | |
549 | .parent_names = (const char *[]){ "gsbi2_qup_src" }, | |
550 | .num_parents = 1, | |
551 | .ops = &clk_branch_ops, | |
552 | .flags = CLK_SET_RATE_PARENT, | |
553 | }, | |
554 | }, | |
555 | }; | |
556 | ||
557 | static struct clk_rcg gsbi3_qup_src = { | |
558 | .ns_reg = 0x2a0c, | |
559 | .md_reg = 0x2a08, | |
560 | .mn = { | |
561 | .mnctr_en_bit = 8, | |
562 | .mnctr_reset_bit = 7, | |
563 | .mnctr_mode_shift = 5, | |
564 | .n_val_shift = 16, | |
565 | .m_val_shift = 16, | |
566 | .width = 8, | |
567 | }, | |
568 | .p = { | |
569 | .pre_div_shift = 3, | |
570 | .pre_div_width = 2, | |
571 | }, | |
572 | .s = { | |
573 | .src_sel_shift = 0, | |
574 | .parent_map = gcc_cxo_pll8_map, | |
575 | }, | |
576 | .freq_tbl = clk_tbl_gsbi_qup, | |
577 | .clkr = { | |
578 | .enable_reg = 0x2a0c, | |
579 | .enable_mask = BIT(11), | |
580 | .hw.init = &(struct clk_init_data){ | |
581 | .name = "gsbi3_qup_src", | |
582 | .parent_names = gcc_cxo_pll8, | |
583 | .num_parents = 2, | |
584 | .ops = &clk_rcg_ops, | |
585 | .flags = CLK_SET_PARENT_GATE, | |
586 | }, | |
587 | }, | |
588 | }; | |
589 | ||
590 | static struct clk_branch gsbi3_qup_clk = { | |
591 | .halt_reg = 0x2fcc, | |
592 | .halt_bit = 0, | |
593 | .clkr = { | |
594 | .enable_reg = 0x2a0c, | |
595 | .enable_mask = BIT(9), | |
596 | .hw.init = &(struct clk_init_data){ | |
597 | .name = "gsbi3_qup_clk", | |
598 | .parent_names = (const char *[]){ "gsbi3_qup_src" }, | |
599 | .num_parents = 1, | |
600 | .ops = &clk_branch_ops, | |
601 | .flags = CLK_SET_RATE_PARENT, | |
602 | }, | |
603 | }, | |
604 | }; | |
605 | ||
606 | static struct clk_rcg gsbi4_qup_src = { | |
607 | .ns_reg = 0x2a2c, | |
608 | .md_reg = 0x2a28, | |
609 | .mn = { | |
610 | .mnctr_en_bit = 8, | |
611 | .mnctr_reset_bit = 7, | |
612 | .mnctr_mode_shift = 5, | |
613 | .n_val_shift = 16, | |
614 | .m_val_shift = 16, | |
615 | .width = 8, | |
616 | }, | |
617 | .p = { | |
618 | .pre_div_shift = 3, | |
619 | .pre_div_width = 2, | |
620 | }, | |
621 | .s = { | |
622 | .src_sel_shift = 0, | |
623 | .parent_map = gcc_cxo_pll8_map, | |
624 | }, | |
625 | .freq_tbl = clk_tbl_gsbi_qup, | |
626 | .clkr = { | |
627 | .enable_reg = 0x2a2c, | |
628 | .enable_mask = BIT(11), | |
629 | .hw.init = &(struct clk_init_data){ | |
630 | .name = "gsbi4_qup_src", | |
631 | .parent_names = gcc_cxo_pll8, | |
632 | .num_parents = 2, | |
633 | .ops = &clk_rcg_ops, | |
634 | .flags = CLK_SET_PARENT_GATE, | |
635 | }, | |
636 | }, | |
637 | }; | |
638 | ||
639 | static struct clk_branch gsbi4_qup_clk = { | |
640 | .halt_reg = 0x2fd0, | |
641 | .halt_bit = 24, | |
642 | .clkr = { | |
643 | .enable_reg = 0x2a2c, | |
644 | .enable_mask = BIT(9), | |
645 | .hw.init = &(struct clk_init_data){ | |
646 | .name = "gsbi4_qup_clk", | |
647 | .parent_names = (const char *[]){ "gsbi4_qup_src" }, | |
648 | .num_parents = 1, | |
649 | .ops = &clk_branch_ops, | |
650 | .flags = CLK_SET_RATE_PARENT, | |
651 | }, | |
652 | }, | |
653 | }; | |
654 | ||
655 | static struct clk_rcg gsbi5_qup_src = { | |
656 | .ns_reg = 0x2a4c, | |
657 | .md_reg = 0x2a48, | |
658 | .mn = { | |
659 | .mnctr_en_bit = 8, | |
660 | .mnctr_reset_bit = 7, | |
661 | .mnctr_mode_shift = 5, | |
662 | .n_val_shift = 16, | |
663 | .m_val_shift = 16, | |
664 | .width = 8, | |
665 | }, | |
666 | .p = { | |
667 | .pre_div_shift = 3, | |
668 | .pre_div_width = 2, | |
669 | }, | |
670 | .s = { | |
671 | .src_sel_shift = 0, | |
672 | .parent_map = gcc_cxo_pll8_map, | |
673 | }, | |
674 | .freq_tbl = clk_tbl_gsbi_qup, | |
675 | .clkr = { | |
676 | .enable_reg = 0x2a4c, | |
677 | .enable_mask = BIT(11), | |
678 | .hw.init = &(struct clk_init_data){ | |
679 | .name = "gsbi5_qup_src", | |
680 | .parent_names = gcc_cxo_pll8, | |
681 | .num_parents = 2, | |
682 | .ops = &clk_rcg_ops, | |
683 | .flags = CLK_SET_PARENT_GATE, | |
684 | }, | |
685 | }, | |
686 | }; | |
687 | ||
688 | static struct clk_branch gsbi5_qup_clk = { | |
689 | .halt_reg = 0x2fd0, | |
690 | .halt_bit = 20, | |
691 | .clkr = { | |
692 | .enable_reg = 0x2a4c, | |
693 | .enable_mask = BIT(9), | |
694 | .hw.init = &(struct clk_init_data){ | |
695 | .name = "gsbi5_qup_clk", | |
696 | .parent_names = (const char *[]){ "gsbi5_qup_src" }, | |
697 | .num_parents = 1, | |
698 | .ops = &clk_branch_ops, | |
699 | .flags = CLK_SET_RATE_PARENT, | |
700 | }, | |
701 | }, | |
702 | }; | |
703 | ||
704 | static const struct freq_tbl clk_tbl_gp[] = { | |
705 | { 9600000, P_CXO, 2, 0, 0 }, | |
706 | { 19200000, P_CXO, 1, 0, 0 }, | |
707 | { } | |
708 | }; | |
709 | ||
710 | static struct clk_rcg gp0_src = { | |
711 | .ns_reg = 0x2d24, | |
712 | .md_reg = 0x2d00, | |
713 | .mn = { | |
714 | .mnctr_en_bit = 8, | |
715 | .mnctr_reset_bit = 7, | |
716 | .mnctr_mode_shift = 5, | |
717 | .n_val_shift = 16, | |
718 | .m_val_shift = 16, | |
719 | .width = 8, | |
720 | }, | |
721 | .p = { | |
722 | .pre_div_shift = 3, | |
723 | .pre_div_width = 2, | |
724 | }, | |
725 | .s = { | |
726 | .src_sel_shift = 0, | |
727 | .parent_map = gcc_cxo_map, | |
728 | }, | |
729 | .freq_tbl = clk_tbl_gp, | |
730 | .clkr = { | |
731 | .enable_reg = 0x2d24, | |
732 | .enable_mask = BIT(11), | |
733 | .hw.init = &(struct clk_init_data){ | |
734 | .name = "gp0_src", | |
735 | .parent_names = gcc_cxo, | |
736 | .num_parents = 1, | |
737 | .ops = &clk_rcg_ops, | |
738 | .flags = CLK_SET_PARENT_GATE, | |
739 | }, | |
740 | } | |
741 | }; | |
742 | ||
743 | static struct clk_branch gp0_clk = { | |
744 | .halt_reg = 0x2fd8, | |
745 | .halt_bit = 7, | |
746 | .clkr = { | |
747 | .enable_reg = 0x2d24, | |
748 | .enable_mask = BIT(9), | |
749 | .hw.init = &(struct clk_init_data){ | |
750 | .name = "gp0_clk", | |
751 | .parent_names = (const char *[]){ "gp0_src" }, | |
752 | .num_parents = 1, | |
753 | .ops = &clk_branch_ops, | |
754 | .flags = CLK_SET_RATE_PARENT, | |
755 | }, | |
756 | }, | |
757 | }; | |
758 | ||
759 | static struct clk_rcg gp1_src = { | |
760 | .ns_reg = 0x2d44, | |
761 | .md_reg = 0x2d40, | |
762 | .mn = { | |
763 | .mnctr_en_bit = 8, | |
764 | .mnctr_reset_bit = 7, | |
765 | .mnctr_mode_shift = 5, | |
766 | .n_val_shift = 16, | |
767 | .m_val_shift = 16, | |
768 | .width = 8, | |
769 | }, | |
770 | .p = { | |
771 | .pre_div_shift = 3, | |
772 | .pre_div_width = 2, | |
773 | }, | |
774 | .s = { | |
775 | .src_sel_shift = 0, | |
776 | .parent_map = gcc_cxo_map, | |
777 | }, | |
778 | .freq_tbl = clk_tbl_gp, | |
779 | .clkr = { | |
780 | .enable_reg = 0x2d44, | |
781 | .enable_mask = BIT(11), | |
782 | .hw.init = &(struct clk_init_data){ | |
783 | .name = "gp1_src", | |
784 | .parent_names = gcc_cxo, | |
785 | .num_parents = 1, | |
786 | .ops = &clk_rcg_ops, | |
787 | .flags = CLK_SET_RATE_GATE, | |
788 | }, | |
789 | } | |
790 | }; | |
791 | ||
792 | static struct clk_branch gp1_clk = { | |
793 | .halt_reg = 0x2fd8, | |
794 | .halt_bit = 6, | |
795 | .clkr = { | |
796 | .enable_reg = 0x2d44, | |
797 | .enable_mask = BIT(9), | |
798 | .hw.init = &(struct clk_init_data){ | |
799 | .name = "gp1_clk", | |
800 | .parent_names = (const char *[]){ "gp1_src" }, | |
801 | .num_parents = 1, | |
802 | .ops = &clk_branch_ops, | |
803 | .flags = CLK_SET_RATE_PARENT, | |
804 | }, | |
805 | }, | |
806 | }; | |
807 | ||
808 | static struct clk_rcg gp2_src = { | |
809 | .ns_reg = 0x2d64, | |
810 | .md_reg = 0x2d60, | |
811 | .mn = { | |
812 | .mnctr_en_bit = 8, | |
813 | .mnctr_reset_bit = 7, | |
814 | .mnctr_mode_shift = 5, | |
815 | .n_val_shift = 16, | |
816 | .m_val_shift = 16, | |
817 | .width = 8, | |
818 | }, | |
819 | .p = { | |
820 | .pre_div_shift = 3, | |
821 | .pre_div_width = 2, | |
822 | }, | |
823 | .s = { | |
824 | .src_sel_shift = 0, | |
825 | .parent_map = gcc_cxo_map, | |
826 | }, | |
827 | .freq_tbl = clk_tbl_gp, | |
828 | .clkr = { | |
829 | .enable_reg = 0x2d64, | |
830 | .enable_mask = BIT(11), | |
831 | .hw.init = &(struct clk_init_data){ | |
832 | .name = "gp2_src", | |
833 | .parent_names = gcc_cxo, | |
834 | .num_parents = 1, | |
835 | .ops = &clk_rcg_ops, | |
836 | .flags = CLK_SET_RATE_GATE, | |
837 | }, | |
838 | } | |
839 | }; | |
840 | ||
841 | static struct clk_branch gp2_clk = { | |
842 | .halt_reg = 0x2fd8, | |
843 | .halt_bit = 5, | |
844 | .clkr = { | |
845 | .enable_reg = 0x2d64, | |
846 | .enable_mask = BIT(9), | |
847 | .hw.init = &(struct clk_init_data){ | |
848 | .name = "gp2_clk", | |
849 | .parent_names = (const char *[]){ "gp2_src" }, | |
850 | .num_parents = 1, | |
851 | .ops = &clk_branch_ops, | |
852 | .flags = CLK_SET_RATE_PARENT, | |
853 | }, | |
854 | }, | |
855 | }; | |
856 | ||
857 | static struct clk_branch pmem_clk = { | |
858 | .hwcg_reg = 0x25a0, | |
859 | .hwcg_bit = 6, | |
860 | .halt_reg = 0x2fc8, | |
861 | .halt_bit = 20, | |
862 | .clkr = { | |
863 | .enable_reg = 0x25a0, | |
864 | .enable_mask = BIT(4), | |
865 | .hw.init = &(struct clk_init_data){ | |
866 | .name = "pmem_clk", | |
867 | .ops = &clk_branch_ops, | |
868 | }, | |
869 | }, | |
870 | }; | |
871 | ||
872 | static struct clk_rcg prng_src = { | |
873 | .ns_reg = 0x2e80, | |
874 | .p = { | |
875 | .pre_div_shift = 3, | |
876 | .pre_div_width = 4, | |
877 | }, | |
878 | .s = { | |
879 | .src_sel_shift = 0, | |
880 | .parent_map = gcc_cxo_pll8_map, | |
881 | }, | |
882 | .clkr = { | |
883 | .hw.init = &(struct clk_init_data){ | |
884 | .name = "prng_src", | |
885 | .parent_names = gcc_cxo_pll8, | |
886 | .num_parents = 2, | |
887 | .ops = &clk_rcg_ops, | |
888 | }, | |
889 | }, | |
890 | }; | |
891 | ||
892 | static struct clk_branch prng_clk = { | |
893 | .halt_reg = 0x2fd8, | |
894 | .halt_check = BRANCH_HALT_VOTED, | |
895 | .halt_bit = 10, | |
896 | .clkr = { | |
897 | .enable_reg = 0x3080, | |
898 | .enable_mask = BIT(10), | |
899 | .hw.init = &(struct clk_init_data){ | |
900 | .name = "prng_clk", | |
901 | .parent_names = (const char *[]){ "prng_src" }, | |
902 | .num_parents = 1, | |
903 | .ops = &clk_branch_ops, | |
904 | }, | |
905 | }, | |
906 | }; | |
907 | ||
908 | static const struct freq_tbl clk_tbl_sdc[] = { | |
909 | { 144000, P_CXO, 1, 1, 133 }, | |
910 | { 400000, P_PLL8, 4, 1, 240 }, | |
911 | { 16000000, P_PLL8, 4, 1, 6 }, | |
912 | { 17070000, P_PLL8, 1, 2, 45 }, | |
913 | { 20210000, P_PLL8, 1, 1, 19 }, | |
914 | { 24000000, P_PLL8, 4, 1, 4 }, | |
915 | { 38400000, P_PLL8, 2, 1, 5 }, | |
916 | { 48000000, P_PLL8, 4, 1, 2 }, | |
917 | { 64000000, P_PLL8, 3, 1, 2 }, | |
918 | { 76800000, P_PLL8, 1, 1, 5 }, | |
919 | { } | |
920 | }; | |
921 | ||
922 | static struct clk_rcg sdc1_src = { | |
923 | .ns_reg = 0x282c, | |
924 | .md_reg = 0x2828, | |
925 | .mn = { | |
926 | .mnctr_en_bit = 8, | |
927 | .mnctr_reset_bit = 7, | |
928 | .mnctr_mode_shift = 5, | |
929 | .n_val_shift = 16, | |
930 | .m_val_shift = 16, | |
931 | .width = 8, | |
932 | }, | |
933 | .p = { | |
934 | .pre_div_shift = 3, | |
935 | .pre_div_width = 2, | |
936 | }, | |
937 | .s = { | |
938 | .src_sel_shift = 0, | |
939 | .parent_map = gcc_cxo_pll8_map, | |
940 | }, | |
941 | .freq_tbl = clk_tbl_sdc, | |
942 | .clkr = { | |
943 | .enable_reg = 0x282c, | |
944 | .enable_mask = BIT(11), | |
945 | .hw.init = &(struct clk_init_data){ | |
946 | .name = "sdc1_src", | |
947 | .parent_names = gcc_cxo_pll8, | |
948 | .num_parents = 2, | |
949 | .ops = &clk_rcg_ops, | |
950 | .flags = CLK_SET_RATE_GATE, | |
951 | }, | |
952 | } | |
953 | }; | |
954 | ||
955 | static struct clk_branch sdc1_clk = { | |
956 | .halt_reg = 0x2fc8, | |
957 | .halt_bit = 6, | |
958 | .clkr = { | |
959 | .enable_reg = 0x282c, | |
960 | .enable_mask = BIT(9), | |
961 | .hw.init = &(struct clk_init_data){ | |
962 | .name = "sdc1_clk", | |
963 | .parent_names = (const char *[]){ "sdc1_src" }, | |
964 | .num_parents = 1, | |
965 | .ops = &clk_branch_ops, | |
966 | .flags = CLK_SET_RATE_PARENT, | |
967 | }, | |
968 | }, | |
969 | }; | |
970 | ||
971 | static struct clk_rcg sdc2_src = { | |
972 | .ns_reg = 0x284c, | |
973 | .md_reg = 0x2848, | |
974 | .mn = { | |
975 | .mnctr_en_bit = 8, | |
976 | .mnctr_reset_bit = 7, | |
977 | .mnctr_mode_shift = 5, | |
978 | .n_val_shift = 16, | |
979 | .m_val_shift = 16, | |
980 | .width = 8, | |
981 | }, | |
982 | .p = { | |
983 | .pre_div_shift = 3, | |
984 | .pre_div_width = 2, | |
985 | }, | |
986 | .s = { | |
987 | .src_sel_shift = 0, | |
988 | .parent_map = gcc_cxo_pll8_map, | |
989 | }, | |
990 | .freq_tbl = clk_tbl_sdc, | |
991 | .clkr = { | |
992 | .enable_reg = 0x284c, | |
993 | .enable_mask = BIT(11), | |
994 | .hw.init = &(struct clk_init_data){ | |
995 | .name = "sdc2_src", | |
996 | .parent_names = gcc_cxo_pll8, | |
997 | .num_parents = 2, | |
998 | .ops = &clk_rcg_ops, | |
999 | .flags = CLK_SET_RATE_GATE, | |
1000 | }, | |
1001 | } | |
1002 | }; | |
1003 | ||
1004 | static struct clk_branch sdc2_clk = { | |
1005 | .halt_reg = 0x2fc8, | |
1006 | .halt_bit = 5, | |
1007 | .clkr = { | |
1008 | .enable_reg = 0x284c, | |
1009 | .enable_mask = BIT(9), | |
1010 | .hw.init = &(struct clk_init_data){ | |
1011 | .name = "sdc2_clk", | |
1012 | .parent_names = (const char *[]){ "sdc2_src" }, | |
1013 | .num_parents = 1, | |
1014 | .ops = &clk_branch_ops, | |
1015 | .flags = CLK_SET_RATE_PARENT, | |
1016 | }, | |
1017 | }, | |
1018 | }; | |
1019 | ||
1020 | static const struct freq_tbl clk_tbl_usb[] = { | |
1021 | { 60000000, P_PLL8, 1, 5, 32 }, | |
1022 | { } | |
1023 | }; | |
1024 | ||
1025 | static struct clk_rcg usb_hs1_xcvr_src = { | |
1026 | .ns_reg = 0x290c, | |
1027 | .md_reg = 0x2908, | |
1028 | .mn = { | |
1029 | .mnctr_en_bit = 8, | |
1030 | .mnctr_reset_bit = 7, | |
1031 | .mnctr_mode_shift = 5, | |
1032 | .n_val_shift = 16, | |
1033 | .m_val_shift = 16, | |
1034 | .width = 8, | |
1035 | }, | |
1036 | .p = { | |
1037 | .pre_div_shift = 3, | |
1038 | .pre_div_width = 2, | |
1039 | }, | |
1040 | .s = { | |
1041 | .src_sel_shift = 0, | |
1042 | .parent_map = gcc_cxo_pll8_map, | |
1043 | }, | |
1044 | .freq_tbl = clk_tbl_usb, | |
1045 | .clkr = { | |
1046 | .enable_reg = 0x290c, | |
1047 | .enable_mask = BIT(11), | |
1048 | .hw.init = &(struct clk_init_data){ | |
1049 | .name = "usb_hs1_xcvr_src", | |
1050 | .parent_names = gcc_cxo_pll8, | |
1051 | .num_parents = 2, | |
1052 | .ops = &clk_rcg_ops, | |
1053 | .flags = CLK_SET_RATE_GATE, | |
1054 | }, | |
1055 | } | |
1056 | }; | |
1057 | ||
1058 | static struct clk_branch usb_hs1_xcvr_clk = { | |
1059 | .halt_reg = 0x2fc8, | |
1060 | .halt_bit = 0, | |
1061 | .clkr = { | |
1062 | .enable_reg = 0x290c, | |
1063 | .enable_mask = BIT(9), | |
1064 | .hw.init = &(struct clk_init_data){ | |
1065 | .name = "usb_hs1_xcvr_clk", | |
1066 | .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, | |
1067 | .num_parents = 1, | |
1068 | .ops = &clk_branch_ops, | |
1069 | .flags = CLK_SET_RATE_PARENT, | |
1070 | }, | |
1071 | }, | |
1072 | }; | |
1073 | ||
1074 | static struct clk_rcg usb_hsic_xcvr_fs_src = { | |
1075 | .ns_reg = 0x2928, | |
1076 | .md_reg = 0x2924, | |
1077 | .mn = { | |
1078 | .mnctr_en_bit = 8, | |
1079 | .mnctr_reset_bit = 7, | |
1080 | .mnctr_mode_shift = 5, | |
1081 | .n_val_shift = 16, | |
1082 | .m_val_shift = 16, | |
1083 | .width = 8, | |
1084 | }, | |
1085 | .p = { | |
1086 | .pre_div_shift = 3, | |
1087 | .pre_div_width = 2, | |
1088 | }, | |
1089 | .s = { | |
1090 | .src_sel_shift = 0, | |
1091 | .parent_map = gcc_cxo_pll8_map, | |
1092 | }, | |
1093 | .freq_tbl = clk_tbl_usb, | |
1094 | .clkr = { | |
1095 | .enable_reg = 0x2928, | |
1096 | .enable_mask = BIT(11), | |
1097 | .hw.init = &(struct clk_init_data){ | |
1098 | .name = "usb_hsic_xcvr_fs_src", | |
1099 | .parent_names = gcc_cxo_pll8, | |
1100 | .num_parents = 2, | |
1101 | .ops = &clk_rcg_ops, | |
1102 | .flags = CLK_SET_RATE_GATE, | |
1103 | }, | |
1104 | } | |
1105 | }; | |
1106 | ||
1107 | static struct clk_branch usb_hsic_xcvr_fs_clk = { | |
1108 | .halt_reg = 0x2fc8, | |
1109 | .halt_bit = 9, | |
1110 | .clkr = { | |
1111 | .enable_reg = 0x2928, | |
1112 | .enable_mask = BIT(9), | |
1113 | .hw.init = &(struct clk_init_data){ | |
1114 | .name = "usb_hsic_xcvr_fs_clk", | |
1115 | .parent_names = | |
1116 | (const char *[]){ "usb_hsic_xcvr_fs_src" }, | |
1117 | .num_parents = 1, | |
1118 | .ops = &clk_branch_ops, | |
1119 | .flags = CLK_SET_RATE_PARENT, | |
1120 | }, | |
1121 | }, | |
1122 | }; | |
1123 | ||
1124 | static const struct freq_tbl clk_tbl_usb_hs1_system[] = { | |
1125 | { 60000000, P_PLL8, 1, 5, 32 }, | |
1126 | { } | |
1127 | }; | |
1128 | ||
1129 | static struct clk_rcg usb_hs1_system_src = { | |
1130 | .ns_reg = 0x36a4, | |
1131 | .md_reg = 0x36a0, | |
1132 | .mn = { | |
1133 | .mnctr_en_bit = 8, | |
1134 | .mnctr_reset_bit = 7, | |
1135 | .mnctr_mode_shift = 5, | |
1136 | .n_val_shift = 16, | |
1137 | .m_val_shift = 16, | |
1138 | .width = 8, | |
1139 | }, | |
1140 | .p = { | |
1141 | .pre_div_shift = 3, | |
1142 | .pre_div_width = 2, | |
1143 | }, | |
1144 | .s = { | |
1145 | .src_sel_shift = 0, | |
1146 | .parent_map = gcc_cxo_pll8_map, | |
1147 | }, | |
1148 | .freq_tbl = clk_tbl_usb_hs1_system, | |
1149 | .clkr = { | |
1150 | .enable_reg = 0x36a4, | |
1151 | .enable_mask = BIT(11), | |
1152 | .hw.init = &(struct clk_init_data){ | |
1153 | .name = "usb_hs1_system_src", | |
1154 | .parent_names = gcc_cxo_pll8, | |
1155 | .num_parents = 2, | |
1156 | .ops = &clk_rcg_ops, | |
1157 | .flags = CLK_SET_RATE_GATE, | |
1158 | }, | |
1159 | } | |
1160 | }; | |
1161 | ||
1162 | static struct clk_branch usb_hs1_system_clk = { | |
1163 | .halt_reg = 0x2fc8, | |
1164 | .halt_bit = 4, | |
1165 | .clkr = { | |
1166 | .enable_reg = 0x36a4, | |
1167 | .enable_mask = BIT(9), | |
1168 | .hw.init = &(struct clk_init_data){ | |
1169 | .parent_names = | |
1170 | (const char *[]){ "usb_hs1_system_src" }, | |
1171 | .num_parents = 1, | |
1172 | .name = "usb_hs1_system_clk", | |
1173 | .ops = &clk_branch_ops, | |
1174 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1175 | }, | |
1176 | }, | |
1177 | }; | |
1178 | ||
1179 | static const struct freq_tbl clk_tbl_usb_hsic_system[] = { | |
1180 | { 64000000, P_PLL8, 1, 1, 6 }, | |
1181 | { } | |
1182 | }; | |
1183 | ||
1184 | static struct clk_rcg usb_hsic_system_src = { | |
1185 | .ns_reg = 0x2b58, | |
1186 | .md_reg = 0x2b54, | |
1187 | .mn = { | |
1188 | .mnctr_en_bit = 8, | |
1189 | .mnctr_reset_bit = 7, | |
1190 | .mnctr_mode_shift = 5, | |
1191 | .n_val_shift = 16, | |
1192 | .m_val_shift = 16, | |
1193 | .width = 8, | |
1194 | }, | |
1195 | .p = { | |
1196 | .pre_div_shift = 3, | |
1197 | .pre_div_width = 2, | |
1198 | }, | |
1199 | .s = { | |
1200 | .src_sel_shift = 0, | |
1201 | .parent_map = gcc_cxo_pll8_map, | |
1202 | }, | |
1203 | .freq_tbl = clk_tbl_usb_hsic_system, | |
1204 | .clkr = { | |
1205 | .enable_reg = 0x2b58, | |
1206 | .enable_mask = BIT(11), | |
1207 | .hw.init = &(struct clk_init_data){ | |
1208 | .name = "usb_hsic_system_src", | |
1209 | .parent_names = gcc_cxo_pll8, | |
1210 | .num_parents = 2, | |
1211 | .ops = &clk_rcg_ops, | |
1212 | .flags = CLK_SET_RATE_GATE, | |
1213 | }, | |
1214 | } | |
1215 | }; | |
1216 | ||
1217 | static struct clk_branch usb_hsic_system_clk = { | |
1218 | .halt_reg = 0x2fc8, | |
1219 | .halt_bit = 7, | |
1220 | .clkr = { | |
1221 | .enable_reg = 0x2b58, | |
1222 | .enable_mask = BIT(9), | |
1223 | .hw.init = &(struct clk_init_data){ | |
1224 | .parent_names = | |
1225 | (const char *[]){ "usb_hsic_system_src" }, | |
1226 | .num_parents = 1, | |
1227 | .name = "usb_hsic_system_clk", | |
1228 | .ops = &clk_branch_ops, | |
1229 | .flags = CLK_SET_RATE_PARENT, | |
1230 | }, | |
1231 | }, | |
1232 | }; | |
1233 | ||
1234 | static const struct freq_tbl clk_tbl_usb_hsic_hsic[] = { | |
1235 | { 48000000, P_PLL14, 1, 0, 0 }, | |
1236 | { } | |
1237 | }; | |
1238 | ||
1239 | static struct clk_rcg usb_hsic_hsic_src = { | |
1240 | .ns_reg = 0x2b50, | |
1241 | .md_reg = 0x2b4c, | |
1242 | .mn = { | |
1243 | .mnctr_en_bit = 8, | |
1244 | .mnctr_reset_bit = 7, | |
1245 | .mnctr_mode_shift = 5, | |
1246 | .n_val_shift = 16, | |
1247 | .m_val_shift = 16, | |
1248 | .width = 8, | |
1249 | }, | |
1250 | .p = { | |
1251 | .pre_div_shift = 3, | |
1252 | .pre_div_width = 2, | |
1253 | }, | |
1254 | .s = { | |
1255 | .src_sel_shift = 0, | |
1256 | .parent_map = gcc_cxo_pll14_map, | |
1257 | }, | |
1258 | .freq_tbl = clk_tbl_usb_hsic_hsic, | |
1259 | .clkr = { | |
1260 | .enable_reg = 0x2b50, | |
1261 | .enable_mask = BIT(11), | |
1262 | .hw.init = &(struct clk_init_data){ | |
1263 | .name = "usb_hsic_hsic_src", | |
1264 | .parent_names = gcc_cxo_pll14, | |
1265 | .num_parents = 2, | |
1266 | .ops = &clk_rcg_ops, | |
1267 | .flags = CLK_SET_RATE_GATE, | |
1268 | }, | |
1269 | } | |
1270 | }; | |
1271 | ||
1272 | static struct clk_branch usb_hsic_hsic_clk = { | |
1273 | .halt_check = BRANCH_HALT_DELAY, | |
1274 | .clkr = { | |
1275 | .enable_reg = 0x2b50, | |
1276 | .enable_mask = BIT(9), | |
1277 | .hw.init = &(struct clk_init_data){ | |
1278 | .parent_names = (const char *[]){ "usb_hsic_hsic_src" }, | |
1279 | .num_parents = 1, | |
1280 | .name = "usb_hsic_hsic_clk", | |
1281 | .ops = &clk_branch_ops, | |
1282 | .flags = CLK_SET_RATE_PARENT, | |
1283 | }, | |
1284 | }, | |
1285 | }; | |
1286 | ||
1287 | static struct clk_branch usb_hsic_hsio_cal_clk = { | |
1288 | .halt_reg = 0x2fc8, | |
1289 | .halt_bit = 8, | |
1290 | .clkr = { | |
1291 | .enable_reg = 0x2b48, | |
1292 | .enable_mask = BIT(0), | |
1293 | .hw.init = &(struct clk_init_data){ | |
1294 | .parent_names = (const char *[]){ "cxo" }, | |
1295 | .num_parents = 1, | |
1296 | .name = "usb_hsic_hsio_cal_clk", | |
1297 | .ops = &clk_branch_ops, | |
1298 | }, | |
1299 | }, | |
1300 | }; | |
1301 | ||
1302 | static struct clk_branch ce1_core_clk = { | |
1303 | .hwcg_reg = 0x2724, | |
1304 | .hwcg_bit = 6, | |
1305 | .halt_reg = 0x2fd4, | |
1306 | .halt_bit = 27, | |
1307 | .clkr = { | |
1308 | .enable_reg = 0x2724, | |
1309 | .enable_mask = BIT(4), | |
1310 | .hw.init = &(struct clk_init_data){ | |
1311 | .name = "ce1_core_clk", | |
1312 | .ops = &clk_branch_ops, | |
1313 | }, | |
1314 | }, | |
1315 | }; | |
1316 | ||
1317 | static struct clk_branch ce1_h_clk = { | |
1318 | .halt_reg = 0x2fd4, | |
1319 | .halt_bit = 1, | |
1320 | .clkr = { | |
1321 | .enable_reg = 0x2720, | |
1322 | .enable_mask = BIT(4), | |
1323 | .hw.init = &(struct clk_init_data){ | |
1324 | .name = "ce1_h_clk", | |
1325 | .ops = &clk_branch_ops, | |
1326 | }, | |
1327 | }, | |
1328 | }; | |
1329 | ||
1330 | static struct clk_branch dma_bam_h_clk = { | |
1331 | .hwcg_reg = 0x25c0, | |
1332 | .hwcg_bit = 6, | |
1333 | .halt_reg = 0x2fc8, | |
1334 | .halt_bit = 12, | |
1335 | .clkr = { | |
1336 | .enable_reg = 0x25c0, | |
1337 | .enable_mask = BIT(4), | |
1338 | .hw.init = &(struct clk_init_data){ | |
1339 | .name = "dma_bam_h_clk", | |
1340 | .ops = &clk_branch_ops, | |
1341 | }, | |
1342 | }, | |
1343 | }; | |
1344 | ||
1345 | static struct clk_branch gsbi1_h_clk = { | |
1346 | .hwcg_reg = 0x29c0, | |
1347 | .hwcg_bit = 6, | |
1348 | .halt_reg = 0x2fcc, | |
1349 | .halt_bit = 11, | |
1350 | .clkr = { | |
1351 | .enable_reg = 0x29c0, | |
1352 | .enable_mask = BIT(4), | |
1353 | .hw.init = &(struct clk_init_data){ | |
1354 | .name = "gsbi1_h_clk", | |
1355 | .ops = &clk_branch_ops, | |
1356 | }, | |
1357 | }, | |
1358 | }; | |
1359 | ||
1360 | static struct clk_branch gsbi2_h_clk = { | |
1361 | .hwcg_reg = 0x29e0, | |
1362 | .hwcg_bit = 6, | |
1363 | .halt_reg = 0x2fcc, | |
1364 | .halt_bit = 7, | |
1365 | .clkr = { | |
1366 | .enable_reg = 0x29e0, | |
1367 | .enable_mask = BIT(4), | |
1368 | .hw.init = &(struct clk_init_data){ | |
1369 | .name = "gsbi2_h_clk", | |
1370 | .ops = &clk_branch_ops, | |
1371 | }, | |
1372 | }, | |
1373 | }; | |
1374 | ||
1375 | static struct clk_branch gsbi3_h_clk = { | |
1376 | .hwcg_reg = 0x2a00, | |
1377 | .hwcg_bit = 6, | |
1378 | .halt_reg = 0x2fcc, | |
1379 | .halt_bit = 3, | |
1380 | .clkr = { | |
1381 | .enable_reg = 0x2a00, | |
1382 | .enable_mask = BIT(4), | |
1383 | .hw.init = &(struct clk_init_data){ | |
1384 | .name = "gsbi3_h_clk", | |
1385 | .ops = &clk_branch_ops, | |
1386 | }, | |
1387 | }, | |
1388 | }; | |
1389 | ||
1390 | static struct clk_branch gsbi4_h_clk = { | |
1391 | .hwcg_reg = 0x2a20, | |
1392 | .hwcg_bit = 6, | |
1393 | .halt_reg = 0x2fd0, | |
1394 | .halt_bit = 27, | |
1395 | .clkr = { | |
1396 | .enable_reg = 0x2a20, | |
1397 | .enable_mask = BIT(4), | |
1398 | .hw.init = &(struct clk_init_data){ | |
1399 | .name = "gsbi4_h_clk", | |
1400 | .ops = &clk_branch_ops, | |
1401 | }, | |
1402 | }, | |
1403 | }; | |
1404 | ||
1405 | static struct clk_branch gsbi5_h_clk = { | |
1406 | .hwcg_reg = 0x2a40, | |
1407 | .hwcg_bit = 6, | |
1408 | .halt_reg = 0x2fd0, | |
1409 | .halt_bit = 23, | |
1410 | .clkr = { | |
1411 | .enable_reg = 0x2a40, | |
1412 | .enable_mask = BIT(4), | |
1413 | .hw.init = &(struct clk_init_data){ | |
1414 | .name = "gsbi5_h_clk", | |
1415 | .ops = &clk_branch_ops, | |
1416 | }, | |
1417 | }, | |
1418 | }; | |
1419 | ||
1420 | static struct clk_branch usb_hs1_h_clk = { | |
1421 | .hwcg_reg = 0x2900, | |
1422 | .hwcg_bit = 6, | |
1423 | .halt_reg = 0x2fc8, | |
1424 | .halt_bit = 1, | |
1425 | .clkr = { | |
1426 | .enable_reg = 0x2900, | |
1427 | .enable_mask = BIT(4), | |
1428 | .hw.init = &(struct clk_init_data){ | |
1429 | .name = "usb_hs1_h_clk", | |
1430 | .ops = &clk_branch_ops, | |
1431 | }, | |
1432 | }, | |
1433 | }; | |
1434 | ||
1435 | static struct clk_branch usb_hsic_h_clk = { | |
1436 | .halt_reg = 0x2fcc, | |
1437 | .halt_bit = 28, | |
1438 | .clkr = { | |
1439 | .enable_reg = 0x2920, | |
1440 | .enable_mask = BIT(4), | |
1441 | .hw.init = &(struct clk_init_data){ | |
1442 | .name = "usb_hsic_h_clk", | |
1443 | .ops = &clk_branch_ops, | |
1444 | }, | |
1445 | }, | |
1446 | }; | |
1447 | ||
1448 | static struct clk_branch sdc1_h_clk = { | |
1449 | .hwcg_reg = 0x2820, | |
1450 | .hwcg_bit = 6, | |
1451 | .halt_reg = 0x2fc8, | |
1452 | .halt_bit = 11, | |
1453 | .clkr = { | |
1454 | .enable_reg = 0x2820, | |
1455 | .enable_mask = BIT(4), | |
1456 | .hw.init = &(struct clk_init_data){ | |
1457 | .name = "sdc1_h_clk", | |
1458 | .ops = &clk_branch_ops, | |
1459 | }, | |
1460 | }, | |
1461 | }; | |
1462 | ||
1463 | static struct clk_branch sdc2_h_clk = { | |
1464 | .hwcg_reg = 0x2840, | |
1465 | .hwcg_bit = 6, | |
1466 | .halt_reg = 0x2fc8, | |
1467 | .halt_bit = 10, | |
1468 | .clkr = { | |
1469 | .enable_reg = 0x2840, | |
1470 | .enable_mask = BIT(4), | |
1471 | .hw.init = &(struct clk_init_data){ | |
1472 | .name = "sdc2_h_clk", | |
1473 | .ops = &clk_branch_ops, | |
1474 | }, | |
1475 | }, | |
1476 | }; | |
1477 | ||
1478 | static struct clk_branch adm0_clk = { | |
1479 | .halt_reg = 0x2fdc, | |
1480 | .halt_check = BRANCH_HALT_VOTED, | |
1481 | .halt_bit = 14, | |
1482 | .clkr = { | |
1483 | .enable_reg = 0x3080, | |
1484 | .enable_mask = BIT(2), | |
1485 | .hw.init = &(struct clk_init_data){ | |
1486 | .name = "adm0_clk", | |
1487 | .ops = &clk_branch_ops, | |
1488 | }, | |
1489 | }, | |
1490 | }; | |
1491 | ||
1492 | static struct clk_branch adm0_pbus_clk = { | |
1493 | .hwcg_reg = 0x2208, | |
1494 | .hwcg_bit = 6, | |
1495 | .halt_reg = 0x2fdc, | |
1496 | .halt_check = BRANCH_HALT_VOTED, | |
1497 | .halt_bit = 13, | |
1498 | .clkr = { | |
1499 | .enable_reg = 0x3080, | |
1500 | .enable_mask = BIT(3), | |
1501 | .hw.init = &(struct clk_init_data){ | |
1502 | .name = "adm0_pbus_clk", | |
1503 | .ops = &clk_branch_ops, | |
1504 | }, | |
1505 | }, | |
1506 | }; | |
1507 | ||
1508 | static struct clk_branch pmic_arb0_h_clk = { | |
1509 | .halt_reg = 0x2fd8, | |
1510 | .halt_check = BRANCH_HALT_VOTED, | |
1511 | .halt_bit = 22, | |
1512 | .clkr = { | |
1513 | .enable_reg = 0x3080, | |
1514 | .enable_mask = BIT(8), | |
1515 | .hw.init = &(struct clk_init_data){ | |
1516 | .name = "pmic_arb0_h_clk", | |
1517 | .ops = &clk_branch_ops, | |
1518 | }, | |
1519 | }, | |
1520 | }; | |
1521 | ||
1522 | static struct clk_branch pmic_arb1_h_clk = { | |
1523 | .halt_reg = 0x2fd8, | |
1524 | .halt_check = BRANCH_HALT_VOTED, | |
1525 | .halt_bit = 21, | |
1526 | .clkr = { | |
1527 | .enable_reg = 0x3080, | |
1528 | .enable_mask = BIT(9), | |
1529 | .hw.init = &(struct clk_init_data){ | |
1530 | .name = "pmic_arb1_h_clk", | |
1531 | .ops = &clk_branch_ops, | |
1532 | }, | |
1533 | }, | |
1534 | }; | |
1535 | ||
1536 | static struct clk_branch pmic_ssbi2_clk = { | |
1537 | .halt_reg = 0x2fd8, | |
1538 | .halt_check = BRANCH_HALT_VOTED, | |
1539 | .halt_bit = 23, | |
1540 | .clkr = { | |
1541 | .enable_reg = 0x3080, | |
1542 | .enable_mask = BIT(7), | |
1543 | .hw.init = &(struct clk_init_data){ | |
1544 | .name = "pmic_ssbi2_clk", | |
1545 | .ops = &clk_branch_ops, | |
1546 | }, | |
1547 | }, | |
1548 | }; | |
1549 | ||
1550 | static struct clk_branch rpm_msg_ram_h_clk = { | |
1551 | .hwcg_reg = 0x27e0, | |
1552 | .hwcg_bit = 6, | |
1553 | .halt_reg = 0x2fd8, | |
1554 | .halt_check = BRANCH_HALT_VOTED, | |
1555 | .halt_bit = 12, | |
1556 | .clkr = { | |
1557 | .enable_reg = 0x3080, | |
1558 | .enable_mask = BIT(6), | |
1559 | .hw.init = &(struct clk_init_data){ | |
1560 | .name = "rpm_msg_ram_h_clk", | |
1561 | .ops = &clk_branch_ops, | |
1562 | }, | |
1563 | }, | |
1564 | }; | |
1565 | ||
1566 | static struct clk_hw *gcc_mdm9615_hws[] = { | |
1567 | &cxo.hw, | |
1568 | }; | |
1569 | ||
1570 | static struct clk_regmap *gcc_mdm9615_clks[] = { | |
1571 | [PLL0] = &pll0.clkr, | |
1572 | [PLL0_VOTE] = &pll0_vote, | |
1573 | [PLL4_VOTE] = &pll4_vote, | |
1574 | [PLL8] = &pll8.clkr, | |
1575 | [PLL8_VOTE] = &pll8_vote, | |
1576 | [PLL14] = &pll14.clkr, | |
1577 | [PLL14_VOTE] = &pll14_vote, | |
1578 | [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, | |
1579 | [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, | |
1580 | [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, | |
1581 | [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, | |
1582 | [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr, | |
1583 | [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr, | |
1584 | [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, | |
1585 | [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, | |
1586 | [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, | |
1587 | [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, | |
1588 | [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, | |
1589 | [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, | |
1590 | [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, | |
1591 | [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, | |
1592 | [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr, | |
1593 | [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr, | |
1594 | [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, | |
1595 | [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, | |
1596 | [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, | |
1597 | [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, | |
1598 | [GP0_SRC] = &gp0_src.clkr, | |
1599 | [GP0_CLK] = &gp0_clk.clkr, | |
1600 | [GP1_SRC] = &gp1_src.clkr, | |
1601 | [GP1_CLK] = &gp1_clk.clkr, | |
1602 | [GP2_SRC] = &gp2_src.clkr, | |
1603 | [GP2_CLK] = &gp2_clk.clkr, | |
1604 | [PMEM_A_CLK] = &pmem_clk.clkr, | |
1605 | [PRNG_SRC] = &prng_src.clkr, | |
1606 | [PRNG_CLK] = &prng_clk.clkr, | |
1607 | [SDC1_SRC] = &sdc1_src.clkr, | |
1608 | [SDC1_CLK] = &sdc1_clk.clkr, | |
1609 | [SDC2_SRC] = &sdc2_src.clkr, | |
1610 | [SDC2_CLK] = &sdc2_clk.clkr, | |
1611 | [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr, | |
1612 | [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, | |
1613 | [USB_HS1_SYSTEM_CLK_SRC] = &usb_hs1_system_src.clkr, | |
1614 | [USB_HS1_SYSTEM_CLK] = &usb_hs1_system_clk.clkr, | |
1615 | [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr, | |
1616 | [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr, | |
1617 | [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_src.clkr, | |
1618 | [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr, | |
1619 | [USB_HSIC_HSIC_CLK_SRC] = &usb_hsic_hsic_src.clkr, | |
1620 | [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr, | |
1621 | [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr, | |
1622 | [CE1_CORE_CLK] = &ce1_core_clk.clkr, | |
1623 | [CE1_H_CLK] = &ce1_h_clk.clkr, | |
1624 | [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr, | |
1625 | [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, | |
1626 | [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, | |
1627 | [GSBI3_H_CLK] = &gsbi3_h_clk.clkr, | |
1628 | [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, | |
1629 | [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, | |
1630 | [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, | |
1631 | [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr, | |
1632 | [SDC1_H_CLK] = &sdc1_h_clk.clkr, | |
1633 | [SDC2_H_CLK] = &sdc2_h_clk.clkr, | |
1634 | [ADM0_CLK] = &adm0_clk.clkr, | |
1635 | [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, | |
1636 | [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, | |
1637 | [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, | |
1638 | [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, | |
1639 | [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, | |
1640 | }; | |
1641 | ||
1642 | static const struct qcom_reset_map gcc_mdm9615_resets[] = { | |
1643 | [DMA_BAM_RESET] = { 0x25c0, 7 }, | |
1644 | [CE1_H_RESET] = { 0x2720, 7 }, | |
1645 | [CE1_CORE_RESET] = { 0x2724, 7 }, | |
1646 | [SDC1_RESET] = { 0x2830 }, | |
1647 | [SDC2_RESET] = { 0x2850 }, | |
1648 | [ADM0_C2_RESET] = { 0x220c, 4 }, | |
1649 | [ADM0_C1_RESET] = { 0x220c, 3 }, | |
1650 | [ADM0_C0_RESET] = { 0x220c, 2 }, | |
1651 | [ADM0_PBUS_RESET] = { 0x220c, 1 }, | |
1652 | [ADM0_RESET] = { 0x220c }, | |
1653 | [USB_HS1_RESET] = { 0x2910 }, | |
1654 | [USB_HSIC_RESET] = { 0x2934 }, | |
1655 | [GSBI1_RESET] = { 0x29dc }, | |
1656 | [GSBI2_RESET] = { 0x29fc }, | |
1657 | [GSBI3_RESET] = { 0x2a1c }, | |
1658 | [GSBI4_RESET] = { 0x2a3c }, | |
1659 | [GSBI5_RESET] = { 0x2a5c }, | |
1660 | [PDM_RESET] = { 0x2CC0, 12 }, | |
1661 | }; | |
1662 | ||
1663 | static const struct regmap_config gcc_mdm9615_regmap_config = { | |
1664 | .reg_bits = 32, | |
1665 | .reg_stride = 4, | |
1666 | .val_bits = 32, | |
1667 | .max_register = 0x3660, | |
1668 | .fast_io = true, | |
1669 | }; | |
1670 | ||
1671 | static const struct qcom_cc_desc gcc_mdm9615_desc = { | |
1672 | .config = &gcc_mdm9615_regmap_config, | |
1673 | .clks = gcc_mdm9615_clks, | |
1674 | .num_clks = ARRAY_SIZE(gcc_mdm9615_clks), | |
1675 | .resets = gcc_mdm9615_resets, | |
1676 | .num_resets = ARRAY_SIZE(gcc_mdm9615_resets), | |
1677 | }; | |
1678 | ||
1679 | static const struct of_device_id gcc_mdm9615_match_table[] = { | |
1680 | { .compatible = "qcom,gcc-mdm9615" }, | |
1681 | { } | |
1682 | }; | |
1683 | MODULE_DEVICE_TABLE(of, gcc_mdm9615_match_table); | |
1684 | ||
1685 | static int gcc_mdm9615_probe(struct platform_device *pdev) | |
1686 | { | |
1687 | struct device *dev = &pdev->dev; | |
1688 | struct regmap *regmap; | |
120c1552 | 1689 | int ret; |
7792a8d6 NA |
1690 | int i; |
1691 | ||
1692 | regmap = qcom_cc_map(pdev, &gcc_mdm9615_desc); | |
1693 | if (IS_ERR(regmap)) | |
1694 | return PTR_ERR(regmap); | |
1695 | ||
1696 | for (i = 0; i < ARRAY_SIZE(gcc_mdm9615_hws); i++) { | |
120c1552 SB |
1697 | ret = devm_clk_hw_register(dev, gcc_mdm9615_hws[i]); |
1698 | if (ret) | |
1699 | return ret; | |
7792a8d6 NA |
1700 | } |
1701 | ||
1702 | return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap); | |
1703 | } | |
1704 | ||
1705 | static struct platform_driver gcc_mdm9615_driver = { | |
1706 | .probe = gcc_mdm9615_probe, | |
1707 | .driver = { | |
1708 | .name = "gcc-mdm9615", | |
1709 | .of_match_table = gcc_mdm9615_match_table, | |
1710 | }, | |
1711 | }; | |
1712 | ||
1713 | static int __init gcc_mdm9615_init(void) | |
1714 | { | |
1715 | return platform_driver_register(&gcc_mdm9615_driver); | |
1716 | } | |
1717 | core_initcall(gcc_mdm9615_init); | |
1718 | ||
1719 | static void __exit gcc_mdm9615_exit(void) | |
1720 | { | |
1721 | platform_driver_unregister(&gcc_mdm9615_driver); | |
1722 | } | |
1723 | module_exit(gcc_mdm9615_exit); | |
1724 | ||
1725 | MODULE_DESCRIPTION("QCOM GCC MDM9615 Driver"); | |
1726 | MODULE_LICENSE("GPL v2"); | |
1727 | MODULE_ALIAS("platform:gcc-mdm9615"); |