[deliverable/linux.git] / drivers / clk / shmobile / clk-div6.c

/*
 * r8a7790 Common Clock Framework support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 *
 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 */

#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>

#include "clk-div6.h"

#define CPG_DIV6_CKSTP		BIT(8)
#define CPG_DIV6_DIV(d)		((d) & 0x3f)
#define CPG_DIV6_DIV_MASK	0x3f

/**
 * struct div6_clock - CPG 6 bit divider clock
 * @hw: handle between common and hardware-specific interfaces
 * @reg: IO-remapped register
 * @div: divisor value (1-64)
 */
struct div6_clock {
	struct clk_hw hw;
	void __iomem *reg;
	unsigned int div;
	u32 src_shift;
	u32 src_width;
	u8 *parents;
};

#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)

static int cpg_div6_clock_enable(struct clk_hw *hw)
{
	struct div6_clock *clock = to_div6_clock(hw);
	u32 val;

	val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
	    | CPG_DIV6_DIV(clock->div - 1);
	clk_writel(val, clock->reg);

	return 0;
}

static void cpg_div6_clock_disable(struct clk_hw *hw)
{
	struct div6_clock *clock = to_div6_clock(hw);
	u32 val;

	val = clk_readl(clock->reg);
	val |= CPG_DIV6_CKSTP;
	/*
	 * DIV6 clocks require the divisor field to be non-zero when stopping
	 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
	 * re-enabled later if the divisor field is changed when stopping the
	 * clock
	 */
	if (!(val & CPG_DIV6_DIV_MASK))
		val |= CPG_DIV6_DIV_MASK;
	clk_writel(val, clock->reg);
}

static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
{
	struct div6_clock *clock = to_div6_clock(hw);

	return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);
}

static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	struct div6_clock *clock = to_div6_clock(hw);
	unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;

	return parent_rate / div;
}

static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
					    unsigned long parent_rate)
{
	unsigned int div;

	if (!rate)
		rate = 1;

	div = DIV_ROUND_CLOSEST(parent_rate, rate);
	return clamp_t(unsigned int, div, 1, 64);
}

static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
				      unsigned long *parent_rate)
{
	unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);

	return *parent_rate / div;
}

static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long parent_rate)
{
	struct div6_clock *clock = to_div6_clock(hw);
	unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
	u32 val;

	clock->div = div;

	val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
	/* Only program the new divisor if the clock isn't stopped. */
	if (!(val & CPG_DIV6_CKSTP))
		clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);

	return 0;
}

static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
{
	struct div6_clock *clock = to_div6_clock(hw);
	unsigned int i;
	u8 hw_index;

	if (clock->src_width == 0)
		return 0;

	hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
		   (BIT(clock->src_width) - 1);
	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
		if (clock->parents[i] == hw_index)
			return i;
	}

	pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
	       __func__, clk_hw_get_name(hw), hw_index);
	return 0;
}

static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
{
	struct div6_clock *clock = to_div6_clock(hw);
	u8 hw_index;
	u32 mask;

	if (index >= clk_hw_get_num_parents(hw))
		return -EINVAL;

	mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
	hw_index = clock->parents[index];

	clk_writel((clk_readl(clock->reg) & mask) |
		(hw_index << clock->src_shift), clock->reg);

	return 0;
}

static const struct clk_ops cpg_div6_clock_ops = {
	.enable = cpg_div6_clock_enable,
	.disable = cpg_div6_clock_disable,
	.is_enabled = cpg_div6_clock_is_enabled,
	.get_parent = cpg_div6_clock_get_parent,
	.set_parent = cpg_div6_clock_set_parent,
	.recalc_rate = cpg_div6_clock_recalc_rate,
	.round_rate = cpg_div6_clock_round_rate,
	.set_rate = cpg_div6_clock_set_rate,
};


/**
 * cpg_div6_register - Register a DIV6 clock
 * @name: Name of the DIV6 clock
 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
 * @parent_names: Array containing the names of the parent clocks
 * @reg: Mapped register used to control the DIV6 clock
 */
struct clk * __init cpg_div6_register(const char *name,
				      unsigned int num_parents,
				      const char **parent_names,
				      void __iomem *reg)
{
	unsigned int valid_parents;
	struct clk_init_data init;
	struct div6_clock *clock;
	struct clk *clk;
	unsigned int i;

	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
	if (!clock)
		return ERR_PTR(-ENOMEM);

	clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
				       GFP_KERNEL);
	if (!clock->parents) {
		clk = ERR_PTR(-ENOMEM);
		goto free_clock;
	}

	clock->reg = reg;

	/*
	 * Read the divisor. Disabling the clock overwrites the divisor, so we
	 * need to cache its value for the enable operation.
	 */
	clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;

	switch (num_parents) {
	case 1:
		/* fixed parent clock */
		clock->src_shift = clock->src_width = 0;
		break;
	case 4:
		/* clock with EXSRC bits 6-7 */
		clock->src_shift = 6;
		clock->src_width = 2;
		break;
	case 8:
		/* VCLK with EXSRC bits 12-14 */
		clock->src_shift = 12;
		clock->src_width = 3;
		break;
	default:
		pr_err("%s: invalid number of parents for DIV6 clock %s\n",
		       __func__, name);
		clk = ERR_PTR(-EINVAL);
		goto free_parents;
	}

	/* Filter out invalid parents */
	for (i = 0, valid_parents = 0; i < num_parents; i++) {
		if (parent_names[i]) {
			parent_names[valid_parents] = parent_names[i];
			clock->parents[valid_parents] = i;
			valid_parents++;
		}
	}

	/* Register the clock. */
	init.name = name;
	init.ops = &cpg_div6_clock_ops;
	init.flags = CLK_IS_BASIC;
	init.parent_names = parent_names;
	init.num_parents = valid_parents;

	clock->hw.init = &init;

	clk = clk_register(NULL, &clock->hw);
	if (IS_ERR(clk))
		goto free_parents;

	return clk;

free_parents:
	kfree(clock->parents);
free_clock:
	kfree(clock);
	return clk;
}

static void __init cpg_div6_clock_init(struct device_node *np)
{
	unsigned int num_parents;
	const char **parent_names;
	const char *clk_name = np->name;
	void __iomem *reg;
	struct clk *clk;
	unsigned int i;

	num_parents = of_clk_get_parent_count(np);
	if (num_parents < 1) {
		pr_err("%s: no parent found for %s DIV6 clock\n",
		       __func__, np->name);
		return;
	}

	parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
				GFP_KERNEL);
	if (!parent_names)
		return;

	reg = of_iomap(np, 0);
	if (reg == NULL) {
		pr_err("%s: failed to map %s DIV6 clock register\n",
		       __func__, np->name);
		goto error;
	}

	/* Parse the DT properties. */
	of_property_read_string(np, "clock-output-names", &clk_name);

	for (i = 0; i < num_parents; i++)
		parent_names[i] = of_clk_get_parent_name(np, i);

	clk = cpg_div6_register(clk_name, num_parents, parent_names, reg);
	if (IS_ERR(clk)) {
		pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
		       __func__, np->name, PTR_ERR(clk));
		goto error;
	}

	of_clk_add_provider(np, of_clk_src_simple_get, clk);

	kfree(parent_names);
	return;

error:
	if (reg)
		iounmap(reg);
	kfree(parent_names);
}
CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
Commit	Line	Data
abe844aa LP	1	/*
	2	* r8a7790 Common Clock Framework support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	*
	6	* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*/
	12
	13	#include <linux/clk-provider.h>
abe844aa LP	14	#include <linux/init.h>
	15	#include <linux/io.h>
	16	#include <linux/kernel.h>
	17	#include <linux/of.h>
	18	#include <linux/of_address.h>
5a1cfafa	19	#include <linux/slab.h>
abe844aa	20
1fae91ec GU	21	#include "clk-div6.h"
1fae91ec GU	22
abe844aa LP	23	#define CPG_DIV6_CKSTP BIT(8)
	24	#define CPG_DIV6_DIV(d) ((d) & 0x3f)
	25	#define CPG_DIV6_DIV_MASK 0x3f
	26
	27	/**
95aa4f9b	28	* struct div6_clock - CPG 6 bit divider clock
abe844aa LP	29	* @hw: handle between common and hardware-specific interfaces
	30	* @reg: IO-remapped register
	31	* @div: divisor value (1-64)
	32	*/
	33	struct div6_clock {
	34	struct clk_hw hw;
	35	void __iomem *reg;
	36	unsigned int div;
c6d67fb0 UH	37	u32 src_shift;
	38	u32 src_width;
	39	u8 *parents;
abe844aa LP	40	};
	41
	42	#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
	43
	44	static int cpg_div6_clock_enable(struct clk_hw *hw)
	45	{
	46	struct div6_clock *clock = to_div6_clock(hw);
c6d67fb0	47	u32 val;
abe844aa	48
c6d67fb0 UH	49	val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK \| CPG_DIV6_CKSTP))
	50	\| CPG_DIV6_DIV(clock->div - 1);
	51	clk_writel(val, clock->reg);
abe844aa LP	52
	53	return 0;
	54	}
	55
	56	static void cpg_div6_clock_disable(struct clk_hw *hw)
	57	{
	58	struct div6_clock *clock = to_div6_clock(hw);
7980a861	59	u32 val;
abe844aa	60
7980a861 GU	61	val = clk_readl(clock->reg);
	62	val \|= CPG_DIV6_CKSTP;
	63	/*
	64	* DIV6 clocks require the divisor field to be non-zero when stopping
	65	* the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
	66	* re-enabled later if the divisor field is changed when stopping the
	67	* clock
abe844aa	68	*/
7980a861 GU	69	if (!(val & CPG_DIV6_DIV_MASK))
	70	val \|= CPG_DIV6_DIV_MASK;
	71	clk_writel(val, clock->reg);
abe844aa LP	72	}
	73
	74	static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
	75	{
	76	struct div6_clock *clock = to_div6_clock(hw);
	77
	78	return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);
	79	}
	80
	81	static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
	82	unsigned long parent_rate)
	83	{
	84	struct div6_clock *clock = to_div6_clock(hw);
	85	unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
	86
	87	return parent_rate / div;
	88	}
	89
	90	static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
	91	unsigned long parent_rate)
	92	{
	93	unsigned int div;
	94
5469d4f2 GU	95	if (!rate)
	96	rate = 1;
	97
abe844aa LP	98	div = DIV_ROUND_CLOSEST(parent_rate, rate);
	99	return clamp_t(unsigned int, div, 1, 64);
	100	}
	101
	102	static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
	103	unsigned long *parent_rate)
	104	{
	105	unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
	106
	107	return *parent_rate / div;
	108	}
	109
	110	static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
	111	unsigned long parent_rate)
	112	{
	113	struct div6_clock *clock = to_div6_clock(hw);
	114	unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
c6d67fb0	115	u32 val;
abe844aa LP	116
	117	clock->div = div;
	118
c6d67fb0	119	val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
abe844aa	120	/* Only program the new divisor if the clock isn't stopped. */
c6d67fb0 UH	121	if (!(val & CPG_DIV6_CKSTP))
	122	clk_writel(val \| CPG_DIV6_DIV(clock->div - 1), clock->reg);
	123
	124	return 0;
	125	}
	126
	127	static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
	128	{
	129	struct div6_clock *clock = to_div6_clock(hw);
	130	unsigned int i;
	131	u8 hw_index;
	132
	133	if (clock->src_width == 0)
	134	return 0;
	135
	136	hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
	137	(BIT(clock->src_width) - 1);
497295af	138	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
c6d67fb0 UH	139	if (clock->parents[i] == hw_index)
	140	return i;
	141	}
	142
	143	pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
836ee0f7	144	__func__, clk_hw_get_name(hw), hw_index);
c6d67fb0 UH	145	return 0;
	146	}
	147
	148	static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
	149	{
	150	struct div6_clock *clock = to_div6_clock(hw);
	151	u8 hw_index;
	152	u32 mask;
	153
497295af	154	if (index >= clk_hw_get_num_parents(hw))
c6d67fb0 UH	155	return -EINVAL;
	156
	157	mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
	158	hw_index = clock->parents[index];
	159
	160	clk_writel((clk_readl(clock->reg) & mask) \|
	161	(hw_index << clock->src_shift), clock->reg);
abe844aa LP	162
	163	return 0;
	164	}
	165
	166	static const struct clk_ops cpg_div6_clock_ops = {
	167	.enable = cpg_div6_clock_enable,
	168	.disable = cpg_div6_clock_disable,
	169	.is_enabled = cpg_div6_clock_is_enabled,
c6d67fb0 UH	170	.get_parent = cpg_div6_clock_get_parent,
c6d67fb0 UH	171	.set_parent = cpg_div6_clock_set_parent,
abe844aa LP	172	.recalc_rate = cpg_div6_clock_recalc_rate,
	173	.round_rate = cpg_div6_clock_round_rate,
	174	.set_rate = cpg_div6_clock_set_rate,
	175	};
	176
1fae91ec GU	177
	178	/**
	179	* cpg_div6_register - Register a DIV6 clock
	180	* @name: Name of the DIV6 clock
	181	* @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
	182	* @parent_names: Array containing the names of the parent clocks
	183	* @reg: Mapped register used to control the DIV6 clock
	184	*/
	185	struct clk * __init cpg_div6_register(const char *name,
	186	unsigned int num_parents,
	187	const char **parent_names,
	188	void __iomem *reg)
abe844aa	189	{
1fae91ec	190	unsigned int valid_parents;
abe844aa LP	191	struct clk_init_data init;
abe844aa LP	192	struct div6_clock *clock;
abe844aa	193	struct clk *clk;
c6d67fb0	194	unsigned int i;
abe844aa LP	195
abe844aa LP	196	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
c6d67fb0	197	if (!clock)
1fae91ec	198	return ERR_PTR(-ENOMEM);
c6d67fb0	199
1fae91ec GU	200	clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
	201	GFP_KERNEL);
	202	if (!clock->parents) {
	203	clk = ERR_PTR(-ENOMEM);
	204	goto free_clock;
abe844aa LP	205	}
abe844aa LP	206
1fae91ec	207	clock->reg = reg;
c6d67fb0	208
1fae91ec GU	209	/*
	210	* Read the divisor. Disabling the clock overwrites the divisor, so we
	211	* need to cache its value for the enable operation.
abe844aa	212	*/
abe844aa LP	213	clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
abe844aa LP	214
c6d67fb0 UH	215	switch (num_parents) {
	216	case 1:
	217	/* fixed parent clock */
	218	clock->src_shift = clock->src_width = 0;
	219	break;
	220	case 4:
	221	/* clock with EXSRC bits 6-7 */
	222	clock->src_shift = 6;
	223	clock->src_width = 2;
	224	break;
	225	case 8:
	226	/* VCLK with EXSRC bits 12-14 */
	227	clock->src_shift = 12;
	228	clock->src_width = 3;
	229	break;
	230	default:
	231	pr_err("%s: invalid number of parents for DIV6 clock %s\n",
1fae91ec GU	232	__func__, name);
	233	clk = ERR_PTR(-EINVAL);
	234	goto free_parents;
	235	}
	236
	237	/* Filter out invalid parents */
	238	for (i = 0, valid_parents = 0; i < num_parents; i++) {
	239	if (parent_names[i]) {
	240	parent_names[valid_parents] = parent_names[i];
	241	clock->parents[valid_parents] = i;
	242	valid_parents++;
	243	}
abe844aa LP	244	}
	245
	246	/* Register the clock. */
1fae91ec	247	init.name = name;
abe844aa LP	248	init.ops = &cpg_div6_clock_ops;
abe844aa LP	249	init.flags = CLK_IS_BASIC;
c6d67fb0 UH	250	init.parent_names = parent_names;
c6d67fb0 UH	251	init.num_parents = valid_parents;
abe844aa LP	252
	253	clock->hw.init = &init;
	254
	255	clk = clk_register(NULL, &clock->hw);
1fae91ec GU	256	if (IS_ERR(clk))
	257	goto free_parents;
	258
	259	return clk;
	260
	261	free_parents:
	262	kfree(clock->parents);
	263	free_clock:
	264	kfree(clock);
	265	return clk;
	266	}
	267
	268	static void __init cpg_div6_clock_init(struct device_node *np)
	269	{
	270	unsigned int num_parents;
	271	const char **parent_names;
	272	const char *clk_name = np->name;
	273	void __iomem *reg;
	274	struct clk *clk;
	275	unsigned int i;
	276
	277	num_parents = of_clk_get_parent_count(np);
	278	if (num_parents < 1) {
	279	pr_err("%s: no parent found for %s DIV6 clock\n",
	280	__func__, np->name);
	281	return;
	282	}
	283
	284	parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
	285	GFP_KERNEL);
	286	if (!parent_names)
	287	return;
	288
	289	reg = of_iomap(np, 0);
	290	if (reg == NULL) {
	291	pr_err("%s: failed to map %s DIV6 clock register\n",
	292	__func__, np->name);
	293	goto error;
	294	}
	295
	296	/* Parse the DT properties. */
	297	of_property_read_string(np, "clock-output-names", &clk_name);
	298
	299	for (i = 0; i < num_parents; i++)
	300	parent_names[i] = of_clk_get_parent_name(np, i);
	301
	302	clk = cpg_div6_register(clk_name, num_parents, parent_names, reg);
abe844aa LP	303	if (IS_ERR(clk)) {
	304	pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
	305	__func__, np->name, PTR_ERR(clk));
	306	goto error;
	307	}
	308
	309	of_clk_add_provider(np, of_clk_src_simple_get, clk);
	310
c6d67fb0	311	kfree(parent_names);
abe844aa LP	312	return;
	313
	314	error:
1fae91ec GU	315	if (reg)
1fae91ec GU	316	iounmap(reg);
c6d67fb0	317	kfree(parent_names);
abe844aa LP	318	}
abe844aa LP	319	CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);