Commit | Line | Data |
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7b42a997 SH |
1 | /* |
2 | * r8a7779 Core CPG Clocks | |
3 | * | |
4 | * Copyright (C) 2013, 2014 Horms Solutions Ltd. | |
5 | * | |
6 | * Contact: Simon Horman <horms@verge.net.au> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/clkdev.h> | |
15 | #include <linux/clk/shmobile.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <linux/spinlock.h> | |
21 | ||
22 | #include <dt-bindings/clock/r8a7779-clock.h> | |
23 | ||
24 | #define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1) | |
25 | ||
26 | struct r8a7779_cpg { | |
27 | struct clk_onecell_data data; | |
28 | spinlock_t lock; | |
29 | void __iomem *reg; | |
30 | }; | |
31 | ||
32 | /* ----------------------------------------------------------------------------- | |
33 | * CPG Clock Data | |
34 | */ | |
35 | ||
36 | /* | |
37 | * MD1 = 1 MD1 = 0 | |
38 | * (PLLA = 1500) (PLLA = 1600) | |
39 | * (MHz) (MHz) | |
40 | *------------------------------------------------+-------------------- | |
41 | * clkz 1000 (2/3) 800 (1/2) | |
42 | * clkzs 250 (1/6) 200 (1/8) | |
43 | * clki 750 (1/2) 800 (1/2) | |
44 | * clks 250 (1/6) 200 (1/8) | |
45 | * clks1 125 (1/12) 100 (1/16) | |
46 | * clks3 187.5 (1/8) 200 (1/8) | |
47 | * clks4 93.7 (1/16) 100 (1/16) | |
48 | * clkp 62.5 (1/24) 50 (1/32) | |
49 | * clkg 62.5 (1/24) 66.6 (1/24) | |
50 | * clkb, CLKOUT | |
51 | * (MD2 = 0) 62.5 (1/24) 66.6 (1/24) | |
52 | * (MD2 = 1) 41.6 (1/36) 50 (1/32) | |
53 | */ | |
54 | ||
55 | #define CPG_CLK_CONFIG_INDEX(md) (((md) & (BIT(2)|BIT(1))) >> 1) | |
56 | ||
57 | struct cpg_clk_config { | |
58 | unsigned int z_mult; | |
59 | unsigned int z_div; | |
60 | unsigned int zs_and_s_div; | |
61 | unsigned int s1_div; | |
62 | unsigned int p_div; | |
63 | unsigned int b_and_out_div; | |
64 | }; | |
65 | ||
66 | static const struct cpg_clk_config cpg_clk_configs[4] __initconst = { | |
67 | { 1, 2, 8, 16, 32, 24 }, | |
68 | { 2, 3, 6, 12, 24, 24 }, | |
69 | { 1, 2, 8, 16, 32, 32 }, | |
70 | { 2, 3, 6, 12, 24, 36 }, | |
71 | }; | |
72 | ||
73 | /* | |
74 | * MD PLLA Ratio | |
75 | * 12 11 | |
76 | *------------------------ | |
77 | * 0 0 x42 | |
78 | * 0 1 x48 | |
79 | * 1 0 x56 | |
80 | * 1 1 x64 | |
81 | */ | |
82 | ||
83 | #define CPG_PLLA_MULT_INDEX(md) (((md) & (BIT(12)|BIT(11))) >> 11) | |
84 | ||
85 | static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; | |
86 | ||
87 | /* ----------------------------------------------------------------------------- | |
88 | * Initialization | |
89 | */ | |
90 | ||
91 | static u32 cpg_mode __initdata; | |
92 | ||
93 | static struct clk * __init | |
94 | r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, | |
95 | const struct cpg_clk_config *config, | |
96 | unsigned int plla_mult, const char *name) | |
97 | { | |
98 | const char *parent_name = "plla"; | |
99 | unsigned int mult = 1; | |
100 | unsigned int div = 1; | |
101 | ||
102 | if (!strcmp(name, "plla")) { | |
103 | parent_name = of_clk_get_parent_name(np, 0); | |
104 | mult = plla_mult; | |
105 | } else if (!strcmp(name, "z")) { | |
106 | div = config->z_div; | |
107 | mult = config->z_mult; | |
108 | } else if (!strcmp(name, "zs") || !strcmp(name, "s")) { | |
109 | div = config->zs_and_s_div; | |
110 | } else if (!strcmp(name, "s1")) { | |
111 | div = config->s1_div; | |
112 | } else if (!strcmp(name, "p")) { | |
113 | div = config->p_div; | |
114 | } else if (!strcmp(name, "b") || !strcmp(name, "out")) { | |
115 | div = config->b_and_out_div; | |
116 | } else { | |
117 | return ERR_PTR(-EINVAL); | |
118 | } | |
119 | ||
120 | return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); | |
121 | } | |
122 | ||
123 | static void __init r8a7779_cpg_clocks_init(struct device_node *np) | |
124 | { | |
125 | const struct cpg_clk_config *config; | |
126 | struct r8a7779_cpg *cpg; | |
127 | struct clk **clks; | |
128 | unsigned int i, plla_mult; | |
129 | int num_clks; | |
130 | ||
131 | num_clks = of_property_count_strings(np, "clock-output-names"); | |
132 | if (num_clks < 0) { | |
133 | pr_err("%s: failed to count clocks\n", __func__); | |
134 | return; | |
135 | } | |
136 | ||
137 | cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); | |
138 | clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL); | |
139 | if (cpg == NULL || clks == NULL) { | |
140 | /* We're leaking memory on purpose, there's no point in cleaning | |
141 | * up as the system won't boot anyway. | |
142 | */ | |
143 | return; | |
144 | } | |
145 | ||
146 | spin_lock_init(&cpg->lock); | |
147 | ||
148 | cpg->data.clks = clks; | |
149 | cpg->data.clk_num = num_clks; | |
150 | ||
151 | config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)]; | |
152 | plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)]; | |
153 | ||
154 | for (i = 0; i < num_clks; ++i) { | |
155 | const char *name; | |
156 | struct clk *clk; | |
157 | ||
158 | of_property_read_string_index(np, "clock-output-names", i, | |
159 | &name); | |
160 | ||
161 | clk = r8a7779_cpg_register_clock(np, cpg, config, | |
162 | plla_mult, name); | |
163 | if (IS_ERR(clk)) | |
164 | pr_err("%s: failed to register %s %s clock (%ld)\n", | |
165 | __func__, np->name, name, PTR_ERR(clk)); | |
166 | else | |
167 | cpg->data.clks[i] = clk; | |
168 | } | |
169 | ||
170 | of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); | |
171 | } | |
172 | CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks", | |
173 | r8a7779_cpg_clocks_init); | |
174 | ||
175 | void __init r8a7779_clocks_init(u32 mode) | |
176 | { | |
177 | cpg_mode = mode; | |
178 | ||
179 | of_clk_init(NULL); | |
180 | } |