Commit | Line | Data |
---|---|---|
02c981c0 | 1 | /* |
7bf21bc8 | 2 | * common clks module for all SiRF SoCs |
02c981c0 | 3 | * |
77366929 BS |
4 | * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group |
5 | * company. | |
02c981c0 BD |
6 | * |
7 | * Licensed under GPLv2 or later. | |
8 | */ | |
9 | ||
fdb94059 SB |
10 | #include <linux/clk.h> |
11 | ||
02c981c0 BD |
12 | #define KHZ 1000 |
13 | #define MHZ (KHZ * KHZ) | |
14 | ||
f53f551b SB |
15 | static void __iomem *sirfsoc_clk_vbase; |
16 | static void __iomem *sirfsoc_rsc_vbase; | |
7bf21bc8 BS |
17 | static struct clk_onecell_data clk_data; |
18 | ||
198678b0 BD |
19 | /* |
20 | * SiRFprimaII clock controller | |
21 | * - 2 oscillators: osc-26MHz, rtc-32.768KHz | |
22 | * - 3 standard configurable plls: pll1, pll2 & pll3 | |
23 | * - 2 exclusive plls: usb phy pll and sata phy pll | |
24 | * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia, | |
25 | * display and sdphy. | |
26 | * Each clock domain can select its own clock source from five clock sources, | |
27 | * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source | |
28 | * clock of the group clock. | |
29 | * - dsp domain: gps, mf | |
30 | * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse | |
31 | * - sys domain: security | |
32 | */ | |
33 | ||
34 | struct clk_pll { | |
35 | struct clk_hw hw; | |
36 | unsigned short regofs; /* register offset */ | |
02c981c0 BD |
37 | }; |
38 | ||
198678b0 BD |
39 | #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) |
40 | ||
41 | struct clk_dmn { | |
42 | struct clk_hw hw; | |
02c981c0 BD |
43 | signed char enable_bit; /* enable bit: 0 ~ 63 */ |
44 | unsigned short regofs; /* register offset */ | |
02c981c0 BD |
45 | }; |
46 | ||
198678b0 BD |
47 | #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw) |
48 | ||
49 | struct clk_std { | |
50 | struct clk_hw hw; | |
51 | signed char enable_bit; /* enable bit: 0 ~ 63 */ | |
52 | }; | |
53 | ||
54 | #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw) | |
55 | ||
56 | static int std_clk_is_enabled(struct clk_hw *hw); | |
57 | static int std_clk_enable(struct clk_hw *hw); | |
58 | static void std_clk_disable(struct clk_hw *hw); | |
02c981c0 BD |
59 | |
60 | static inline unsigned long clkc_readl(unsigned reg) | |
61 | { | |
198678b0 | 62 | return readl(sirfsoc_clk_vbase + reg); |
02c981c0 BD |
63 | } |
64 | ||
65 | static inline void clkc_writel(u32 val, unsigned reg) | |
66 | { | |
198678b0 | 67 | writel(val, sirfsoc_clk_vbase + reg); |
02c981c0 BD |
68 | } |
69 | ||
02c981c0 BD |
70 | /* |
71 | * std pll | |
72 | */ | |
198678b0 BD |
73 | |
74 | static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, | |
75 | unsigned long parent_rate) | |
02c981c0 | 76 | { |
198678b0 BD |
77 | unsigned long fin = parent_rate; |
78 | struct clk_pll *clk = to_pllclk(hw); | |
02c981c0 BD |
79 | u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - |
80 | SIRFSOC_CLKC_PLL1_CFG0; | |
81 | ||
82 | if (clkc_readl(regcfg2) & BIT(2)) { | |
83 | /* pll bypass mode */ | |
198678b0 | 84 | return fin; |
02c981c0 BD |
85 | } else { |
86 | /* fout = fin * nf / nr / od */ | |
87 | u32 cfg0 = clkc_readl(clk->regofs); | |
88 | u32 nf = (cfg0 & (BIT(13) - 1)) + 1; | |
89 | u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; | |
90 | u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; | |
91 | WARN_ON(fin % MHZ); | |
198678b0 | 92 | return fin / MHZ * nf / nr / od * MHZ; |
02c981c0 | 93 | } |
198678b0 BD |
94 | } |
95 | ||
96 | static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
97 | unsigned long *parent_rate) | |
98 | { | |
99 | unsigned long fin, nf, nr, od; | |
7bf21bc8 | 100 | u64 dividend; |
198678b0 BD |
101 | |
102 | /* | |
103 | * fout = fin * nf / (nr * od); | |
104 | * set od = 1, nr = fin/MHz, so fout = nf * MHz | |
105 | */ | |
106 | rate = rate - rate % MHZ; | |
107 | ||
108 | nf = rate / MHZ; | |
109 | if (nf > BIT(13)) | |
110 | nf = BIT(13); | |
111 | if (nf < 1) | |
112 | nf = 1; | |
02c981c0 | 113 | |
198678b0 BD |
114 | fin = *parent_rate; |
115 | ||
116 | nr = fin / MHZ; | |
117 | if (nr > BIT(6)) | |
118 | nr = BIT(6); | |
119 | od = 1; | |
120 | ||
7bf21bc8 BS |
121 | dividend = (u64)fin * nf; |
122 | do_div(dividend, nr * od); | |
123 | ||
124 | return (long)dividend; | |
02c981c0 BD |
125 | } |
126 | ||
198678b0 BD |
127 | static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
128 | unsigned long parent_rate) | |
02c981c0 | 129 | { |
198678b0 | 130 | struct clk_pll *clk = to_pllclk(hw); |
02c981c0 BD |
131 | unsigned long fin, nf, nr, od, reg; |
132 | ||
133 | /* | |
134 | * fout = fin * nf / (nr * od); | |
135 | * set od = 1, nr = fin/MHz, so fout = nf * MHz | |
136 | */ | |
137 | ||
138 | nf = rate / MHZ; | |
139 | if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) | |
140 | return -EINVAL; | |
141 | ||
198678b0 | 142 | fin = parent_rate; |
02c981c0 BD |
143 | BUG_ON(fin < MHZ); |
144 | ||
145 | nr = fin / MHZ; | |
146 | BUG_ON((fin % MHZ) || nr > BIT(6)); | |
147 | ||
148 | od = 1; | |
149 | ||
150 | reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); | |
151 | clkc_writel(reg, clk->regofs); | |
152 | ||
153 | reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; | |
154 | clkc_writel((nf >> 1) - 1, reg); | |
155 | ||
156 | reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; | |
157 | while (!(clkc_readl(reg) & BIT(6))) | |
158 | cpu_relax(); | |
159 | ||
02c981c0 BD |
160 | return 0; |
161 | } | |
162 | ||
7bf21bc8 BS |
163 | static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
164 | unsigned long *parent_rate) | |
165 | { | |
166 | /* | |
167 | * SiRF SoC has not cpu clock control, | |
168 | * So bypass to it's parent pll. | |
169 | */ | |
b17dbff4 SB |
170 | struct clk_hw *parent_clk = clk_hw_get_parent(hw); |
171 | struct clk_hw *pll_parent_clk = clk_hw_get_parent(parent_clk); | |
172 | unsigned long pll_parent_rate = clk_hw_get_rate(pll_parent_clk); | |
173 | return pll_clk_round_rate(parent_clk, rate, &pll_parent_rate); | |
7bf21bc8 BS |
174 | } |
175 | ||
176 | static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw, | |
177 | unsigned long parent_rate) | |
178 | { | |
179 | /* | |
180 | * SiRF SoC has not cpu clock control, | |
181 | * So return the parent pll rate. | |
182 | */ | |
b17dbff4 SB |
183 | struct clk_hw *parent_clk = clk_hw_get_parent(hw); |
184 | return clk_hw_get_rate(parent_clk); | |
7bf21bc8 BS |
185 | } |
186 | ||
02c981c0 | 187 | static struct clk_ops std_pll_ops = { |
198678b0 BD |
188 | .recalc_rate = pll_clk_recalc_rate, |
189 | .round_rate = pll_clk_round_rate, | |
190 | .set_rate = pll_clk_set_rate, | |
02c981c0 BD |
191 | }; |
192 | ||
45195b8f | 193 | static const char * const pll_clk_parents[] = { |
198678b0 BD |
194 | "osc", |
195 | }; | |
196 | ||
197 | static struct clk_init_data clk_pll1_init = { | |
198 | .name = "pll1", | |
02c981c0 | 199 | .ops = &std_pll_ops, |
198678b0 BD |
200 | .parent_names = pll_clk_parents, |
201 | .num_parents = ARRAY_SIZE(pll_clk_parents), | |
02c981c0 BD |
202 | }; |
203 | ||
198678b0 BD |
204 | static struct clk_init_data clk_pll2_init = { |
205 | .name = "pll2", | |
02c981c0 | 206 | .ops = &std_pll_ops, |
198678b0 BD |
207 | .parent_names = pll_clk_parents, |
208 | .num_parents = ARRAY_SIZE(pll_clk_parents), | |
02c981c0 BD |
209 | }; |
210 | ||
198678b0 BD |
211 | static struct clk_init_data clk_pll3_init = { |
212 | .name = "pll3", | |
02c981c0 | 213 | .ops = &std_pll_ops, |
198678b0 BD |
214 | .parent_names = pll_clk_parents, |
215 | .num_parents = ARRAY_SIZE(pll_clk_parents), | |
216 | }; | |
217 | ||
218 | static struct clk_pll clk_pll1 = { | |
219 | .regofs = SIRFSOC_CLKC_PLL1_CFG0, | |
220 | .hw = { | |
221 | .init = &clk_pll1_init, | |
222 | }, | |
223 | }; | |
224 | ||
225 | static struct clk_pll clk_pll2 = { | |
226 | .regofs = SIRFSOC_CLKC_PLL2_CFG0, | |
227 | .hw = { | |
228 | .init = &clk_pll2_init, | |
229 | }, | |
230 | }; | |
231 | ||
232 | static struct clk_pll clk_pll3 = { | |
233 | .regofs = SIRFSOC_CLKC_PLL3_CFG0, | |
234 | .hw = { | |
235 | .init = &clk_pll3_init, | |
236 | }, | |
02c981c0 BD |
237 | }; |
238 | ||
239 | /* | |
198678b0 | 240 | * usb uses specified pll |
02c981c0 BD |
241 | */ |
242 | ||
198678b0 BD |
243 | static int usb_pll_clk_enable(struct clk_hw *hw) |
244 | { | |
245 | u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); | |
246 | reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); | |
247 | writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); | |
248 | while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) & | |
249 | SIRFSOC_USBPHY_PLL_LOCK)) | |
250 | cpu_relax(); | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
255 | static void usb_pll_clk_disable(struct clk_hw *clk) | |
256 | { | |
257 | u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); | |
258 | reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); | |
259 | writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); | |
260 | } | |
02c981c0 | 261 | |
198678b0 | 262 | static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) |
02c981c0 | 263 | { |
198678b0 BD |
264 | u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); |
265 | return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ; | |
266 | } | |
267 | ||
268 | static struct clk_ops usb_pll_ops = { | |
269 | .enable = usb_pll_clk_enable, | |
270 | .disable = usb_pll_clk_disable, | |
271 | .recalc_rate = usb_pll_clk_recalc_rate, | |
272 | }; | |
273 | ||
274 | static struct clk_init_data clk_usb_pll_init = { | |
275 | .name = "usb_pll", | |
276 | .ops = &usb_pll_ops, | |
277 | .parent_names = pll_clk_parents, | |
278 | .num_parents = ARRAY_SIZE(pll_clk_parents), | |
279 | }; | |
280 | ||
281 | static struct clk_hw usb_pll_clk_hw = { | |
282 | .init = &clk_usb_pll_init, | |
283 | }; | |
284 | ||
285 | /* | |
286 | * clock domains - cpu, mem, sys/io, dsp, gfx | |
287 | */ | |
288 | ||
45195b8f | 289 | static const char * const dmn_clk_parents[] = { |
198678b0 BD |
290 | "rtc", |
291 | "osc", | |
292 | "pll1", | |
293 | "pll2", | |
294 | "pll3", | |
295 | }; | |
296 | ||
297 | static u8 dmn_clk_get_parent(struct clk_hw *hw) | |
298 | { | |
299 | struct clk_dmn *clk = to_dmnclk(hw); | |
02c981c0 | 300 | u32 cfg = clkc_readl(clk->regofs); |
198678b0 BD |
301 | |
302 | /* parent of io domain can only be pll3 */ | |
303 | if (strcmp(hw->init->name, "io") == 0) | |
304 | return 4; | |
305 | ||
02c981c0 | 306 | WARN_ON((cfg & (BIT(3) - 1)) > 4); |
198678b0 BD |
307 | |
308 | return cfg & (BIT(3) - 1); | |
02c981c0 BD |
309 | } |
310 | ||
198678b0 | 311 | static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent) |
02c981c0 | 312 | { |
198678b0 | 313 | struct clk_dmn *clk = to_dmnclk(hw); |
02c981c0 | 314 | u32 cfg = clkc_readl(clk->regofs); |
198678b0 BD |
315 | |
316 | /* parent of io domain can only be pll3 */ | |
317 | if (strcmp(hw->init->name, "io") == 0) | |
318 | return -EINVAL; | |
319 | ||
320 | cfg &= ~(BIT(3) - 1); | |
321 | clkc_writel(cfg | parent, clk->regofs); | |
322 | /* BIT(3) - switching status: 1 - busy, 0 - done */ | |
323 | while (clkc_readl(clk->regofs) & BIT(3)) | |
324 | cpu_relax(); | |
325 | ||
326 | return 0; | |
02c981c0 BD |
327 | } |
328 | ||
198678b0 BD |
329 | static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw, |
330 | unsigned long parent_rate) | |
331 | ||
02c981c0 | 332 | { |
198678b0 BD |
333 | unsigned long fin = parent_rate; |
334 | struct clk_dmn *clk = to_dmnclk(hw); | |
335 | ||
02c981c0 | 336 | u32 cfg = clkc_readl(clk->regofs); |
198678b0 | 337 | |
02c981c0 BD |
338 | if (cfg & BIT(24)) { |
339 | /* fcd bypass mode */ | |
198678b0 | 340 | return fin; |
02c981c0 BD |
341 | } else { |
342 | /* | |
343 | * wait count: bit[19:16], hold count: bit[23:20] | |
344 | */ | |
345 | u32 wait = (cfg >> 16) & (BIT(4) - 1); | |
346 | u32 hold = (cfg >> 20) & (BIT(4) - 1); | |
347 | ||
198678b0 | 348 | return fin / (wait + hold + 2); |
02c981c0 | 349 | } |
198678b0 BD |
350 | } |
351 | ||
352 | static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
353 | unsigned long *parent_rate) | |
354 | { | |
355 | unsigned long fin; | |
356 | unsigned ratio, wait, hold; | |
357 | unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4; | |
358 | ||
359 | fin = *parent_rate; | |
360 | ratio = fin / rate; | |
361 | ||
362 | if (ratio < 2) | |
363 | ratio = 2; | |
364 | if (ratio > BIT(bits + 1)) | |
365 | ratio = BIT(bits + 1); | |
02c981c0 | 366 | |
198678b0 BD |
367 | wait = (ratio >> 1) - 1; |
368 | hold = ratio - wait - 2; | |
369 | ||
370 | return fin / (wait + hold + 2); | |
02c981c0 BD |
371 | } |
372 | ||
198678b0 BD |
373 | static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
374 | unsigned long parent_rate) | |
02c981c0 | 375 | { |
198678b0 | 376 | struct clk_dmn *clk = to_dmnclk(hw); |
02c981c0 BD |
377 | unsigned long fin; |
378 | unsigned ratio, wait, hold, reg; | |
198678b0 | 379 | unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4; |
02c981c0 | 380 | |
198678b0 | 381 | fin = parent_rate; |
02c981c0 BD |
382 | ratio = fin / rate; |
383 | ||
384 | if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) | |
385 | return -EINVAL; | |
386 | ||
387 | WARN_ON(fin % rate); | |
388 | ||
389 | wait = (ratio >> 1) - 1; | |
390 | hold = ratio - wait - 2; | |
391 | ||
392 | reg = clkc_readl(clk->regofs); | |
393 | reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); | |
394 | reg |= (wait << 16) | (hold << 20) | BIT(25); | |
395 | clkc_writel(reg, clk->regofs); | |
396 | ||
397 | /* waiting FCD been effective */ | |
398 | while (clkc_readl(clk->regofs) & BIT(25)) | |
399 | cpu_relax(); | |
400 | ||
02c981c0 BD |
401 | return 0; |
402 | } | |
403 | ||
7bf21bc8 BS |
404 | static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
405 | unsigned long parent_rate) | |
406 | { | |
407 | int ret1, ret2; | |
408 | struct clk *cur_parent; | |
409 | ||
410 | if (rate == clk_get_rate(clk_pll1.hw.clk)) { | |
411 | ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); | |
412 | return ret1; | |
413 | } | |
414 | ||
415 | if (rate == clk_get_rate(clk_pll2.hw.clk)) { | |
416 | ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); | |
417 | return ret1; | |
418 | } | |
419 | ||
420 | if (rate == clk_get_rate(clk_pll3.hw.clk)) { | |
421 | ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk); | |
422 | return ret1; | |
423 | } | |
424 | ||
425 | cur_parent = clk_get_parent(hw->clk); | |
426 | ||
427 | /* switch to tmp pll before setting parent clock's rate */ | |
428 | if (cur_parent == clk_pll1.hw.clk) { | |
429 | ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); | |
430 | BUG_ON(ret1); | |
431 | } | |
432 | ||
433 | ret2 = clk_set_rate(clk_pll1.hw.clk, rate); | |
434 | ||
435 | ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); | |
436 | ||
437 | return ret2 ? ret2 : ret1; | |
438 | } | |
439 | ||
198678b0 BD |
440 | static struct clk_ops msi_ops = { |
441 | .set_rate = dmn_clk_set_rate, | |
442 | .round_rate = dmn_clk_round_rate, | |
443 | .recalc_rate = dmn_clk_recalc_rate, | |
444 | .set_parent = dmn_clk_set_parent, | |
445 | .get_parent = dmn_clk_get_parent, | |
446 | }; | |
02c981c0 | 447 | |
198678b0 BD |
448 | static struct clk_init_data clk_mem_init = { |
449 | .name = "mem", | |
450 | .ops = &msi_ops, | |
451 | .parent_names = dmn_clk_parents, | |
452 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
453 | }; | |
02c981c0 | 454 | |
198678b0 BD |
455 | static struct clk_dmn clk_mem = { |
456 | .regofs = SIRFSOC_CLKC_MEM_CFG, | |
457 | .hw = { | |
458 | .init = &clk_mem_init, | |
459 | }, | |
460 | }; | |
02c981c0 | 461 | |
198678b0 BD |
462 | static struct clk_init_data clk_sys_init = { |
463 | .name = "sys", | |
464 | .ops = &msi_ops, | |
465 | .parent_names = dmn_clk_parents, | |
466 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
467 | .flags = CLK_SET_RATE_GATE, | |
468 | }; | |
02c981c0 | 469 | |
198678b0 BD |
470 | static struct clk_dmn clk_sys = { |
471 | .regofs = SIRFSOC_CLKC_SYS_CFG, | |
472 | .hw = { | |
473 | .init = &clk_sys_init, | |
474 | }, | |
475 | }; | |
02c981c0 | 476 | |
198678b0 BD |
477 | static struct clk_init_data clk_io_init = { |
478 | .name = "io", | |
479 | .ops = &msi_ops, | |
480 | .parent_names = dmn_clk_parents, | |
481 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
482 | }; | |
02c981c0 | 483 | |
198678b0 BD |
484 | static struct clk_dmn clk_io = { |
485 | .regofs = SIRFSOC_CLKC_IO_CFG, | |
486 | .hw = { | |
487 | .init = &clk_io_init, | |
488 | }, | |
489 | }; | |
02c981c0 BD |
490 | |
491 | static struct clk_ops cpu_ops = { | |
198678b0 BD |
492 | .set_parent = dmn_clk_set_parent, |
493 | .get_parent = dmn_clk_get_parent, | |
7bf21bc8 BS |
494 | .set_rate = cpu_clk_set_rate, |
495 | .round_rate = cpu_clk_round_rate, | |
496 | .recalc_rate = cpu_clk_recalc_rate, | |
02c981c0 BD |
497 | }; |
498 | ||
198678b0 BD |
499 | static struct clk_init_data clk_cpu_init = { |
500 | .name = "cpu", | |
02c981c0 | 501 | .ops = &cpu_ops, |
198678b0 BD |
502 | .parent_names = dmn_clk_parents, |
503 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
504 | .flags = CLK_SET_RATE_PARENT, | |
02c981c0 BD |
505 | }; |
506 | ||
198678b0 BD |
507 | static struct clk_dmn clk_cpu = { |
508 | .regofs = SIRFSOC_CLKC_CPU_CFG, | |
509 | .hw = { | |
510 | .init = &clk_cpu_init, | |
511 | }, | |
512 | }; | |
02c981c0 | 513 | |
198678b0 BD |
514 | static struct clk_ops dmn_ops = { |
515 | .is_enabled = std_clk_is_enabled, | |
516 | .enable = std_clk_enable, | |
517 | .disable = std_clk_disable, | |
518 | .set_rate = dmn_clk_set_rate, | |
519 | .round_rate = dmn_clk_round_rate, | |
520 | .recalc_rate = dmn_clk_recalc_rate, | |
521 | .set_parent = dmn_clk_set_parent, | |
522 | .get_parent = dmn_clk_get_parent, | |
02c981c0 BD |
523 | }; |
524 | ||
198678b0 BD |
525 | /* dsp, gfx, mm, lcd and vpp domain */ |
526 | ||
527 | static struct clk_init_data clk_dsp_init = { | |
528 | .name = "dsp", | |
529 | .ops = &dmn_ops, | |
530 | .parent_names = dmn_clk_parents, | |
531 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
02c981c0 BD |
532 | }; |
533 | ||
198678b0 BD |
534 | static struct clk_dmn clk_dsp = { |
535 | .regofs = SIRFSOC_CLKC_DSP_CFG, | |
536 | .enable_bit = 0, | |
537 | .hw = { | |
538 | .init = &clk_dsp_init, | |
539 | }, | |
02c981c0 BD |
540 | }; |
541 | ||
198678b0 BD |
542 | static struct clk_init_data clk_gfx_init = { |
543 | .name = "gfx", | |
544 | .ops = &dmn_ops, | |
545 | .parent_names = dmn_clk_parents, | |
546 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
02c981c0 BD |
547 | }; |
548 | ||
198678b0 BD |
549 | static struct clk_dmn clk_gfx = { |
550 | .regofs = SIRFSOC_CLKC_GFX_CFG, | |
551 | .enable_bit = 8, | |
552 | .hw = { | |
553 | .init = &clk_gfx_init, | |
554 | }, | |
555 | }; | |
02c981c0 | 556 | |
198678b0 BD |
557 | static struct clk_init_data clk_mm_init = { |
558 | .name = "mm", | |
559 | .ops = &dmn_ops, | |
560 | .parent_names = dmn_clk_parents, | |
561 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
562 | }; | |
02c981c0 | 563 | |
198678b0 BD |
564 | static struct clk_dmn clk_mm = { |
565 | .regofs = SIRFSOC_CLKC_MM_CFG, | |
566 | .enable_bit = 9, | |
567 | .hw = { | |
568 | .init = &clk_mm_init, | |
569 | }, | |
570 | }; | |
02c981c0 | 571 | |
7bf21bc8 BS |
572 | /* |
573 | * for atlas6, gfx2d holds the bit of prima2's clk_mm | |
574 | */ | |
575 | #define clk_gfx2d clk_mm | |
576 | ||
198678b0 BD |
577 | static struct clk_init_data clk_lcd_init = { |
578 | .name = "lcd", | |
579 | .ops = &dmn_ops, | |
580 | .parent_names = dmn_clk_parents, | |
581 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
582 | }; | |
02c981c0 | 583 | |
198678b0 BD |
584 | static struct clk_dmn clk_lcd = { |
585 | .regofs = SIRFSOC_CLKC_LCD_CFG, | |
586 | .enable_bit = 10, | |
587 | .hw = { | |
588 | .init = &clk_lcd_init, | |
589 | }, | |
590 | }; | |
02c981c0 | 591 | |
198678b0 BD |
592 | static struct clk_init_data clk_vpp_init = { |
593 | .name = "vpp", | |
594 | .ops = &dmn_ops, | |
595 | .parent_names = dmn_clk_parents, | |
596 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
597 | }; | |
02c981c0 | 598 | |
198678b0 BD |
599 | static struct clk_dmn clk_vpp = { |
600 | .regofs = SIRFSOC_CLKC_LCD_CFG, | |
601 | .enable_bit = 11, | |
602 | .hw = { | |
603 | .init = &clk_vpp_init, | |
604 | }, | |
605 | }; | |
02c981c0 | 606 | |
198678b0 BD |
607 | static struct clk_init_data clk_mmc01_init = { |
608 | .name = "mmc01", | |
609 | .ops = &dmn_ops, | |
610 | .parent_names = dmn_clk_parents, | |
611 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
612 | }; | |
02c981c0 | 613 | |
198678b0 BD |
614 | static struct clk_init_data clk_mmc23_init = { |
615 | .name = "mmc23", | |
616 | .ops = &dmn_ops, | |
617 | .parent_names = dmn_clk_parents, | |
618 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
619 | }; | |
02c981c0 | 620 | |
198678b0 BD |
621 | static struct clk_init_data clk_mmc45_init = { |
622 | .name = "mmc45", | |
623 | .ops = &dmn_ops, | |
624 | .parent_names = dmn_clk_parents, | |
625 | .num_parents = ARRAY_SIZE(dmn_clk_parents), | |
626 | }; | |
02c981c0 | 627 | |
198678b0 BD |
628 | /* |
629 | * peripheral controllers in io domain | |
630 | */ | |
631 | ||
632 | static int std_clk_is_enabled(struct clk_hw *hw) | |
02c981c0 | 633 | { |
198678b0 BD |
634 | u32 reg; |
635 | int bit; | |
636 | struct clk_std *clk = to_stdclk(hw); | |
02c981c0 | 637 | |
198678b0 BD |
638 | bit = clk->enable_bit % 32; |
639 | reg = clk->enable_bit / 32; | |
640 | reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); | |
02c981c0 | 641 | |
198678b0 | 642 | return !!(clkc_readl(reg) & BIT(bit)); |
02c981c0 | 643 | } |
02c981c0 | 644 | |
198678b0 | 645 | static int std_clk_enable(struct clk_hw *hw) |
02c981c0 | 646 | { |
198678b0 BD |
647 | u32 val, reg; |
648 | int bit; | |
649 | struct clk_std *clk = to_stdclk(hw); | |
02c981c0 | 650 | |
198678b0 BD |
651 | BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); |
652 | ||
653 | bit = clk->enable_bit % 32; | |
654 | reg = clk->enable_bit / 32; | |
655 | reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); | |
02c981c0 | 656 | |
198678b0 BD |
657 | val = clkc_readl(reg) | BIT(bit); |
658 | clkc_writel(val, reg); | |
659 | return 0; | |
02c981c0 | 660 | } |
02c981c0 | 661 | |
198678b0 | 662 | static void std_clk_disable(struct clk_hw *hw) |
02c981c0 | 663 | { |
198678b0 BD |
664 | u32 val, reg; |
665 | int bit; | |
666 | struct clk_std *clk = to_stdclk(hw); | |
02c981c0 | 667 | |
198678b0 | 668 | BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); |
02c981c0 | 669 | |
198678b0 BD |
670 | bit = clk->enable_bit % 32; |
671 | reg = clk->enable_bit / 32; | |
672 | reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); | |
02c981c0 | 673 | |
198678b0 BD |
674 | val = clkc_readl(reg) & ~BIT(bit); |
675 | clkc_writel(val, reg); | |
02c981c0 | 676 | } |
02c981c0 | 677 | |
45195b8f | 678 | static const char * const std_clk_io_parents[] = { |
198678b0 BD |
679 | "io", |
680 | }; | |
02c981c0 | 681 | |
198678b0 BD |
682 | static struct clk_ops ios_ops = { |
683 | .is_enabled = std_clk_is_enabled, | |
684 | .enable = std_clk_enable, | |
685 | .disable = std_clk_disable, | |
686 | }; | |
02c981c0 | 687 | |
7bf21bc8 BS |
688 | static struct clk_init_data clk_cphif_init = { |
689 | .name = "cphif", | |
690 | .ops = &ios_ops, | |
691 | .parent_names = std_clk_io_parents, | |
692 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
693 | }; | |
694 | ||
695 | static struct clk_std clk_cphif = { | |
696 | .enable_bit = 20, | |
697 | .hw = { | |
698 | .init = &clk_cphif_init, | |
699 | }, | |
700 | }; | |
701 | ||
198678b0 BD |
702 | static struct clk_init_data clk_dmac0_init = { |
703 | .name = "dmac0", | |
704 | .ops = &ios_ops, | |
705 | .parent_names = std_clk_io_parents, | |
706 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
707 | }; | |
02c981c0 | 708 | |
198678b0 BD |
709 | static struct clk_std clk_dmac0 = { |
710 | .enable_bit = 32, | |
711 | .hw = { | |
712 | .init = &clk_dmac0_init, | |
713 | }, | |
714 | }; | |
02c981c0 | 715 | |
198678b0 BD |
716 | static struct clk_init_data clk_dmac1_init = { |
717 | .name = "dmac1", | |
718 | .ops = &ios_ops, | |
719 | .parent_names = std_clk_io_parents, | |
720 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
721 | }; | |
722 | ||
723 | static struct clk_std clk_dmac1 = { | |
724 | .enable_bit = 33, | |
725 | .hw = { | |
726 | .init = &clk_dmac1_init, | |
727 | }, | |
728 | }; | |
729 | ||
198678b0 BD |
730 | static struct clk_init_data clk_audio_init = { |
731 | .name = "audio", | |
732 | .ops = &ios_ops, | |
733 | .parent_names = std_clk_io_parents, | |
734 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
735 | }; | |
736 | ||
737 | static struct clk_std clk_audio = { | |
738 | .enable_bit = 35, | |
739 | .hw = { | |
740 | .init = &clk_audio_init, | |
741 | }, | |
742 | }; | |
743 | ||
744 | static struct clk_init_data clk_uart0_init = { | |
745 | .name = "uart0", | |
746 | .ops = &ios_ops, | |
747 | .parent_names = std_clk_io_parents, | |
748 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
749 | }; | |
750 | ||
751 | static struct clk_std clk_uart0 = { | |
752 | .enable_bit = 36, | |
753 | .hw = { | |
754 | .init = &clk_uart0_init, | |
755 | }, | |
756 | }; | |
757 | ||
758 | static struct clk_init_data clk_uart1_init = { | |
759 | .name = "uart1", | |
760 | .ops = &ios_ops, | |
761 | .parent_names = std_clk_io_parents, | |
762 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
763 | }; | |
764 | ||
765 | static struct clk_std clk_uart1 = { | |
766 | .enable_bit = 37, | |
767 | .hw = { | |
768 | .init = &clk_uart1_init, | |
769 | }, | |
770 | }; | |
771 | ||
772 | static struct clk_init_data clk_uart2_init = { | |
773 | .name = "uart2", | |
774 | .ops = &ios_ops, | |
775 | .parent_names = std_clk_io_parents, | |
776 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
777 | }; | |
778 | ||
779 | static struct clk_std clk_uart2 = { | |
780 | .enable_bit = 38, | |
781 | .hw = { | |
782 | .init = &clk_uart2_init, | |
783 | }, | |
784 | }; | |
785 | ||
786 | static struct clk_init_data clk_usp0_init = { | |
787 | .name = "usp0", | |
788 | .ops = &ios_ops, | |
789 | .parent_names = std_clk_io_parents, | |
790 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
791 | }; | |
792 | ||
793 | static struct clk_std clk_usp0 = { | |
794 | .enable_bit = 39, | |
795 | .hw = { | |
796 | .init = &clk_usp0_init, | |
797 | }, | |
798 | }; | |
799 | ||
800 | static struct clk_init_data clk_usp1_init = { | |
801 | .name = "usp1", | |
802 | .ops = &ios_ops, | |
803 | .parent_names = std_clk_io_parents, | |
804 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
805 | }; | |
806 | ||
807 | static struct clk_std clk_usp1 = { | |
808 | .enable_bit = 40, | |
809 | .hw = { | |
810 | .init = &clk_usp1_init, | |
811 | }, | |
812 | }; | |
813 | ||
814 | static struct clk_init_data clk_usp2_init = { | |
815 | .name = "usp2", | |
816 | .ops = &ios_ops, | |
817 | .parent_names = std_clk_io_parents, | |
818 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
819 | }; | |
820 | ||
821 | static struct clk_std clk_usp2 = { | |
822 | .enable_bit = 41, | |
823 | .hw = { | |
824 | .init = &clk_usp2_init, | |
825 | }, | |
826 | }; | |
827 | ||
828 | static struct clk_init_data clk_vip_init = { | |
829 | .name = "vip", | |
830 | .ops = &ios_ops, | |
831 | .parent_names = std_clk_io_parents, | |
832 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
833 | }; | |
834 | ||
835 | static struct clk_std clk_vip = { | |
836 | .enable_bit = 42, | |
837 | .hw = { | |
838 | .init = &clk_vip_init, | |
839 | }, | |
840 | }; | |
841 | ||
842 | static struct clk_init_data clk_spi0_init = { | |
843 | .name = "spi0", | |
844 | .ops = &ios_ops, | |
845 | .parent_names = std_clk_io_parents, | |
846 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
847 | }; | |
848 | ||
849 | static struct clk_std clk_spi0 = { | |
850 | .enable_bit = 43, | |
851 | .hw = { | |
852 | .init = &clk_spi0_init, | |
853 | }, | |
854 | }; | |
855 | ||
856 | static struct clk_init_data clk_spi1_init = { | |
857 | .name = "spi1", | |
858 | .ops = &ios_ops, | |
859 | .parent_names = std_clk_io_parents, | |
860 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
861 | }; | |
862 | ||
863 | static struct clk_std clk_spi1 = { | |
864 | .enable_bit = 44, | |
865 | .hw = { | |
866 | .init = &clk_spi1_init, | |
867 | }, | |
868 | }; | |
869 | ||
870 | static struct clk_init_data clk_tsc_init = { | |
871 | .name = "tsc", | |
872 | .ops = &ios_ops, | |
873 | .parent_names = std_clk_io_parents, | |
874 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
875 | }; | |
876 | ||
877 | static struct clk_std clk_tsc = { | |
878 | .enable_bit = 45, | |
879 | .hw = { | |
880 | .init = &clk_tsc_init, | |
881 | }, | |
882 | }; | |
883 | ||
884 | static struct clk_init_data clk_i2c0_init = { | |
885 | .name = "i2c0", | |
886 | .ops = &ios_ops, | |
887 | .parent_names = std_clk_io_parents, | |
888 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
889 | }; | |
890 | ||
891 | static struct clk_std clk_i2c0 = { | |
892 | .enable_bit = 46, | |
893 | .hw = { | |
894 | .init = &clk_i2c0_init, | |
895 | }, | |
896 | }; | |
897 | ||
898 | static struct clk_init_data clk_i2c1_init = { | |
899 | .name = "i2c1", | |
900 | .ops = &ios_ops, | |
901 | .parent_names = std_clk_io_parents, | |
902 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
903 | }; | |
904 | ||
905 | static struct clk_std clk_i2c1 = { | |
906 | .enable_bit = 47, | |
907 | .hw = { | |
908 | .init = &clk_i2c1_init, | |
909 | }, | |
910 | }; | |
911 | ||
912 | static struct clk_init_data clk_pwmc_init = { | |
913 | .name = "pwmc", | |
914 | .ops = &ios_ops, | |
915 | .parent_names = std_clk_io_parents, | |
916 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
917 | }; | |
918 | ||
919 | static struct clk_std clk_pwmc = { | |
920 | .enable_bit = 48, | |
921 | .hw = { | |
922 | .init = &clk_pwmc_init, | |
923 | }, | |
924 | }; | |
925 | ||
926 | static struct clk_init_data clk_efuse_init = { | |
927 | .name = "efuse", | |
928 | .ops = &ios_ops, | |
929 | .parent_names = std_clk_io_parents, | |
930 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
931 | }; | |
932 | ||
933 | static struct clk_std clk_efuse = { | |
934 | .enable_bit = 49, | |
935 | .hw = { | |
936 | .init = &clk_efuse_init, | |
937 | }, | |
938 | }; | |
939 | ||
940 | static struct clk_init_data clk_pulse_init = { | |
941 | .name = "pulse", | |
942 | .ops = &ios_ops, | |
943 | .parent_names = std_clk_io_parents, | |
944 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
945 | }; | |
946 | ||
947 | static struct clk_std clk_pulse = { | |
948 | .enable_bit = 50, | |
949 | .hw = { | |
950 | .init = &clk_pulse_init, | |
951 | }, | |
952 | }; | |
953 | ||
45195b8f | 954 | static const char * const std_clk_dsp_parents[] = { |
198678b0 BD |
955 | "dsp", |
956 | }; | |
957 | ||
958 | static struct clk_init_data clk_gps_init = { | |
959 | .name = "gps", | |
960 | .ops = &ios_ops, | |
961 | .parent_names = std_clk_dsp_parents, | |
962 | .num_parents = ARRAY_SIZE(std_clk_dsp_parents), | |
963 | }; | |
964 | ||
965 | static struct clk_std clk_gps = { | |
966 | .enable_bit = 1, | |
967 | .hw = { | |
968 | .init = &clk_gps_init, | |
969 | }, | |
970 | }; | |
971 | ||
972 | static struct clk_init_data clk_mf_init = { | |
973 | .name = "mf", | |
974 | .ops = &ios_ops, | |
975 | .parent_names = std_clk_io_parents, | |
976 | .num_parents = ARRAY_SIZE(std_clk_io_parents), | |
977 | }; | |
978 | ||
979 | static struct clk_std clk_mf = { | |
980 | .enable_bit = 2, | |
981 | .hw = { | |
982 | .init = &clk_mf_init, | |
983 | }, | |
984 | }; | |
985 | ||
45195b8f | 986 | static const char * const std_clk_sys_parents[] = { |
198678b0 BD |
987 | "sys", |
988 | }; | |
989 | ||
990 | static struct clk_init_data clk_security_init = { | |
7bf21bc8 | 991 | .name = "security", |
198678b0 BD |
992 | .ops = &ios_ops, |
993 | .parent_names = std_clk_sys_parents, | |
994 | .num_parents = ARRAY_SIZE(std_clk_sys_parents), | |
995 | }; | |
996 | ||
997 | static struct clk_std clk_security = { | |
998 | .enable_bit = 19, | |
999 | .hw = { | |
1000 | .init = &clk_security_init, | |
1001 | }, | |
1002 | }; | |
1003 | ||
45195b8f | 1004 | static const char * const std_clk_usb_parents[] = { |
198678b0 BD |
1005 | "usb_pll", |
1006 | }; | |
1007 | ||
1008 | static struct clk_init_data clk_usb0_init = { | |
1009 | .name = "usb0", | |
1010 | .ops = &ios_ops, | |
1011 | .parent_names = std_clk_usb_parents, | |
1012 | .num_parents = ARRAY_SIZE(std_clk_usb_parents), | |
1013 | }; | |
1014 | ||
1015 | static struct clk_std clk_usb0 = { | |
1016 | .enable_bit = 16, | |
1017 | .hw = { | |
1018 | .init = &clk_usb0_init, | |
1019 | }, | |
1020 | }; | |
1021 | ||
1022 | static struct clk_init_data clk_usb1_init = { | |
1023 | .name = "usb1", | |
1024 | .ops = &ios_ops, | |
1025 | .parent_names = std_clk_usb_parents, | |
1026 | .num_parents = ARRAY_SIZE(std_clk_usb_parents), | |
1027 | }; | |
1028 | ||
1029 | static struct clk_std clk_usb1 = { | |
1030 | .enable_bit = 17, | |
1031 | .hw = { | |
1032 | .init = &clk_usb1_init, | |
1033 | }, | |
1034 | }; |