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5343325f DN |
1 | /* |
2 | * Copyright (C) 2015 Altera Corporation. All rights reserved | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
b0af24b5 | 16 | #include <linux/slab.h> |
5343325f DN |
17 | #include <linux/clk-provider.h> |
18 | #include <linux/io.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | ||
22 | #include "clk.h" | |
23 | ||
24 | /* Clock Manager offsets */ | |
25 | #define CLK_MGR_PLL_CLK_SRC_SHIFT 8 | |
26 | #define CLK_MGR_PLL_CLK_SRC_MASK 0x3 | |
27 | ||
28 | /* Clock bypass bits */ | |
29 | #define SOCFPGA_PLL_BG_PWRDWN 0 | |
30 | #define SOCFPGA_PLL_PWR_DOWN 1 | |
31 | #define SOCFPGA_PLL_EXT_ENA 2 | |
32 | #define SOCFPGA_PLL_DIVF_MASK 0x00001FFF | |
33 | #define SOCFPGA_PLL_DIVF_SHIFT 0 | |
34 | #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 | |
35 | #define SOCFPGA_PLL_DIVQ_SHIFT 16 | |
36 | #define SOCFGPA_MAX_PARENTS 5 | |
37 | ||
38 | #define SOCFPGA_MAIN_PLL_CLK "main_pll" | |
39 | #define SOCFPGA_PERIP_PLL_CLK "periph_pll" | |
40 | ||
41 | #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw) | |
42 | ||
43 | void __iomem *clk_mgr_a10_base_addr; | |
44 | ||
45 | static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, | |
46 | unsigned long parent_rate) | |
47 | { | |
48 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); | |
49 | unsigned long divf, divq, reg; | |
50 | unsigned long long vco_freq; | |
51 | ||
52 | /* read VCO1 reg for numerator and denominator */ | |
53 | reg = readl(socfpgaclk->hw.reg + 0x4); | |
54 | divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; | |
55 | divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; | |
56 | vco_freq = (unsigned long long)parent_rate * (divf + 1); | |
57 | do_div(vco_freq, (1 + divq)); | |
58 | return (unsigned long)vco_freq; | |
59 | } | |
60 | ||
61 | static u8 clk_pll_get_parent(struct clk_hw *hwclk) | |
62 | { | |
63 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); | |
64 | u32 pll_src; | |
65 | ||
66 | pll_src = readl(socfpgaclk->hw.reg); | |
67 | ||
68 | return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) & | |
69 | CLK_MGR_PLL_CLK_SRC_MASK; | |
70 | } | |
71 | ||
72 | static struct clk_ops clk_pll_ops = { | |
73 | .recalc_rate = clk_pll_recalc_rate, | |
74 | .get_parent = clk_pll_get_parent, | |
75 | }; | |
76 | ||
77 | static struct __init clk * __socfpga_pll_init(struct device_node *node, | |
78 | const struct clk_ops *ops) | |
79 | { | |
80 | u32 reg; | |
81 | struct clk *clk; | |
82 | struct socfpga_pll *pll_clk; | |
83 | const char *clk_name = node->name; | |
84 | const char *parent_name[SOCFGPA_MAX_PARENTS]; | |
85 | struct clk_init_data init; | |
86 | struct device_node *clkmgr_np; | |
87 | int rc; | |
88 | int i = 0; | |
89 | ||
90 | of_property_read_u32(node, "reg", ®); | |
91 | ||
92 | pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); | |
93 | if (WARN_ON(!pll_clk)) | |
94 | return NULL; | |
95 | ||
96 | clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); | |
97 | clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0); | |
98 | BUG_ON(!clk_mgr_a10_base_addr); | |
99 | pll_clk->hw.reg = clk_mgr_a10_base_addr + reg; | |
100 | ||
101 | of_property_read_string(node, "clock-output-names", &clk_name); | |
102 | ||
103 | init.name = clk_name; | |
104 | init.ops = ops; | |
105 | init.flags = 0; | |
106 | ||
107 | while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] = | |
108 | of_clk_get_parent_name(node, i)) != NULL) | |
109 | i++; | |
110 | init.num_parents = i; | |
111 | init.parent_names = parent_name; | |
112 | pll_clk->hw.hw.init = &init; | |
113 | ||
114 | pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; | |
115 | clk_pll_ops.enable = clk_gate_ops.enable; | |
116 | clk_pll_ops.disable = clk_gate_ops.disable; | |
117 | ||
118 | clk = clk_register(NULL, &pll_clk->hw.hw); | |
119 | if (WARN_ON(IS_ERR(clk))) { | |
120 | kfree(pll_clk); | |
121 | return NULL; | |
122 | } | |
123 | rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
124 | return clk; | |
125 | } | |
126 | ||
127 | void __init socfpga_a10_pll_init(struct device_node *node) | |
128 | { | |
129 | __socfpga_pll_init(node, &clk_pll_ops); | |
130 | } |