[deliverable/linux.git] / drivers / clk / socfpga / clk.h

/*
 * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
 *
 * based on drivers/clk/tegra/clk.h
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */

#ifndef __SOCFPGA_CLK_H
#define __SOCFPGA_CLK_H

#include <linux/clk-provider.h>

/* Clock Manager offsets */
#define CLKMGR_CTRL		0x0
#define CLKMGR_BYPASS		0x4
#define CLKMGR_DBCTRL		0x10
#define CLKMGR_L4SRC		0x70
#define CLKMGR_PERPLL_SRC	0xAC

#define SOCFPGA_MAX_PARENTS		5

#define streq(a, b) (strcmp((a), (b)) == 0)
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))

extern void __iomem *clk_mgr_base_addr;
extern void __iomem *clk_mgr_a10_base_addr;

void __init socfpga_pll_init(struct device_node *node);
void __init socfpga_periph_init(struct device_node *node);
void __init socfpga_gate_init(struct device_node *node);
void socfpga_a10_pll_init(struct device_node *node);
void socfpga_a10_periph_init(struct device_node *node);
void socfpga_a10_gate_init(struct device_node *node);

struct socfpga_pll {
	struct clk_gate	hw;
};

struct socfpga_gate_clk {
	struct clk_gate hw;
	char *parent_name;
	u32 fixed_div;
	void __iomem *div_reg;
	struct regmap *sys_mgr_base_addr;
	u32 width;	/* only valid if div_reg != 0 */
	u32 shift;	/* only valid if div_reg != 0 */
	u32 clk_phase[2];
};

struct socfpga_periph_clk {
	struct clk_gate hw;
	char *parent_name;
	u32 fixed_div;
	void __iomem *div_reg;
	u32 width;      /* only valid if div_reg != 0 */
	u32 shift;      /* only valid if div_reg != 0 */
};

#endif /* SOCFPGA_CLK_H */
Commit	Line	Data
97259e99 ST	1	/*
	2	* Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
	3	*
	4	* based on drivers/clk/tegra/clk.h
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	*/
	16
	17	#ifndef __SOCFPGA_CLK_H
	18	#define __SOCFPGA_CLK_H
	19
	20	#include <linux/clk-provider.h>
97259e99 ST	21
	22	/* Clock Manager offsets */
	23	#define CLKMGR_CTRL 0x0
	24	#define CLKMGR_BYPASS 0x4
34d5003b	25	#define CLKMGR_DBCTRL 0x10
97259e99 ST	26	#define CLKMGR_L4SRC 0x70
	27	#define CLKMGR_PERPLL_SRC 0xAC
	28
5611a5ba	29	#define SOCFPGA_MAX_PARENTS 5
97259e99	30
5611a5ba DN	31	#define streq(a, b) (strcmp((a), (b)) == 0)
	32	#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
	33	((((smplsel) & 0x7) << 3) \| (((drvsel) & 0x7) << 0))
	34
97259e99	35	extern void __iomem *clk_mgr_base_addr;
5343325f	36	extern void __iomem *clk_mgr_a10_base_addr;
97259e99 ST	37
	38	void __init socfpga_pll_init(struct device_node *node);
	39	void __init socfpga_periph_init(struct device_node *node);
	40	void __init socfpga_gate_init(struct device_node *node);
5343325f DN	41	void socfpga_a10_pll_init(struct device_node *node);
	42	void socfpga_a10_periph_init(struct device_node *node);
	43	void socfpga_a10_gate_init(struct device_node *node);
97259e99 ST	44
	45	struct socfpga_pll {
	46	struct clk_gate hw;
	47	};
	48
	49	struct socfpga_gate_clk {
	50	struct clk_gate hw;
	51	char *parent_name;
	52	u32 fixed_div;
	53	void __iomem *div_reg;
5343325f	54	struct regmap *sys_mgr_base_addr;
97259e99 ST	55	u32 width; /* only valid if div_reg != 0 */
	56	u32 shift; /* only valid if div_reg != 0 */
	57	u32 clk_phase[2];
	58	};
	59
	60	struct socfpga_periph_clk {
	61	struct clk_gate hw;
	62	char *parent_name;
	63	u32 fixed_div;
0691bb1b DN	64	void __iomem *div_reg;
	65	u32 width; /* only valid if div_reg != 0 */
	66	u32 shift; /* only valid if div_reg != 0 */
97259e99 ST	67	};
	68
	69	#endif /* SOCFPGA_CLK_H */