[deliverable/linux.git] / drivers / clk / sunxi / clk-factors.c

/*
 * Copyright (C) 2013 Emilio López <emilio@elopez.com.ar>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Adjustable factor-based clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>

#include <linux/delay.h>

#include "clk-factors.h"

/*
 * DOC: basic adjustable factor-based clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is adjustable.
 *        clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
 * parent - fixed parent.  No clk_set_parent support
 */

#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)

#define SETMASK(len, pos)		(((1U << (len)) - 1) << (pos))
#define CLRMASK(len, pos)		(~(SETMASK(len, pos)))
#define FACTOR_GET(bit, len, reg)	(((reg) & SETMASK(len, bit)) >> (bit))

#define FACTOR_SET(bit, len, reg, val) \
	(((reg) & CLRMASK(len, bit)) | (val << (bit)))

static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
					     unsigned long parent_rate)
{
	u8 n = 1, k = 0, p = 0, m = 0;
	u32 reg;
	unsigned long rate;
	struct clk_factors *factors = to_clk_factors(hw);
	struct clk_factors_config *config = factors->config;

	/* Fetch the register value */
	reg = readl(factors->reg);

	/* Get each individual factor if applicable */
	if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE)
		n = FACTOR_GET(config->nshift, config->nwidth, reg);
	if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE)
		k = FACTOR_GET(config->kshift, config->kwidth, reg);
	if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE)
		m = FACTOR_GET(config->mshift, config->mwidth, reg);
	if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
		p = FACTOR_GET(config->pshift, config->pwidth, reg);

	/* Calculate the rate */
	rate = (parent_rate * n * (k + 1) >> p) / (m + 1);

	return rate;
}

static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long *parent_rate)
{
	struct clk_factors *factors = to_clk_factors(hw);
	factors->get_factors((u32 *)&rate, (u32)*parent_rate,
			     NULL, NULL, NULL, NULL);

	return rate;
}

static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{
	u8 n = 0, k = 0, m = 0, p = 0;
	u32 reg;
	struct clk_factors *factors = to_clk_factors(hw);
	struct clk_factors_config *config = factors->config;
	unsigned long flags = 0;

	factors->get_factors((u32 *)&rate, (u32)parent_rate, &n, &k, &m, &p);

	if (factors->lock)
		spin_lock_irqsave(factors->lock, flags);

	/* Fetch the register value */
	reg = readl(factors->reg);

	/* Set up the new factors - macros do not do anything if width is 0 */
	reg = FACTOR_SET(config->nshift, config->nwidth, reg, n);
	reg = FACTOR_SET(config->kshift, config->kwidth, reg, k);
	reg = FACTOR_SET(config->mshift, config->mwidth, reg, m);
	reg = FACTOR_SET(config->pshift, config->pwidth, reg, p);

	/* Apply them now */
	writel(reg, factors->reg);

	/* delay 500us so pll stabilizes */
	__delay((rate >> 20) * 500 / 2);

	if (factors->lock)
		spin_unlock_irqrestore(factors->lock, flags);

	return 0;
}

const struct clk_ops clk_factors_ops = {
	.recalc_rate = clk_factors_recalc_rate,
	.round_rate = clk_factors_round_rate,
	.set_rate = clk_factors_set_rate,
};
Commit	Line	Data
e874a669 EL	1	/*
	2	* Copyright (C) 2013 Emilio López <emilio@elopez.com.ar>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Adjustable factor-based clock implementation
	9	*/
	10
	11	#include <linux/clk-provider.h>
	12	#include <linux/module.h>
	13	#include <linux/slab.h>
	14	#include <linux/io.h>
	15	#include <linux/err.h>
	16	#include <linux/string.h>
	17
	18	#include <linux/delay.h>
	19
	20	#include "clk-factors.h"
	21
	22	/*
	23	* DOC: basic adjustable factor-based clock that cannot gate
	24	*
	25	* Traits of this clock:
	26	* prepare - clk_prepare only ensures that parents are prepared
	27	* enable - clk_enable only ensures that parents are enabled
	28	* rate - rate is adjustable.
	29	* clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
	30	* parent - fixed parent. No clk_set_parent support
	31	*/
	32
e874a669 EL	33	#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
e874a669 EL	34
c518e84c	35	#define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
e874a669 EL	36	#define CLRMASK(len, pos) (~(SETMASK(len, pos)))
	37	#define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
	38
	39	#define FACTOR_SET(bit, len, reg, val) \
	40	(((reg) & CLRMASK(len, bit)) \| (val << (bit)))
	41
	42	static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
	43	unsigned long parent_rate)
	44	{
	45	u8 n = 1, k = 0, p = 0, m = 0;
	46	u32 reg;
	47	unsigned long rate;
	48	struct clk_factors *factors = to_clk_factors(hw);
	49	struct clk_factors_config *config = factors->config;
	50
	51	/* Fetch the register value */
	52	reg = readl(factors->reg);
	53
	54	/* Get each individual factor if applicable */
	55	if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE)
	56	n = FACTOR_GET(config->nshift, config->nwidth, reg);
	57	if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE)
	58	k = FACTOR_GET(config->kshift, config->kwidth, reg);
	59	if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE)
	60	m = FACTOR_GET(config->mshift, config->mwidth, reg);
	61	if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
	62	p = FACTOR_GET(config->pshift, config->pwidth, reg);
	63
	64	/* Calculate the rate */
	65	rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
	66
	67	return rate;
	68	}
	69
	70	static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
	71	unsigned long *parent_rate)
	72	{
	73	struct clk_factors *factors = to_clk_factors(hw);
	74	factors->get_factors((u32 )&rate, (u32)parent_rate,
	75	NULL, NULL, NULL, NULL);
	76
	77	return rate;
	78	}
	79
	80	static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
	81	unsigned long parent_rate)
	82	{
12ef06af	83	u8 n = 0, k = 0, m = 0, p = 0;
e874a669 EL	84	u32 reg;
	85	struct clk_factors *factors = to_clk_factors(hw);
	86	struct clk_factors_config *config = factors->config;
	87	unsigned long flags = 0;
	88
	89	factors->get_factors((u32 *)&rate, (u32)parent_rate, &n, &k, &m, &p);
	90
	91	if (factors->lock)
	92	spin_lock_irqsave(factors->lock, flags);
	93
	94	/* Fetch the register value */
	95	reg = readl(factors->reg);
	96
	97	/* Set up the new factors - macros do not do anything if width is 0 */
	98	reg = FACTOR_SET(config->nshift, config->nwidth, reg, n);
	99	reg = FACTOR_SET(config->kshift, config->kwidth, reg, k);
	100	reg = FACTOR_SET(config->mshift, config->mwidth, reg, m);
	101	reg = FACTOR_SET(config->pshift, config->pwidth, reg, p);
	102
	103	/* Apply them now */
	104	writel(reg, factors->reg);
	105
	106	/* delay 500us so pll stabilizes */
	107	__delay((rate >> 20) * 500 / 2);
	108
	109	if (factors->lock)
	110	spin_unlock_irqrestore(factors->lock, flags);
	111
	112	return 0;
	113	}
	114
40a5dcba	115	const struct clk_ops clk_factors_ops = {
e874a669 EL	116	.recalc_rate = clk_factors_recalc_rate,
	117	.round_rate = clk_factors_round_rate,
	118	.set_rate = clk_factors_set_rate,
	119	};