Commit | Line | Data |
---|---|---|
992a56e4 MR |
1 | /* |
2 | * Copyright 2013 Emilio López | |
3 | * | |
4 | * Emilio López <emilio@elopez.com.ar> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
9dfefe8c | 17 | #include <linux/clk.h> |
992a56e4 | 18 | #include <linux/clk-provider.h> |
37e1041f | 19 | #include <linux/of_address.h> |
6ea3953d | 20 | #include <linux/platform_device.h> |
9dfefe8c | 21 | #include <linux/slab.h> |
992a56e4 MR |
22 | |
23 | #include "clk-factors.h" | |
24 | ||
25 | /** | |
26 | * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks | |
27 | * MOD0 rate is calculated as follows | |
28 | * rate = (parent_rate >> p) / (m + 1); | |
29 | */ | |
30 | ||
31 | static void sun4i_a10_get_mod0_factors(u32 *freq, u32 parent_rate, | |
32 | u8 *n, u8 *k, u8 *m, u8 *p) | |
33 | { | |
34 | u8 div, calcm, calcp; | |
35 | ||
36 | /* These clocks can only divide, so we will never be able to achieve | |
37 | * frequencies higher than the parent frequency */ | |
38 | if (*freq > parent_rate) | |
39 | *freq = parent_rate; | |
40 | ||
41 | div = DIV_ROUND_UP(parent_rate, *freq); | |
42 | ||
43 | if (div < 16) | |
44 | calcp = 0; | |
45 | else if (div / 2 < 16) | |
46 | calcp = 1; | |
47 | else if (div / 4 < 16) | |
48 | calcp = 2; | |
49 | else | |
50 | calcp = 3; | |
51 | ||
52 | calcm = DIV_ROUND_UP(div, 1 << calcp); | |
53 | ||
54 | *freq = (parent_rate >> calcp) / calcm; | |
55 | ||
56 | /* we were called to round the frequency, we can now return */ | |
57 | if (n == NULL) | |
58 | return; | |
59 | ||
60 | *m = calcm - 1; | |
61 | *p = calcp; | |
62 | } | |
63 | ||
64 | /* user manual says "n" but it's really "p" */ | |
65 | static struct clk_factors_config sun4i_a10_mod0_config = { | |
66 | .mshift = 0, | |
67 | .mwidth = 4, | |
68 | .pshift = 16, | |
69 | .pwidth = 2, | |
70 | }; | |
71 | ||
6ea3953d | 72 | static const struct factors_data sun4i_a10_mod0_data = { |
992a56e4 MR |
73 | .enable = 31, |
74 | .mux = 24, | |
e94f8cb3 | 75 | .muxmask = BIT(1) | BIT(0), |
992a56e4 MR |
76 | .table = &sun4i_a10_mod0_config, |
77 | .getter = sun4i_a10_get_mod0_factors, | |
78 | }; | |
79 | ||
80 | static DEFINE_SPINLOCK(sun4i_a10_mod0_lock); | |
81 | ||
82 | static void __init sun4i_a10_mod0_setup(struct device_node *node) | |
83 | { | |
7c74c220 HG |
84 | void __iomem *reg; |
85 | ||
86 | reg = of_iomap(node, 0); | |
87 | if (!reg) { | |
6ea3953d HG |
88 | /* |
89 | * This happens with mod0 clk nodes instantiated through | |
90 | * mfd, as those do not have their resources assigned at | |
91 | * CLK_OF_DECLARE time yet, so do not print an error. | |
92 | */ | |
7c74c220 HG |
93 | return; |
94 | } | |
95 | ||
96 | sunxi_factors_register(node, &sun4i_a10_mod0_data, | |
97 | &sun4i_a10_mod0_lock, reg); | |
992a56e4 MR |
98 | } |
99 | CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup); | |
eaa18f5d | 100 | |
6ea3953d HG |
101 | static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev) |
102 | { | |
103 | struct device_node *np = pdev->dev.of_node; | |
104 | struct resource *r; | |
105 | void __iomem *reg; | |
106 | ||
107 | if (!np) | |
108 | return -ENODEV; | |
109 | ||
110 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
111 | reg = devm_ioremap_resource(&pdev->dev, r); | |
112 | if (IS_ERR(reg)) | |
113 | return PTR_ERR(reg); | |
114 | ||
115 | sunxi_factors_register(np, &sun4i_a10_mod0_data, | |
116 | &sun4i_a10_mod0_lock, reg); | |
117 | return 0; | |
118 | } | |
119 | ||
120 | static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = { | |
121 | { .compatible = "allwinner,sun4i-a10-mod0-clk" }, | |
122 | { /* sentinel */ } | |
123 | }; | |
124 | ||
125 | static struct platform_driver sun4i_a10_mod0_clk_driver = { | |
126 | .driver = { | |
127 | .name = "sun4i-a10-mod0-clk", | |
128 | .of_match_table = sun4i_a10_mod0_clk_dt_ids, | |
129 | }, | |
130 | .probe = sun4i_a10_mod0_clk_probe, | |
131 | }; | |
77459a0f | 132 | builtin_platform_driver(sun4i_a10_mod0_clk_driver); |
6ea3953d | 133 | |
61af4d8d CYT |
134 | static const struct factors_data sun9i_a80_mod0_data __initconst = { |
135 | .enable = 31, | |
136 | .mux = 24, | |
137 | .muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0), | |
138 | .table = &sun4i_a10_mod0_config, | |
139 | .getter = sun4i_a10_get_mod0_factors, | |
140 | }; | |
141 | ||
142 | static void __init sun9i_a80_mod0_setup(struct device_node *node) | |
143 | { | |
144 | void __iomem *reg; | |
145 | ||
146 | reg = of_io_request_and_map(node, 0, of_node_full_name(node)); | |
147 | if (IS_ERR(reg)) { | |
148 | pr_err("Could not get registers for mod0-clk: %s\n", | |
149 | node->name); | |
150 | return; | |
151 | } | |
152 | ||
153 | sunxi_factors_register(node, &sun9i_a80_mod0_data, | |
154 | &sun4i_a10_mod0_lock, reg); | |
155 | } | |
156 | CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup); | |
157 | ||
eaa18f5d MR |
158 | static DEFINE_SPINLOCK(sun5i_a13_mbus_lock); |
159 | ||
160 | static void __init sun5i_a13_mbus_setup(struct device_node *node) | |
161 | { | |
7c74c220 HG |
162 | struct clk *mbus; |
163 | void __iomem *reg; | |
164 | ||
165 | reg = of_iomap(node, 0); | |
166 | if (!reg) { | |
167 | pr_err("Could not get registers for a13-mbus-clk\n"); | |
168 | return; | |
169 | } | |
170 | ||
171 | mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data, | |
172 | &sun5i_a13_mbus_lock, reg); | |
eaa18f5d MR |
173 | |
174 | /* The MBUS clocks needs to be always enabled */ | |
175 | __clk_get(mbus); | |
176 | clk_prepare_enable(mbus); | |
177 | } | |
178 | CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup); | |
37e1041f | 179 | |
37e1041f MR |
180 | struct mmc_phase { |
181 | struct clk_hw hw; | |
6b0b8ccf | 182 | u8 offset; |
37e1041f | 183 | void __iomem *reg; |
37e1041f MR |
184 | spinlock_t *lock; |
185 | }; | |
186 | ||
187 | #define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw) | |
188 | ||
189 | static int mmc_get_phase(struct clk_hw *hw) | |
190 | { | |
191 | struct clk *mmc, *mmc_parent, *clk = hw->clk; | |
192 | struct mmc_phase *phase = to_mmc_phase(hw); | |
193 | unsigned int mmc_rate, mmc_parent_rate; | |
194 | u16 step, mmc_div; | |
195 | u32 value; | |
196 | u8 delay; | |
197 | ||
198 | value = readl(phase->reg); | |
6b0b8ccf | 199 | delay = (value >> phase->offset) & 0x3; |
37e1041f MR |
200 | |
201 | if (!delay) | |
202 | return 180; | |
203 | ||
204 | /* Get the main MMC clock */ | |
205 | mmc = clk_get_parent(clk); | |
206 | if (!mmc) | |
207 | return -EINVAL; | |
208 | ||
209 | /* And its rate */ | |
210 | mmc_rate = clk_get_rate(mmc); | |
211 | if (!mmc_rate) | |
212 | return -EINVAL; | |
213 | ||
214 | /* Now, get the MMC parent (most likely some PLL) */ | |
215 | mmc_parent = clk_get_parent(mmc); | |
216 | if (!mmc_parent) | |
217 | return -EINVAL; | |
218 | ||
219 | /* And its rate */ | |
220 | mmc_parent_rate = clk_get_rate(mmc_parent); | |
221 | if (!mmc_parent_rate) | |
222 | return -EINVAL; | |
223 | ||
224 | /* Get MMC clock divider */ | |
225 | mmc_div = mmc_parent_rate / mmc_rate; | |
226 | ||
227 | step = DIV_ROUND_CLOSEST(360, mmc_div); | |
228 | return delay * step; | |
229 | } | |
230 | ||
231 | static int mmc_set_phase(struct clk_hw *hw, int degrees) | |
232 | { | |
233 | struct clk *mmc, *mmc_parent, *clk = hw->clk; | |
234 | struct mmc_phase *phase = to_mmc_phase(hw); | |
235 | unsigned int mmc_rate, mmc_parent_rate; | |
236 | unsigned long flags; | |
237 | u32 value; | |
238 | u8 delay; | |
239 | ||
240 | /* Get the main MMC clock */ | |
241 | mmc = clk_get_parent(clk); | |
242 | if (!mmc) | |
243 | return -EINVAL; | |
244 | ||
245 | /* And its rate */ | |
246 | mmc_rate = clk_get_rate(mmc); | |
247 | if (!mmc_rate) | |
248 | return -EINVAL; | |
249 | ||
250 | /* Now, get the MMC parent (most likely some PLL) */ | |
251 | mmc_parent = clk_get_parent(mmc); | |
252 | if (!mmc_parent) | |
253 | return -EINVAL; | |
254 | ||
255 | /* And its rate */ | |
256 | mmc_parent_rate = clk_get_rate(mmc_parent); | |
257 | if (!mmc_parent_rate) | |
258 | return -EINVAL; | |
259 | ||
260 | if (degrees != 180) { | |
261 | u16 step, mmc_div; | |
262 | ||
263 | /* Get MMC clock divider */ | |
264 | mmc_div = mmc_parent_rate / mmc_rate; | |
265 | ||
266 | /* | |
267 | * We can only outphase the clocks by multiple of the | |
268 | * PLL's period. | |
269 | * | |
270 | * Since the MMC clock in only a divider, and the | |
271 | * formula to get the outphasing in degrees is deg = | |
272 | * 360 * delta / period | |
273 | * | |
274 | * If we simplify this formula, we can see that the | |
275 | * only thing that we're concerned about is the number | |
276 | * of period we want to outphase our clock from, and | |
277 | * the divider set by the MMC clock. | |
278 | */ | |
279 | step = DIV_ROUND_CLOSEST(360, mmc_div); | |
280 | delay = DIV_ROUND_CLOSEST(degrees, step); | |
281 | } else { | |
282 | delay = 0; | |
283 | } | |
284 | ||
285 | spin_lock_irqsave(phase->lock, flags); | |
286 | value = readl(phase->reg); | |
6b0b8ccf MR |
287 | value &= ~GENMASK(phase->offset + 3, phase->offset); |
288 | value |= delay << phase->offset; | |
37e1041f MR |
289 | writel(value, phase->reg); |
290 | spin_unlock_irqrestore(phase->lock, flags); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | static const struct clk_ops mmc_clk_ops = { | |
296 | .get_phase = mmc_get_phase, | |
297 | .set_phase = mmc_set_phase, | |
298 | }; | |
299 | ||
eb378df7 CYT |
300 | /* |
301 | * sunxi_mmc_setup - Common setup function for mmc module clocks | |
302 | * | |
303 | * The only difference between module clocks on different platforms is the | |
304 | * width of the mux register bits and the valid values, which are passed in | |
305 | * through struct factors_data. The phase clocks parts are identical. | |
306 | */ | |
307 | static void __init sunxi_mmc_setup(struct device_node *node, | |
308 | const struct factors_data *data, | |
309 | spinlock_t *lock) | |
6b0b8ccf MR |
310 | { |
311 | struct clk_onecell_data *clk_data; | |
312 | const char *parent; | |
313 | void __iomem *reg; | |
314 | int i; | |
37e1041f | 315 | |
6b0b8ccf MR |
316 | reg = of_io_request_and_map(node, 0, of_node_full_name(node)); |
317 | if (IS_ERR(reg)) { | |
318 | pr_err("Couldn't map the %s clock registers\n", node->name); | |
319 | return; | |
320 | } | |
37e1041f | 321 | |
6b0b8ccf MR |
322 | clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL); |
323 | if (!clk_data) | |
324 | return; | |
37e1041f | 325 | |
6b0b8ccf MR |
326 | clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL); |
327 | if (!clk_data->clks) | |
328 | goto err_free_data; | |
329 | ||
330 | clk_data->clk_num = 3; | |
eb378df7 | 331 | clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg); |
6b0b8ccf MR |
332 | if (!clk_data->clks[0]) |
333 | goto err_free_clks; | |
334 | ||
335 | parent = __clk_get_name(clk_data->clks[0]); | |
336 | ||
337 | for (i = 1; i < 3; i++) { | |
338 | struct clk_init_data init = { | |
339 | .num_parents = 1, | |
340 | .parent_names = &parent, | |
341 | .ops = &mmc_clk_ops, | |
342 | }; | |
343 | struct mmc_phase *phase; | |
344 | ||
345 | phase = kmalloc(sizeof(*phase), GFP_KERNEL); | |
346 | if (!phase) | |
347 | continue; | |
348 | ||
349 | phase->hw.init = &init; | |
350 | phase->reg = reg; | |
eb378df7 | 351 | phase->lock = lock; |
6b0b8ccf MR |
352 | |
353 | if (i == 1) | |
354 | phase->offset = 8; | |
355 | else | |
356 | phase->offset = 20; | |
357 | ||
358 | if (of_property_read_string_index(node, "clock-output-names", | |
359 | i, &init.name)) | |
360 | init.name = node->name; | |
361 | ||
362 | clk_data->clks[i] = clk_register(NULL, &phase->hw); | |
363 | if (IS_ERR(clk_data->clks[i])) { | |
364 | kfree(phase); | |
365 | continue; | |
366 | } | |
367 | } | |
37e1041f | 368 | |
6b0b8ccf | 369 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
37e1041f MR |
370 | |
371 | return; | |
372 | ||
6b0b8ccf MR |
373 | err_free_clks: |
374 | kfree(clk_data->clks); | |
375 | err_free_data: | |
376 | kfree(clk_data); | |
37e1041f | 377 | } |
eb378df7 CYT |
378 | |
379 | static DEFINE_SPINLOCK(sun4i_a10_mmc_lock); | |
380 | ||
381 | static void __init sun4i_a10_mmc_setup(struct device_node *node) | |
382 | { | |
383 | sunxi_mmc_setup(node, &sun4i_a10_mod0_data, &sun4i_a10_mmc_lock); | |
384 | } | |
6b0b8ccf | 385 | CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup); |
61af4d8d CYT |
386 | |
387 | static DEFINE_SPINLOCK(sun9i_a80_mmc_lock); | |
388 | ||
389 | static void __init sun9i_a80_mmc_setup(struct device_node *node) | |
390 | { | |
391 | sunxi_mmc_setup(node, &sun9i_a80_mod0_data, &sun9i_a80_mmc_lock); | |
392 | } | |
393 | CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup); |