projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branches 'asoc/fix/rt5677', 'asoc/fix/st', 'asoc/fix/sun4i...
[deliverable/linux.git] / drivers / clk / tegra / clk-tegra114.c
CommitLineData
2cb5efef
PDS		 1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
2cb5efef 18#include <linux/clk-provider.h>
2cb5efef
PDS		 19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/delay.h>
25c9ded6 22#include <linux/export.h>
2cb5efef 23#include <linux/clk/tegra.h>
c9e2d69a 24#include <dt-bindings/clock/tegra114-car.h>
2cb5efef
PDS		 25
26#include "clk.h"
6609dbe4 27#include "clk-id.h"
2cb5efef 28
1c472d8e 29#define RST_DFLL_DVCO 0x2F4
25c9ded6
PW		 30#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
31#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
32#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
2cb5efef 33
1c472d8e
PW		 34/* RST_DFLL_DVCO bitfields */
35#define DVFS_DFLL_RESET_SHIFT 0
36
25c9ded6
PW		 37/* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
38#define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */
39#define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */
40#define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */
41#define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */
42#define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */
43#define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */
44
45/* CPU_FINETRIM_R bitfields */
46#define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */
47#define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
48#define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */
49#define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
50#define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */
51#define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
52#define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */
53#define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
54#define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */
55#define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
56#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */
57#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
58
d5ff89a8
PDS		 59#define TEGRA114_CLK_PERIPH_BANKS 5
60
2cb5efef
PDS		 61#define PLLC_BASE 0x80
62#define PLLC_MISC2 0x88
63#define PLLC_MISC 0x8c
64#define PLLC2_BASE 0x4e8
65#define PLLC2_MISC 0x4ec
66#define PLLC3_BASE 0x4fc
67#define PLLC3_MISC 0x500
68#define PLLM_BASE 0x90
69#define PLLM_MISC 0x9c
70#define PLLP_BASE 0xa0
71#define PLLP_MISC 0xac
72#define PLLX_BASE 0xe0
73#define PLLX_MISC 0xe4
74#define PLLX_MISC2 0x514
75#define PLLX_MISC3 0x518
76#define PLLD_BASE 0xd0
77#define PLLD_MISC 0xdc
78#define PLLD2_BASE 0x4b8
79#define PLLD2_MISC 0x4bc
80#define PLLE_BASE 0xe8
81#define PLLE_MISC 0xec
82#define PLLA_BASE 0xb0
83#define PLLA_MISC 0xbc
84#define PLLU_BASE 0xc0
85#define PLLU_MISC 0xcc
86#define PLLRE_BASE 0x4c4
87#define PLLRE_MISC 0x4c8
88
89#define PLL_MISC_LOCK_ENABLE 18
90#define PLLC_MISC_LOCK_ENABLE 24
91#define PLLDU_MISC_LOCK_ENABLE 22
92#define PLLE_MISC_LOCK_ENABLE 9
93#define PLLRE_MISC_LOCK_ENABLE 30
94
95#define PLLC_IDDQ_BIT 26
96#define PLLX_IDDQ_BIT 3
97#define PLLRE_IDDQ_BIT 16
98
99#define PLL_BASE_LOCK BIT(27)
100#define PLLE_MISC_LOCK BIT(11)
101#define PLLRE_MISC_LOCK BIT(24)
102#define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
103
104#define PLLE_AUX 0x48c
105#define PLLC_OUT 0x84
106#define PLLM_OUT 0x94
2cb5efef 107
2cb5efef
PDS		 108#define OSC_CTRL 0x50
109#define OSC_CTRL_OSC_FREQ_SHIFT 28
110#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
111
112#define PLLXC_SW_MAX_P 6
113
114#define CCLKG_BURST_POLICY 0x368
2cb5efef
PDS		 115
116#define UTMIP_PLL_CFG2 0x488
117#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
118#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
119#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
120#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
121#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
122
123#define UTMIP_PLL_CFG1 0x484
124#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
125#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
126#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
127#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
128#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
129#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
130#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
131
132#define UTMIPLL_HW_PWRDN_CFG0 0x52c
133#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
134#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
135#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
136#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
137#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
138#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
139#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
140#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
141
2cb5efef 142#define CLK_SOURCE_CSITE 0x1d4
2cb5efef
PDS		 143#define CLK_SOURCE_EMC 0x19c
144
d53442e9
PDS		 145/* PLLM override registers */
146#define PMC_PLLM_WB0_OVERRIDE 0x1dc
147#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
148
31972fd9
JL		 149/* Tegra CPU clock and reset control regs */
150#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
151
167d5366
PDS		 152#define MUX8(_name, _parents, _offset, \
153 _clk_num, _gate_flags, _clk_id) \
154 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
155 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
156 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
157 NULL)
158
ad7d1140
JL		 159#ifdef CONFIG_PM_SLEEP
160static struct cpu_clk_suspend_context {
161 u32 clk_csite_src;
0017f447
JL		 162 u32 cclkg_burst;
163 u32 cclkg_divider;
ad7d1140
JL		 164} tegra114_cpu_clk_sctx;
165#endif
166
2cb5efef
PDS		 167static void __iomem *clk_base;
168static void __iomem *pmc_base;
169
170static DEFINE_SPINLOCK(pll_d_lock);
171static DEFINE_SPINLOCK(pll_d2_lock);
172static DEFINE_SPINLOCK(pll_u_lock);
2cb5efef 173static DEFINE_SPINLOCK(pll_re_lock);
4f4f85fa 174static DEFINE_SPINLOCK(emc_lock);
2cb5efef 175
fd428ad8
PDS		 176static struct div_nmp pllxc_nmp = {
177 .divm_shift = 0,
178 .divm_width = 8,
179 .divn_shift = 8,
180 .divn_width = 8,
181 .divp_shift = 20,
182 .divp_width = 4,
183};
184
2cb5efef
PDS		 185static struct pdiv_map pllxc_p[] = {
186 { .pdiv = 1, .hw_val = 0 },
187 { .pdiv = 2, .hw_val = 1 },
188 { .pdiv = 3, .hw_val = 2 },
189 { .pdiv = 4, .hw_val = 3 },
190 { .pdiv = 5, .hw_val = 4 },
191 { .pdiv = 6, .hw_val = 5 },
192 { .pdiv = 8, .hw_val = 6 },
193 { .pdiv = 10, .hw_val = 7 },
194 { .pdiv = 12, .hw_val = 8 },
195 { .pdiv = 16, .hw_val = 9 },
196 { .pdiv = 12, .hw_val = 10 },
197 { .pdiv = 16, .hw_val = 11 },
198 { .pdiv = 20, .hw_val = 12 },
199 { .pdiv = 24, .hw_val = 13 },
200 { .pdiv = 32, .hw_val = 14 },
201 { .pdiv = 0, .hw_val = 0 },
202};
203
204static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
205 { 12000000, 624000000, 104, 0, 2},
206 { 12000000, 600000000, 100, 0, 2},
207 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
208 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
209 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
210 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
211 { 0, 0, 0, 0, 0, 0 },
212};
213
214static struct tegra_clk_pll_params pll_c_params = {
215 .input_min = 12000000,
216 .input_max = 800000000,
217 .cf_min = 12000000,
218 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
219 .vco_min = 600000000,
220 .vco_max = 1400000000,
221 .base_reg = PLLC_BASE,
222 .misc_reg = PLLC_MISC,
223 .lock_mask = PLL_BASE_LOCK,
224 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
225 .lock_delay = 300,
226 .iddq_reg = PLLC_MISC,
227 .iddq_bit_idx = PLLC_IDDQ_BIT,
228 .max_p = PLLXC_SW_MAX_P,
229 .dyn_ramp_reg = PLLC_MISC2,
230 .stepa_shift = 17,
231 .stepb_shift = 9,
232 .pdiv_tohw = pllxc_p,
fd428ad8 233 .div_nmp = &pllxc_nmp,
ebe142b2
PDS		 234 .freq_table = pll_c_freq_table,
235 .flags = TEGRA_PLL_USE_LOCK,
fd428ad8
PDS		 236};
237
238static struct div_nmp pllcx_nmp = {
239 .divm_shift = 0,
240 .divm_width = 2,
241 .divn_shift = 8,
242 .divn_width = 8,
243 .divp_shift = 20,
244 .divp_width = 3,
2cb5efef
PDS		 245};
246
247static struct pdiv_map pllc_p[] = {
248 { .pdiv = 1, .hw_val = 0 },
249 { .pdiv = 2, .hw_val = 1 },
250 { .pdiv = 4, .hw_val = 3 },
251 { .pdiv = 8, .hw_val = 5 },
252 { .pdiv = 16, .hw_val = 7 },
253 { .pdiv = 0, .hw_val = 0 },
254};
255
256static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
257 {12000000, 600000000, 100, 0, 2},
258 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
259 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
260 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
261 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
262 {0, 0, 0, 0, 0, 0},
263};
264
265static struct tegra_clk_pll_params pll_c2_params = {
266 .input_min = 12000000,
267 .input_max = 48000000,
268 .cf_min = 12000000,
269 .cf_max = 19200000,
270 .vco_min = 600000000,
271 .vco_max = 1200000000,
272 .base_reg = PLLC2_BASE,
273 .misc_reg = PLLC2_MISC,
274 .lock_mask = PLL_BASE_LOCK,
275 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
276 .lock_delay = 300,
277 .pdiv_tohw = pllc_p,
fd428ad8
PDS		 278 .div_nmp = &pllcx_nmp,
279 .max_p = 7,
2cb5efef
PDS		 280 .ext_misc_reg[0] = 0x4f0,
281 .ext_misc_reg[1] = 0x4f4,
282 .ext_misc_reg[2] = 0x4f8,
ebe142b2
PDS		 283 .freq_table = pll_cx_freq_table,
284 .flags = TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 285};
286
287static struct tegra_clk_pll_params pll_c3_params = {
288 .input_min = 12000000,
289 .input_max = 48000000,
290 .cf_min = 12000000,
291 .cf_max = 19200000,
292 .vco_min = 600000000,
293 .vco_max = 1200000000,
294 .base_reg = PLLC3_BASE,
295 .misc_reg = PLLC3_MISC,
296 .lock_mask = PLL_BASE_LOCK,
297 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
298 .lock_delay = 300,
299 .pdiv_tohw = pllc_p,
fd428ad8
PDS		 300 .div_nmp = &pllcx_nmp,
301 .max_p = 7,
2cb5efef
PDS		 302 .ext_misc_reg[0] = 0x504,
303 .ext_misc_reg[1] = 0x508,
304 .ext_misc_reg[2] = 0x50c,
ebe142b2
PDS		 305 .freq_table = pll_cx_freq_table,
306 .flags = TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 307};
308
fd428ad8
PDS		 309static struct div_nmp pllm_nmp = {
310 .divm_shift = 0,
311 .divm_width = 8,
d53442e9 312 .override_divm_shift = 0,
fd428ad8
PDS		 313 .divn_shift = 8,
314 .divn_width = 8,
d53442e9 315 .override_divn_shift = 8,
fd428ad8
PDS		 316 .divp_shift = 20,
317 .divp_width = 1,
d53442e9 318 .override_divp_shift = 27,
fd428ad8
PDS		 319};
320
2cb5efef
PDS		 321static struct pdiv_map pllm_p[] = {
322 { .pdiv = 1, .hw_val = 0 },
323 { .pdiv = 2, .hw_val = 1 },
324 { .pdiv = 0, .hw_val = 0 },
325};
326
327static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
328 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */
329 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */
330 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */
331 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */
332 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
333 {0, 0, 0, 0, 0, 0},
334};
335
336static struct tegra_clk_pll_params pll_m_params = {
337 .input_min = 12000000,
338 .input_max = 500000000,
339 .cf_min = 12000000,
340 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
341 .vco_min = 400000000,
342 .vco_max = 1066000000,
343 .base_reg = PLLM_BASE,
344 .misc_reg = PLLM_MISC,
345 .lock_mask = PLL_BASE_LOCK,
346 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
347 .lock_delay = 300,
348 .max_p = 2,
349 .pdiv_tohw = pllm_p,
fd428ad8 350 .div_nmp = &pllm_nmp,
d53442e9
PDS		 351 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
352 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
ebe142b2
PDS		 353 .freq_table = pll_m_freq_table,
354 .flags = TEGRA_PLL_USE_LOCK,
fd428ad8
PDS		 355};
356
357static struct div_nmp pllp_nmp = {
358 .divm_shift = 0,
359 .divm_width = 5,
360 .divn_shift = 8,
361 .divn_width = 10,
362 .divp_shift = 20,
363 .divp_width = 3,
2cb5efef
PDS		 364};
365
366static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
367 {12000000, 216000000, 432, 12, 1, 8},
368 {13000000, 216000000, 432, 13, 1, 8},
369 {16800000, 216000000, 360, 14, 1, 8},
370 {19200000, 216000000, 360, 16, 1, 8},
371 {26000000, 216000000, 432, 26, 1, 8},
372 {0, 0, 0, 0, 0, 0},
373};
374
375static struct tegra_clk_pll_params pll_p_params = {
376 .input_min = 2000000,
377 .input_max = 31000000,
378 .cf_min = 1000000,
379 .cf_max = 6000000,
380 .vco_min = 200000000,
381 .vco_max = 700000000,
382 .base_reg = PLLP_BASE,
383 .misc_reg = PLLP_MISC,
384 .lock_mask = PLL_BASE_LOCK,
385 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
386 .lock_delay = 300,
fd428ad8 387 .div_nmp = &pllp_nmp,
ebe142b2
PDS		 388 .freq_table = pll_p_freq_table,
389 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
390 .fixed_rate = 408000000,
2cb5efef
PDS		 391};
392
393static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
394 {9600000, 282240000, 147, 5, 0, 4},
395 {9600000, 368640000, 192, 5, 0, 4},
396 {9600000, 240000000, 200, 8, 0, 8},
397
398 {28800000, 282240000, 245, 25, 0, 8},
399 {28800000, 368640000, 320, 25, 0, 8},
400 {28800000, 240000000, 200, 24, 0, 8},
401 {0, 0, 0, 0, 0, 0},
402};
403
404
405static struct tegra_clk_pll_params pll_a_params = {
406 .input_min = 2000000,
407 .input_max = 31000000,
408 .cf_min = 1000000,
409 .cf_max = 6000000,
410 .vco_min = 200000000,
411 .vco_max = 700000000,
412 .base_reg = PLLA_BASE,
413 .misc_reg = PLLA_MISC,
414 .lock_mask = PLL_BASE_LOCK,
415 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
416 .lock_delay = 300,
fd428ad8 417 .div_nmp = &pllp_nmp,
ebe142b2
PDS		 418 .freq_table = pll_a_freq_table,
419 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 420};
421
422static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
423 {12000000, 216000000, 864, 12, 2, 12},
424 {13000000, 216000000, 864, 13, 2, 12},
425 {16800000, 216000000, 720, 14, 2, 12},
426 {19200000, 216000000, 720, 16, 2, 12},
427 {26000000, 216000000, 864, 26, 2, 12},
428
429 {12000000, 594000000, 594, 12, 0, 12},
430 {13000000, 594000000, 594, 13, 0, 12},
431 {16800000, 594000000, 495, 14, 0, 12},
432 {19200000, 594000000, 495, 16, 0, 12},
433 {26000000, 594000000, 594, 26, 0, 12},
434
435 {12000000, 1000000000, 1000, 12, 0, 12},
436 {13000000, 1000000000, 1000, 13, 0, 12},
437 {19200000, 1000000000, 625, 12, 0, 12},
438 {26000000, 1000000000, 1000, 26, 0, 12},
439
440 {0, 0, 0, 0, 0, 0},
441};
442
443static struct tegra_clk_pll_params pll_d_params = {
444 .input_min = 2000000,
445 .input_max = 40000000,
446 .cf_min = 1000000,
447 .cf_max = 6000000,
448 .vco_min = 500000000,
449 .vco_max = 1000000000,
450 .base_reg = PLLD_BASE,
451 .misc_reg = PLLD_MISC,
452 .lock_mask = PLL_BASE_LOCK,
453 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
454 .lock_delay = 1000,
fd428ad8 455 .div_nmp = &pllp_nmp,
ebe142b2
PDS		 456 .freq_table = pll_d_freq_table,
457 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
458 TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 459};
460
461static struct tegra_clk_pll_params pll_d2_params = {
462 .input_min = 2000000,
463 .input_max = 40000000,
464 .cf_min = 1000000,
465 .cf_max = 6000000,
466 .vco_min = 500000000,
467 .vco_max = 1000000000,
468 .base_reg = PLLD2_BASE,
469 .misc_reg = PLLD2_MISC,
470 .lock_mask = PLL_BASE_LOCK,
471 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
472 .lock_delay = 1000,
fd428ad8 473 .div_nmp = &pllp_nmp,
ebe142b2
PDS		 474 .freq_table = pll_d_freq_table,
475 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
476 TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 477};
478
479static struct pdiv_map pllu_p[] = {
480 { .pdiv = 1, .hw_val = 1 },
481 { .pdiv = 2, .hw_val = 0 },
482 { .pdiv = 0, .hw_val = 0 },
483};
484
fd428ad8
PDS		 485static struct div_nmp pllu_nmp = {
486 .divm_shift = 0,
487 .divm_width = 5,
488 .divn_shift = 8,
489 .divn_width = 10,
490 .divp_shift = 20,
491 .divp_width = 1,
492};
493
2cb5efef
PDS		 494static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
495 {12000000, 480000000, 960, 12, 0, 12},
496 {13000000, 480000000, 960, 13, 0, 12},
497 {16800000, 480000000, 400, 7, 0, 5},
498 {19200000, 480000000, 200, 4, 0, 3},
499 {26000000, 480000000, 960, 26, 0, 12},
500 {0, 0, 0, 0, 0, 0},
501};
502
503static struct tegra_clk_pll_params pll_u_params = {
504 .input_min = 2000000,
505 .input_max = 40000000,
506 .cf_min = 1000000,
507 .cf_max = 6000000,
508 .vco_min = 480000000,
509 .vco_max = 960000000,
510 .base_reg = PLLU_BASE,
511 .misc_reg = PLLU_MISC,
512 .lock_mask = PLL_BASE_LOCK,
513 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
514 .lock_delay = 1000,
515 .pdiv_tohw = pllu_p,
fd428ad8 516 .div_nmp = &pllu_nmp,
ebe142b2
PDS		 517 .freq_table = pll_u_freq_table,
518 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
519 TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 520};
521
522static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
523 /* 1 GHz */
524 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
525 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
526 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
527 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
528 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
529
530 {0, 0, 0, 0, 0, 0},
531};
532
533static struct tegra_clk_pll_params pll_x_params = {
534 .input_min = 12000000,
535 .input_max = 800000000,
536 .cf_min = 12000000,
537 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
538 .vco_min = 700000000,
539 .vco_max = 2400000000U,
540 .base_reg = PLLX_BASE,
541 .misc_reg = PLLX_MISC,
542 .lock_mask = PLL_BASE_LOCK,
543 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
544 .lock_delay = 300,
545 .iddq_reg = PLLX_MISC3,
546 .iddq_bit_idx = PLLX_IDDQ_BIT,
547 .max_p = PLLXC_SW_MAX_P,
548 .dyn_ramp_reg = PLLX_MISC2,
549 .stepa_shift = 16,
550 .stepb_shift = 24,
551 .pdiv_tohw = pllxc_p,
fd428ad8 552 .div_nmp = &pllxc_nmp,
ebe142b2
PDS		 553 .freq_table = pll_x_freq_table,
554 .flags = TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 555};
556
557static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
558 /* PLLE special case: use cpcon field to store cml divider value */
559 {336000000, 100000000, 100, 21, 16, 11},
560 {312000000, 100000000, 200, 26, 24, 13},
8e9cc80a 561 {12000000, 100000000, 200, 1, 24, 13},
2cb5efef
PDS		 562 {0, 0, 0, 0, 0, 0},
563};
564
fd428ad8
PDS		 565static struct div_nmp plle_nmp = {
566 .divm_shift = 0,
567 .divm_width = 8,
568 .divn_shift = 8,
569 .divn_width = 8,
570 .divp_shift = 24,
571 .divp_width = 4,
572};
573
2cb5efef
PDS		 574static struct tegra_clk_pll_params pll_e_params = {
575 .input_min = 12000000,
576 .input_max = 1000000000,
577 .cf_min = 12000000,
578 .cf_max = 75000000,
579 .vco_min = 1600000000,
580 .vco_max = 2400000000U,
581 .base_reg = PLLE_BASE,
582 .misc_reg = PLLE_MISC,
583 .aux_reg = PLLE_AUX,
584 .lock_mask = PLLE_MISC_LOCK,
585 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
586 .lock_delay = 300,
fd428ad8 587 .div_nmp = &plle_nmp,
ebe142b2
PDS		 588 .freq_table = pll_e_freq_table,
589 .flags = TEGRA_PLL_FIXED,
590 .fixed_rate = 100000000,
fd428ad8
PDS		 591};
592
593static struct div_nmp pllre_nmp = {
594 .divm_shift = 0,
595 .divm_width = 8,
596 .divn_shift = 8,
597 .divn_width = 8,
598 .divp_shift = 16,
599 .divp_width = 4,
2cb5efef
PDS		 600};
601
602static struct tegra_clk_pll_params pll_re_vco_params = {
603 .input_min = 12000000,
604 .input_max = 1000000000,
605 .cf_min = 12000000,
606 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
607 .vco_min = 300000000,
608 .vco_max = 600000000,
609 .base_reg = PLLRE_BASE,
610 .misc_reg = PLLRE_MISC,
611 .lock_mask = PLLRE_MISC_LOCK,
612 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
613 .lock_delay = 300,
614 .iddq_reg = PLLRE_MISC,
615 .iddq_bit_idx = PLLRE_IDDQ_BIT,
fd428ad8 616 .div_nmp = &pllre_nmp,
ebe142b2 617 .flags = TEGRA_PLL_USE_LOCK,
2cb5efef
PDS		 618};
619
2cb5efef
PDS		 620/* possible OSC frequencies in Hz */
621static unsigned long tegra114_input_freq[] = {
622 [0] = 13000000,
623 [1] = 16800000,
624 [4] = 19200000,
625 [5] = 38400000,
626 [8] = 12000000,
627 [9] = 48000000,
628 [12] = 260000000,
629};
630
631#define MASK(x) (BIT(x) - 1)
632
2cb5efef
PDS		 633struct utmi_clk_param {
634 /* Oscillator Frequency in KHz */
635 u32 osc_frequency;
636 /* UTMIP PLL Enable Delay Count */
637 u8 enable_delay_count;
638 /* UTMIP PLL Stable count */
639 u8 stable_count;
640 /* UTMIP PLL Active delay count */
641 u8 active_delay_count;
642 /* UTMIP PLL Xtal frequency count */
643 u8 xtal_freq_count;
644};
645
646static const struct utmi_clk_param utmi_parameters[] = {
647 {.osc_frequency = 13000000, .enable_delay_count = 0x02,
648 .stable_count = 0x33, .active_delay_count = 0x05,
649 .xtal_freq_count = 0x7F},
650 {.osc_frequency = 19200000, .enable_delay_count = 0x03,
651 .stable_count = 0x4B, .active_delay_count = 0x06,
652 .xtal_freq_count = 0xBB},
653 {.osc_frequency = 12000000, .enable_delay_count = 0x02,
654 .stable_count = 0x2F, .active_delay_count = 0x04,
655 .xtal_freq_count = 0x76},
656 {.osc_frequency = 26000000, .enable_delay_count = 0x04,
657 .stable_count = 0x66, .active_delay_count = 0x09,
658 .xtal_freq_count = 0xFE},
659 {.osc_frequency = 16800000, .enable_delay_count = 0x03,
660 .stable_count = 0x41, .active_delay_count = 0x0A,
661 .xtal_freq_count = 0xA4},
662};
663
664/* peripheral mux definitions */
665
2cb5efef
PDS		 666static const char *mux_plld_out0_plld2_out0[] = {
667 "pll_d_out0", "pll_d2_out0",
668};
669#define mux_plld_out0_plld2_out0_idx NULL
670
2cb5efef
PDS		 671static const char *mux_pllmcp_clkm[] = {
672 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
673};
674
675static const struct clk_div_table pll_re_div_table[] = {
676 { .val = 0, .div = 1 },
677 { .val = 1, .div = 2 },
678 { .val = 2, .div = 3 },
679 { .val = 3, .div = 4 },
680 { .val = 4, .div = 5 },
681 { .val = 5, .div = 6 },
682 { .val = 0, .div = 0 },
683};
684
6609dbe4
PDS		 685static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
686 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
687 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
688 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
689 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
20e7c323 690 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
6609dbe4
PDS		 691 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
692 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
693 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
20e7c323
AB		 694 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
695 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
6609dbe4
PDS		 696 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
697 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
698 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
699 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
700 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
701 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
702 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
703 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
704 [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
705 [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
706 [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
707 [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
708 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
709 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
710 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
711 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
712 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
713 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
714 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
715 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
6609dbe4
PDS		 716 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
717 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
718 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
719 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
720 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
721 [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
722 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
723 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
724 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
725 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
726 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
727 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
728 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
729 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
20e7c323 730 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
6609dbe4
PDS		 731 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
732 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
733 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
734 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
735 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
736 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
737 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
738 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
6609dbe4
PDS		 739 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
740 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
741 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
742 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
743 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
744 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
745 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
746 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
747 [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
748 [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
749 [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
750 [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
751 [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
752 [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
753 [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
754 [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
755 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
756 [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
757 [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
758 [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
759 [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
760 [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
761 [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
762 [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
763 [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
764 [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
765 [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
766 [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
767 [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
768 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
769 [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
770 [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
771 [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
772 [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
773 [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
774 [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
775 [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
776 [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
777 [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
778 [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
779 [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
780 [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
781 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
782 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
783 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
6609dbe4
PDS		 784 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
785 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
786 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
787 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
788 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
789 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
790 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
791 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
792 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
793 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
794 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
795 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
796 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
797 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
798 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
799 [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
800 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
801 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
802 [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
803 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
804 [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
805 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
806 [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
807 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
808 [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
809 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
810 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
811 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
812 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
813 [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
814 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
815 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
816 [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
817 [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
818 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
819 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
820 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
821 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
822 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
823 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
824 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
825 [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
826 [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
827 [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
828 [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
829 [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
830 [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
831 [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
832 [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
833 [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
834 [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
835 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
836 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
837 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
838 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
5c992afc 839 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
6609dbe4
PDS		 840 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
841 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
842 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
843 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
844 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
845 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
846 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
847 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
848 [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
849 [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
850 [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
851 [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
852 [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
853 [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
854 [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
855 [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
856 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
857 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
858 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
859 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
860 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
861};
862
73d37e4c
PDS		 863static struct tegra_devclk devclks[] __initdata = {
864 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
865 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
866 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
867 { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
868 { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
869 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
870 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
871 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
872 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
873 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
874 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
875 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
876 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
877 { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
878 { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
879 { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
880 { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
881 { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
882 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
883 { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
884 { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
885 { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
886 { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
887 { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
888 { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
889 { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
890 { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
891 { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
892 { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
893 { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
894 { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
895 { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
896 { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
897 { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
898 { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
899 { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
900 { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
901 { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
902 { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
903 { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
904 { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
905 { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
906 { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
907 { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
908 { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
909 { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
910 { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
911 { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
912 { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
913 { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
914 { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
915 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
916 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
917 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
918 { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
919 { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
920 { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
921 { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
922 { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
923 { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
5ab5d404 924 { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
73d37e4c
PDS		 925 { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
926 { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
927};
928
167d5366
PDS		 929static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
930 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
931};
932static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
933 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
934};
935
88d909be
RK		 936static struct tegra_audio_clk_info tegra114_audio_plls[] = {
937 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
938};
939
343a607c 940static struct clk **clks;
2cb5efef
PDS		 941
942static unsigned long osc_freq;
943static unsigned long pll_ref_freq;
944
2cb5efef
PDS		 945static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
946{
947 struct clk *clk;
948
949 /* clk_32k */
950 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
951 32768);
c9e2d69a 952 clks[TEGRA114_CLK_CLK_32K] = clk;
2cb5efef
PDS		 953
954 /* clk_m_div2 */
955 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
956 CLK_SET_RATE_PARENT, 1, 2);
c9e2d69a 957 clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
2cb5efef
PDS		 958
959 /* clk_m_div4 */
960 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
961 CLK_SET_RATE_PARENT, 1, 4);
c9e2d69a 962 clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
2cb5efef
PDS		 963
964}
965
966static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
967{
968 u32 reg;
969 int i;
970
971 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
972 if (osc_freq == utmi_parameters[i].osc_frequency)
973 break;
974 }
975
976 if (i >= ARRAY_SIZE(utmi_parameters)) {
977 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
978 osc_freq);
979 return;
980 }
981
982 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
983
984 /* Program UTMIP PLL stable and active counts */
985 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
986 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
987 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
988
989 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
990
991 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
992 active_delay_count);
993
994 /* Remove power downs from UTMIP PLL control bits */
995 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
996 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
997 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
998
999 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1000
1001 /* Program UTMIP PLL delay and oscillator frequency counts */
1002 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1003 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1004
1005 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1006 enable_delay_count);
1007
1008 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1009 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1010 xtal_freq_count);
1011
1012 /* Remove power downs from UTMIP PLL control bits */
1013 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1014 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1015 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1016 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1017 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1018
1019 /* Setup HW control of UTMIPLL */
1020 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1021 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1022 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1023 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1024 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1025
1026 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1027 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1028 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1029 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1030
1031 udelay(1);
1032
1033 /* Setup SW override of UTMIPLL assuming USB2.0
1034 ports are assigned to USB2 */
1035 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1036 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1037 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1038 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1039
1040 udelay(1);
1041
1042 /* Enable HW control UTMIPLL */
1043 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1044 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1045 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1046}
1047
2cb5efef
PDS		 1048static void __init tegra114_pll_init(void __iomem *clk_base,
1049 void __iomem *pmc)
1050{
1051 u32 val;
1052 struct clk *clk;
1053
1054 /* PLLC */
04edb099 1055 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
ebe142b2 1056 pmc, 0, &pll_c_params, NULL);
04edb099
PDS		 1057 clks[TEGRA114_CLK_PLL_C] = clk;
1058
1059 /* PLLC_OUT1 */
1060 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1061 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1062 8, 8, 1, NULL);
1063 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1064 clk_base + PLLC_OUT, 1, 0,
1065 CLK_SET_RATE_PARENT, 0, NULL);
04edb099 1066 clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
2cb5efef
PDS		 1067
1068 /* PLLC2 */
ebe142b2
PDS		 1069 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1070 &pll_c2_params, NULL);
c9e2d69a 1071 clks[TEGRA114_CLK_PLL_C2] = clk;
2cb5efef
PDS		 1072
1073 /* PLLC3 */
ebe142b2
PDS		 1074 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1075 &pll_c3_params, NULL);
c9e2d69a 1076 clks[TEGRA114_CLK_PLL_C3] = clk;
2cb5efef 1077
2cb5efef 1078 /* PLLM */
2cb5efef 1079 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
ebe142b2
PDS		 1080 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1081 &pll_m_params, NULL);
c9e2d69a 1082 clks[TEGRA114_CLK_PLL_M] = clk;
2cb5efef
PDS		 1083
1084 /* PLLM_OUT1 */
1085 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1086 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1087 8, 8, 1, NULL);
1088 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1089 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1090 CLK_SET_RATE_PARENT, 0, NULL);
c9e2d69a 1091 clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
2cb5efef
PDS		 1092
1093 /* PLLM_UD */
1094 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1095 CLK_SET_RATE_PARENT, 1, 1);
1096
2cb5efef
PDS		 1097 /* PLLU */
1098 val = readl(clk_base + pll_u_params.base_reg);
1099 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1100 writel(val, clk_base + pll_u_params.base_reg);
1101
1102 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
ebe142b2 1103 &pll_u_params, &pll_u_lock);
c9e2d69a 1104 clks[TEGRA114_CLK_PLL_U] = clk;
2cb5efef
PDS		 1105
1106 tegra114_utmi_param_configure(clk_base);
1107
1108 /* PLLU_480M */
1109 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1110 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1111 22, 0, &pll_u_lock);
c9e2d69a 1112 clks[TEGRA114_CLK_PLL_U_480M] = clk;
2cb5efef
PDS		 1113
1114 /* PLLU_60M */
1115 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1116 CLK_SET_RATE_PARENT, 1, 8);
c9e2d69a 1117 clks[TEGRA114_CLK_PLL_U_60M] = clk;
2cb5efef
PDS		 1118
1119 /* PLLU_48M */
1120 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1121 CLK_SET_RATE_PARENT, 1, 10);
c9e2d69a 1122 clks[TEGRA114_CLK_PLL_U_48M] = clk;
2cb5efef
PDS		 1123
1124 /* PLLU_12M */
1125 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1126 CLK_SET_RATE_PARENT, 1, 40);
c9e2d69a 1127 clks[TEGRA114_CLK_PLL_U_12M] = clk;
2cb5efef
PDS		 1128
1129 /* PLLD */
1130 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
ebe142b2 1131 &pll_d_params, &pll_d_lock);
c9e2d69a 1132 clks[TEGRA114_CLK_PLL_D] = clk;
2cb5efef
PDS		 1133
1134 /* PLLD_OUT0 */
1135 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1136 CLK_SET_RATE_PARENT, 1, 2);
c9e2d69a 1137 clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
2cb5efef
PDS		 1138
1139 /* PLLD2 */
1140 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
ebe142b2 1141 &pll_d2_params, &pll_d2_lock);
c9e2d69a 1142 clks[TEGRA114_CLK_PLL_D2] = clk;
2cb5efef
PDS		 1143
1144 /* PLLD2_OUT0 */
1145 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1146 CLK_SET_RATE_PARENT, 1, 2);
c9e2d69a 1147 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
2cb5efef 1148
2cb5efef 1149 /* PLLRE */
2cb5efef 1150 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
ebe142b2 1151 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
c9e2d69a 1152 clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
2cb5efef
PDS		 1153
1154 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1155 clk_base + PLLRE_BASE, 16, 4, 0,
1156 pll_re_div_table, &pll_re_lock);
c9e2d69a 1157 clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
2cb5efef
PDS		 1158
1159 /* PLLE */
8e9cc80a 1160 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
ebe142b2 1161 clk_base, 0, &pll_e_params, NULL);
c9e2d69a 1162 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
2cb5efef
PDS		 1163}
1164
167d5366
PDS		 1165#define CLK_SOURCE_VI_SENSOR 0x1a8
1166
1167static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1168 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
1169};
1170
76ebc134
PDS		 1171static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1172 void __iomem *pmc_base)
2cb5efef 1173{
2cb5efef 1174 struct clk *clk;
167d5366
PDS		 1175 struct tegra_periph_init_data *data;
1176 int i;
76ebc134 1177
5c992afc
AB		 1178 /* xusb_ss_div2 */
1179 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1180 1, 2);
1181 clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
76ebc134
PDS		 1182
1183 /* dsia mux */
2cb5efef 1184 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
819c1de3
JH		 1185 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1186 CLK_SET_RATE_NO_REPARENT,
2cb5efef 1187 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
c9e2d69a 1188 clks[TEGRA114_CLK_DSIA_MUX] = clk;
2cb5efef 1189
76ebc134 1190 /* dsib mux */
2cb5efef 1191 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
819c1de3
JH		 1192 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1193 CLK_SET_RATE_NO_REPARENT,
2cb5efef 1194 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
c9e2d69a 1195 clks[TEGRA114_CLK_DSIB_MUX] = clk;
2cb5efef 1196
b270491e
MZ		 1197 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1198 0, 48, periph_clk_enb_refcnt);
1199 clks[TEGRA114_CLK_DSIA] = clk;
1200
1201 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1202 0, 82, periph_clk_enb_refcnt);
1203 clks[TEGRA114_CLK_DSIB] = clk;
1204
76ebc134 1205 /* emc mux */
2cb5efef 1206 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
819c1de3
JH		 1207 ARRAY_SIZE(mux_pllmcp_clkm),
1208 CLK_SET_RATE_NO_REPARENT,
2cb5efef 1209 clk_base + CLK_SOURCE_EMC,
4f4f85fa
TR		 1210 29, 3, 0, &emc_lock);
1211
1212 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1213 &emc_lock);
1214 clks[TEGRA114_CLK_MC] = clk;
d5ff89a8 1215
167d5366
PDS		 1216 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1217 data = &tegra_periph_clk_list[i];
1218 clk = tegra_clk_register_periph(data->name,
1219 data->p.parent_names, data->num_parents,
1220 &data->periph, clk_base, data->offset, data->flags);
1221 clks[data->clk_id] = clk;
1222 }
1223
76ebc134
PDS		 1224 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1225 &pll_p_params);
2cb5efef
PDS		 1226}
1227
31972fd9
JL		 1228/* Tegra114 CPU clock and reset control functions */
1229static void tegra114_wait_cpu_in_reset(u32 cpu)
1230{
1231 unsigned int reg;
1232
1233 do {
1234 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1235 cpu_relax();
1236 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1237}
6bb18c53 1238
31972fd9
JL		 1239static void tegra114_disable_cpu_clock(u32 cpu)
1240{
1241 /* flow controller would take care in the power sequence. */
1242}
1243
ad7d1140
JL		 1244#ifdef CONFIG_PM_SLEEP
1245static void tegra114_cpu_clock_suspend(void)
1246{
1247 /* switch coresite to clk_m, save off original source */
1248 tegra114_cpu_clk_sctx.clk_csite_src =
1249 readl(clk_base + CLK_SOURCE_CSITE);
1250 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
0017f447
JL		 1251
1252 tegra114_cpu_clk_sctx.cclkg_burst =
1253 readl(clk_base + CCLKG_BURST_POLICY);
1254 tegra114_cpu_clk_sctx.cclkg_divider =
1255 readl(clk_base + CCLKG_BURST_POLICY + 4);
ad7d1140
JL		 1256}
1257
1258static void tegra114_cpu_clock_resume(void)
1259{
1260 writel(tegra114_cpu_clk_sctx.clk_csite_src,
1261 clk_base + CLK_SOURCE_CSITE);
0017f447
JL		 1262
1263 writel(tegra114_cpu_clk_sctx.cclkg_burst,
1264 clk_base + CCLKG_BURST_POLICY);
1265 writel(tegra114_cpu_clk_sctx.cclkg_divider,
1266 clk_base + CCLKG_BURST_POLICY + 4);
ad7d1140
JL		 1267}
1268#endif
1269
31972fd9
JL		 1270static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
1271 .wait_for_reset = tegra114_wait_cpu_in_reset,
1272 .disable_clock = tegra114_disable_cpu_clock,
ad7d1140
JL		 1273#ifdef CONFIG_PM_SLEEP
1274 .suspend = tegra114_cpu_clock_suspend,
1275 .resume = tegra114_cpu_clock_resume,
1276#endif
31972fd9 1277};
2cb5efef
PDS		 1278
1279static const struct of_device_id pmc_match[] __initconst = {
1280 { .compatible = "nvidia,tegra114-pmc" },
1281 {},
1282};
1283
9e60121f
PW		 1284/*
1285 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
1286 * breaks
1287 */
056dfcf6 1288static struct tegra_clk_init_table init_table[] __initdata = {
c9e2d69a
PDS		 1289 {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0},
1290 {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0},
1291 {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0},
1292 {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0},
1293 {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1},
1294 {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1},
1295 {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1},
1296 {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1},
1297 {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1},
1298 {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1299 {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1300 {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1301 {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1302 {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
897e1dde 1303 {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
c9e2d69a
PDS		 1304 {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
1305 {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
77f71730
MP		 1306 {TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0},
1307 {TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
f67a8d21
TR		 1308 {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1309 {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
39409aa4
TR		 1310 {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
1311 {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
4a7f10d6
AB		 1312 {TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0},
1313 {TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0},
1314 {TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0},
1315 {TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0},
1316 {TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0},
1317 {TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0},
c9e2d69a
PDS		 1318 /* This MUST be the last entry. */
1319 {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
2cb5efef
PDS		 1320};
1321
1322static void __init tegra114_clock_apply_init_table(void)
1323{
c9e2d69a 1324 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
2cb5efef
PDS		 1325}
1326
25c9ded6
PW		 1327/**
1328 * tegra114_car_barrier - wait for pending writes to the CAR to complete
1329 *
1330 * Wait for any outstanding writes to the CAR MMIO space from this CPU
1331 * to complete before continuing execution. No return value.
1332 */
1333static void tegra114_car_barrier(void)
1334{
1335 wmb(); /* probably unnecessary */
1336 readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
1337}
1338
1339/**
1340 * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
1341 *
1342 * When the CPU rail voltage is in the high-voltage range, use the
1343 * built-in hardwired clock propagation delays in the CPU clock
1344 * shaper. No return value.
1345 */
1346void tegra114_clock_tune_cpu_trimmers_high(void)
1347{
1348 u32 select = 0;
1349
1350 /* Use hardwired rise->rise & fall->fall clock propagation delays */
1351 select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1352 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1353 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1354 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1355
1356 tegra114_car_barrier();
1357}
1358EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
1359
1360/**
1361 * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
1362 *
1363 * When the CPU rail voltage is in the low-voltage range, use the
1364 * extended clock propagation delays set by
1365 * tegra114_clock_tune_cpu_trimmers_init(). The intention is to
1366 * maintain the input clock duty cycle that the FCPU subsystem
1367 * expects. No return value.
1368 */
1369void tegra114_clock_tune_cpu_trimmers_low(void)
1370{
1371 u32 select = 0;
1372
1373 /*
1374 * Use software-specified rise->rise & fall->fall clock
1375 * propagation delays (from
1376 * tegra114_clock_tune_cpu_trimmers_init()
1377 */
1378 select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1379 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1380 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1381 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1382
1383 tegra114_car_barrier();
1384}
1385EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
1386
1387/**
1388 * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
1389 *
1390 * Program extended clock propagation delays into the FCPU clock
1391 * shaper and enable them. XXX Define the purpose - peak current
1392 * reduction? No return value.
1393 */
1394/* XXX Initial voltage rail state assumption issues? */
1395void tegra114_clock_tune_cpu_trimmers_init(void)
1396{
1397 u32 dr = 0, r = 0;
1398
1399 /* Increment the rise->rise clock delay by four steps */
1400 r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
1401 CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
1402 CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
1403 writel_relaxed(r, clk_base + CPU_FINETRIM_R);
1404
1405 /*
1406 * Use the rise->rise clock propagation delay specified in the
1407 * r field
1408 */
1409 dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1410 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1411 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1412 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
1413
1414 tegra114_clock_tune_cpu_trimmers_low();
1415}
1416EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
1417
1c472d8e
PW		 1418/**
1419 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1420 *
1421 * Assert the reset line of the DFLL's DVCO. No return value.
1422 */
1423void tegra114_clock_assert_dfll_dvco_reset(void)
1424{
1425 u32 v;
1426
1427 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1428 v |= (1 << DVFS_DFLL_RESET_SHIFT);
1429 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1430 tegra114_car_barrier();
1431}
1432EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
1433
1434/**
1435 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1436 *
1437 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1438 * operate. No return value.
1439 */
1440void tegra114_clock_deassert_dfll_dvco_reset(void)
1441{
1442 u32 v;
1443
1444 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1445 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1446 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1447 tegra114_car_barrier();
1448}
1449EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
1450
061cec92 1451static void __init tegra114_clock_init(struct device_node *np)
2cb5efef
PDS		 1452{
1453 struct device_node *node;
2cb5efef
PDS		 1454
1455 clk_base = of_iomap(np, 0);
1456 if (!clk_base) {
1457 pr_err("ioremap tegra114 CAR failed\n");
1458 return;
1459 }
1460
1461 node = of_find_matching_node(NULL, pmc_match);
1462 if (!node) {
1463 pr_err("Failed to find pmc node\n");
1464 WARN_ON(1);
1465 return;
1466 }
1467
1468 pmc_base = of_iomap(node, 0);
1469 if (!pmc_base) {
1470 pr_err("Can't map pmc registers\n");
1471 WARN_ON(1);
1472 return;
1473 }
1474
6d5b988e
SW		 1475 clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
1476 TEGRA114_CLK_PERIPH_BANKS);
343a607c 1477 if (!clks)
2cb5efef
PDS		 1478 return;
1479
a84724a1
TR		 1480 if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
1481 ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,
1482 &pll_ref_freq) < 0)
d5ff89a8
PDS		 1483 return;
1484
2cb5efef
PDS		 1485 tegra114_fixed_clk_init(clk_base);
1486 tegra114_pll_init(clk_base, pmc_base);
76ebc134 1487 tegra114_periph_clk_init(clk_base, pmc_base);
88d909be
RK		 1488 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
1489 tegra114_audio_plls,
1490 ARRAY_SIZE(tegra114_audio_plls));
de4f30fd 1491 tegra_pmc_clk_init(pmc_base, tegra114_clks);
a7c8485a
PDS		 1492 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1493 &pll_x_params);
2cb5efef 1494
343a607c 1495 tegra_add_of_provider(np);
73d37e4c 1496 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
2cb5efef
PDS		 1497
1498 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
1499
1500 tegra_cpu_car_ops = &tegra114_cpu_car_ops;
1501}
061cec92 1502CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
Linux kernel - Deliverables
This page took 0.225607 seconds and 5 git commands to generate.