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c1d1939c | 1 | /* |
8f8f484b PG |
2 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #ifndef __TEGRA_CLK_H | |
18 | #define __TEGRA_CLK_H | |
19 | ||
20 | #include <linux/clk-provider.h> | |
21 | #include <linux/clkdev.h> | |
22 | ||
23 | /** | |
24 | * struct tegra_clk_sync_source - external clock source from codec | |
25 | * | |
26 | * @hw: handle between common and hardware-specific interfaces | |
27 | * @rate: input frequency from source | |
28 | * @max_rate: max rate allowed | |
29 | */ | |
30 | struct tegra_clk_sync_source { | |
31 | struct clk_hw hw; | |
32 | unsigned long rate; | |
33 | unsigned long max_rate; | |
34 | }; | |
35 | ||
36 | #define to_clk_sync_source(_hw) \ | |
37 | container_of(_hw, struct tegra_clk_sync_source, hw) | |
38 | ||
39 | extern const struct clk_ops tegra_clk_sync_source_ops; | |
343a607c PDS |
40 | extern int *periph_clk_enb_refcnt; |
41 | ||
8f8f484b PG |
42 | struct clk *tegra_clk_register_sync_source(const char *name, |
43 | unsigned long fixed_rate, unsigned long max_rate); | |
44 | ||
45 | /** | |
46 | * struct tegra_clk_frac_div - fractional divider clock | |
47 | * | |
48 | * @hw: handle between common and hardware-specific interfaces | |
49 | * @reg: register containing divider | |
50 | * @flags: hardware-specific flags | |
51 | * @shift: shift to the divider bit field | |
52 | * @width: width of the divider bit field | |
53 | * @frac_width: width of the fractional bit field | |
54 | * @lock: register lock | |
55 | * | |
56 | * Flags: | |
57 | * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. | |
58 | * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this | |
59 | * flag indicates that this divider is for fixed rate PLL. | |
60 | * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when | |
61 | * fraction bit is set. This flags indicates to calculate divider for which | |
62 | * fracton bit will be zero. | |
63 | * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is | |
64 | * set when divider value is not 0. This flags indicates that the divider | |
65 | * is for UART module. | |
66 | */ | |
67 | struct tegra_clk_frac_div { | |
68 | struct clk_hw hw; | |
69 | void __iomem *reg; | |
70 | u8 flags; | |
71 | u8 shift; | |
72 | u8 width; | |
73 | u8 frac_width; | |
74 | spinlock_t *lock; | |
75 | }; | |
76 | ||
77 | #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) | |
78 | ||
79 | #define TEGRA_DIVIDER_ROUND_UP BIT(0) | |
80 | #define TEGRA_DIVIDER_FIXED BIT(1) | |
81 | #define TEGRA_DIVIDER_INT BIT(2) | |
82 | #define TEGRA_DIVIDER_UART BIT(3) | |
83 | ||
84 | extern const struct clk_ops tegra_clk_frac_div_ops; | |
85 | struct clk *tegra_clk_register_divider(const char *name, | |
86 | const char *parent_name, void __iomem *reg, | |
87 | unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, | |
88 | u8 frac_width, spinlock_t *lock); | |
4f4f85fa TR |
89 | struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, |
90 | void __iomem *reg, spinlock_t *lock); | |
8f8f484b PG |
91 | |
92 | /* | |
93 | * Tegra PLL: | |
94 | * | |
95 | * In general, there are 3 requirements for each PLL | |
96 | * that SW needs to be comply with. | |
97 | * (1) Input frequency range (REF). | |
98 | * (2) Comparison frequency range (CF). CF = REF/DIVM. | |
99 | * (3) VCO frequency range (VCO). VCO = CF * DIVN. | |
100 | * | |
101 | * The final PLL output frequency (FO) = VCO >> DIVP. | |
102 | */ | |
103 | ||
104 | /** | |
105 | * struct tegra_clk_pll_freq_table - PLL frequecy table | |
106 | * | |
107 | * @input_rate: input rate from source | |
108 | * @output_rate: output rate from PLL for the input rate | |
109 | * @n: feedback divider | |
110 | * @m: input divider | |
111 | * @p: post divider | |
112 | * @cpcon: charge pump current | |
d907f4b4 | 113 | * @sdm_data: fraction divider setting (0 = disabled) |
8f8f484b PG |
114 | */ |
115 | struct tegra_clk_pll_freq_table { | |
116 | unsigned long input_rate; | |
117 | unsigned long output_rate; | |
d907f4b4 | 118 | u32 n; |
8f8f484b PG |
119 | u16 m; |
120 | u8 p; | |
121 | u8 cpcon; | |
d907f4b4 | 122 | u16 sdm_data; |
8f8f484b PG |
123 | }; |
124 | ||
0b6525ac PDS |
125 | /** |
126 | * struct pdiv_map - map post divider to hw value | |
127 | * | |
128 | * @pdiv: post divider | |
129 | * @hw_val: value to be written to the PLL hw | |
130 | */ | |
131 | struct pdiv_map { | |
132 | u8 pdiv; | |
133 | u8 hw_val; | |
134 | }; | |
135 | ||
aa6fefde PDS |
136 | /** |
137 | * struct div_nmp - offset and width of m,n and p fields | |
138 | * | |
139 | * @divn_shift: shift to the feedback divider bit field | |
140 | * @divn_width: width of the feedback divider bit field | |
141 | * @divm_shift: shift to the input divider bit field | |
142 | * @divm_width: width of the input divider bit field | |
143 | * @divp_shift: shift to the post divider bit field | |
144 | * @divp_width: width of the post divider bit field | |
7b781c72 PDS |
145 | * @override_divn_shift: shift to the feedback divider bitfield in override reg |
146 | * @override_divm_shift: shift to the input divider bitfield in override reg | |
147 | * @override_divp_shift: shift to the post divider bitfield in override reg | |
aa6fefde PDS |
148 | */ |
149 | struct div_nmp { | |
150 | u8 divn_shift; | |
151 | u8 divn_width; | |
152 | u8 divm_shift; | |
153 | u8 divm_width; | |
154 | u8 divp_shift; | |
155 | u8 divp_width; | |
7b781c72 PDS |
156 | u8 override_divn_shift; |
157 | u8 override_divm_shift; | |
158 | u8 override_divp_shift; | |
aa6fefde PDS |
159 | }; |
160 | ||
56fd27b3 BH |
161 | #define MAX_PLL_MISC_REG_COUNT 6 |
162 | ||
b985114e BH |
163 | struct tegra_clk_pll; |
164 | ||
8f8f484b | 165 | /** |
db592c4e | 166 | * struct tegra_clk_pll_params - PLL parameters |
8f8f484b PG |
167 | * |
168 | * @input_min: Minimum input frequency | |
169 | * @input_max: Maximum input frequency | |
170 | * @cf_min: Minimum comparison frequency | |
171 | * @cf_max: Maximum comparison frequency | |
172 | * @vco_min: Minimum VCO frequency | |
173 | * @vco_max: Maximum VCO frequency | |
174 | * @base_reg: PLL base reg offset | |
175 | * @misc_reg: PLL misc reg offset | |
176 | * @lock_reg: PLL lock reg offset | |
db592c4e | 177 | * @lock_mask: Bitmask for PLL lock status |
8f8f484b | 178 | * @lock_enable_bit_idx: Bit index to enable PLL lock |
db592c4e TR |
179 | * @iddq_reg: PLL IDDQ register offset |
180 | * @iddq_bit_idx: Bit index to enable PLL IDDQ | |
fde207eb BH |
181 | * @reset_reg: Register offset of where RESET bit is |
182 | * @reset_bit_idx: Shift of reset bit in reset_reg | |
d907f4b4 RK |
183 | * @sdm_din_reg: Register offset where SDM settings are |
184 | * @sdm_din_mask: Mask of SDM divider bits | |
185 | * @sdm_ctrl_reg: Register offset where SDM enable is | |
186 | * @sdm_ctrl_en_mask: Mask of SDM enable bit | |
0ef9db6c BH |
187 | * @ssc_ctrl_reg: Register offset where SSC settings are |
188 | * @ssc_ctrl_en_mask: Mask of SSC enable bit | |
db592c4e TR |
189 | * @aux_reg: AUX register offset |
190 | * @dyn_ramp_reg: Dynamic ramp control register offset | |
191 | * @ext_misc_reg: Miscellaneous control register offsets | |
192 | * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) | |
193 | * @pmc_divp_reg: p divider PMC override register offset (PLLM) | |
194 | * @flags: PLL flags | |
195 | * @stepa_shift: Dynamic ramp step A field shift | |
196 | * @stepb_shift: Dynamic ramp step B field shift | |
8f8f484b | 197 | * @lock_delay: Delay in us if PLL lock is not used |
db592c4e | 198 | * @max_p: maximum value for the p divider |
b985114e | 199 | * @defaults_set: Boolean signaling all reg defaults for PLL set. |
db592c4e TR |
200 | * @pdiv_tohw: mapping of p divider to register values |
201 | * @div_nmp: offsets and widths on n, m and p fields | |
fdc1fead RK |
202 | * @freq_table: array of frequencies supported by PLL |
203 | * @fixed_rate: PLL rate if it is fixed | |
407254da RK |
204 | * @mdiv_default: Default value for fixed mdiv for this PLL |
205 | * @round_p_to_pdiv: Callback used to round p to the closed pdiv | |
d907f4b4 RK |
206 | * @set_gain: Callback to adjust N div for SDM enabled |
207 | * PLL's based on fractional divider value. | |
407254da RK |
208 | * @calc_rate: Callback used to change how out of table |
209 | * rates (dividers and multipler) are calculated. | |
b5512b45 BH |
210 | * @adjust_vco: Callback to adjust the programming range of the |
211 | * divider range (if SDM is present) | |
b985114e BH |
212 | * @set_defaults: Callback which will try to initialize PLL |
213 | * registers to sane default values. This is first | |
214 | * tried during PLL registration, but if the PLL | |
215 | * is already enabled, it will be done the first | |
216 | * time the rate is changed while the PLL is | |
217 | * disabled. | |
17e9273a RK |
218 | * @dyn_ramp: Callback which can be used to define a custom |
219 | * dynamic ramp function for a given PLL. | |
fdc1fead RK |
220 | * |
221 | * Flags: | |
222 | * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for | |
223 | * PLL locking. If not set it will use lock_delay value to wait. | |
224 | * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs | |
225 | * to be programmed to change output frequency of the PLL. | |
226 | * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs | |
227 | * to be programmed to change output frequency of the PLL. | |
228 | * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs | |
229 | * to be programmed to change output frequency of the PLL. | |
230 | * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated | |
231 | * that it is PLLU and invert post divider value. | |
232 | * TEGRA_PLLM - PLLM has additional override settings in PMC. This | |
233 | * flag indicates that it is PLLM and use override settings. | |
234 | * TEGRA_PLL_FIXED - We are not supposed to change output frequency | |
235 | * of some plls. | |
236 | * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. | |
237 | * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the | |
238 | * base register. | |
239 | * TEGRA_PLL_BYPASS - PLL has bypass bit | |
240 | * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring | |
407254da RK |
241 | * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv |
242 | * it may be more accurate (especially if SDM present) | |
6929715c RK |
243 | * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This |
244 | * flag indicated that it is PLLMB. | |
6b301a05 | 245 | * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output |
8f8f484b PG |
246 | */ |
247 | struct tegra_clk_pll_params { | |
248 | unsigned long input_min; | |
249 | unsigned long input_max; | |
250 | unsigned long cf_min; | |
251 | unsigned long cf_max; | |
252 | unsigned long vco_min; | |
253 | unsigned long vco_max; | |
254 | ||
255 | u32 base_reg; | |
256 | u32 misc_reg; | |
257 | u32 lock_reg; | |
3e72771e | 258 | u32 lock_mask; |
8f8f484b | 259 | u32 lock_enable_bit_idx; |
c1d1939c PDS |
260 | u32 iddq_reg; |
261 | u32 iddq_bit_idx; | |
fde207eb BH |
262 | u32 reset_reg; |
263 | u32 reset_bit_idx; | |
d907f4b4 RK |
264 | u32 sdm_din_reg; |
265 | u32 sdm_din_mask; | |
266 | u32 sdm_ctrl_reg; | |
267 | u32 sdm_ctrl_en_mask; | |
0ef9db6c BH |
268 | u32 ssc_ctrl_reg; |
269 | u32 ssc_ctrl_en_mask; | |
c1d1939c PDS |
270 | u32 aux_reg; |
271 | u32 dyn_ramp_reg; | |
56fd27b3 | 272 | u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT]; |
7b781c72 PDS |
273 | u32 pmc_divnm_reg; |
274 | u32 pmc_divp_reg; | |
ebe142b2 | 275 | u32 flags; |
c1d1939c PDS |
276 | int stepa_shift; |
277 | int stepb_shift; | |
8f8f484b | 278 | int lock_delay; |
0b6525ac | 279 | int max_p; |
b985114e | 280 | bool defaults_set; |
385f9adf | 281 | const struct pdiv_map *pdiv_tohw; |
aa6fefde | 282 | struct div_nmp *div_nmp; |
ebe142b2 PDS |
283 | struct tegra_clk_pll_freq_table *freq_table; |
284 | unsigned long fixed_rate; | |
407254da RK |
285 | u16 mdiv_default; |
286 | u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv); | |
d907f4b4 | 287 | void (*set_gain)(struct tegra_clk_pll_freq_table *cfg); |
407254da RK |
288 | int (*calc_rate)(struct clk_hw *hw, |
289 | struct tegra_clk_pll_freq_table *cfg, | |
290 | unsigned long rate, unsigned long parent_rate); | |
b5512b45 BH |
291 | unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params, |
292 | unsigned long parent_rate); | |
b985114e | 293 | void (*set_defaults)(struct tegra_clk_pll *pll); |
17e9273a RK |
294 | int (*dyn_ramp)(struct tegra_clk_pll *pll, |
295 | struct tegra_clk_pll_freq_table *cfg); | |
8f8f484b PG |
296 | }; |
297 | ||
fdc1fead RK |
298 | #define TEGRA_PLL_USE_LOCK BIT(0) |
299 | #define TEGRA_PLL_HAS_CPCON BIT(1) | |
300 | #define TEGRA_PLL_SET_LFCON BIT(2) | |
301 | #define TEGRA_PLL_SET_DCCON BIT(3) | |
302 | #define TEGRA_PLLU BIT(4) | |
303 | #define TEGRA_PLLM BIT(5) | |
304 | #define TEGRA_PLL_FIXED BIT(6) | |
305 | #define TEGRA_PLLE_CONFIGURE BIT(7) | |
306 | #define TEGRA_PLL_LOCK_MISC BIT(8) | |
307 | #define TEGRA_PLL_BYPASS BIT(9) | |
308 | #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) | |
407254da | 309 | #define TEGRA_MDIV_NEW BIT(11) |
6929715c | 310 | #define TEGRA_PLLMB BIT(12) |
6b301a05 | 311 | #define TEGRA_PLL_VCO_OUT BIT(13) |
fdc1fead | 312 | |
8f8f484b PG |
313 | /** |
314 | * struct tegra_clk_pll - Tegra PLL clock | |
315 | * | |
316 | * @hw: handle between common and hardware-specifix interfaces | |
317 | * @clk_base: address of CAR controller | |
318 | * @pmc: address of PMC, required to read override bits | |
8f8f484b | 319 | * @lock: register lock |
fdc1fead | 320 | * @params: PLL parameters |
8f8f484b PG |
321 | */ |
322 | struct tegra_clk_pll { | |
323 | struct clk_hw hw; | |
324 | void __iomem *clk_base; | |
325 | void __iomem *pmc; | |
8f8f484b | 326 | spinlock_t *lock; |
8f8f484b PG |
327 | struct tegra_clk_pll_params *params; |
328 | }; | |
329 | ||
330 | #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) | |
331 | ||
88d909be RK |
332 | /** |
333 | * struct tegra_audio_clk_info - Tegra Audio Clk Information | |
334 | * | |
335 | * @name: name for the audio pll | |
336 | * @pll_params: pll_params for audio pll | |
337 | * @clk_id: clk_ids for the audio pll | |
338 | * @parent: name of the parent of the audio pll | |
339 | */ | |
340 | struct tegra_audio_clk_info { | |
341 | char *name; | |
342 | struct tegra_clk_pll_params *pll_params; | |
343 | int clk_id; | |
344 | char *parent; | |
345 | }; | |
346 | ||
8f8f484b PG |
347 | extern const struct clk_ops tegra_clk_pll_ops; |
348 | extern const struct clk_ops tegra_clk_plle_ops; | |
349 | struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, | |
350 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 PDS |
351 | unsigned long flags, struct tegra_clk_pll_params *pll_params, |
352 | spinlock_t *lock); | |
c1d1939c | 353 | |
8f8f484b PG |
354 | struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, |
355 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 PDS |
356 | unsigned long flags, struct tegra_clk_pll_params *pll_params, |
357 | spinlock_t *lock); | |
8f8f484b | 358 | |
c1d1939c PDS |
359 | struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, |
360 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 | 361 | unsigned long flags, |
c1d1939c | 362 | struct tegra_clk_pll_params *pll_params, |
c1d1939c PDS |
363 | spinlock_t *lock); |
364 | ||
dd322f04 RK |
365 | struct clk *tegra_clk_register_pllxc_tegra210(const char *name, |
366 | const char *parent_name, void __iomem *clk_base, | |
367 | void __iomem *pmc, unsigned long flags, | |
368 | struct tegra_clk_pll_params *pll_params, | |
369 | spinlock_t *lock); | |
370 | ||
c1d1939c PDS |
371 | struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, |
372 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 | 373 | unsigned long flags, |
c1d1939c | 374 | struct tegra_clk_pll_params *pll_params, |
c1d1939c PDS |
375 | spinlock_t *lock); |
376 | ||
377 | struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, | |
378 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 | 379 | unsigned long flags, |
c1d1939c | 380 | struct tegra_clk_pll_params *pll_params, |
c1d1939c PDS |
381 | spinlock_t *lock); |
382 | ||
383 | struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, | |
384 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 | 385 | unsigned long flags, |
c1d1939c | 386 | struct tegra_clk_pll_params *pll_params, |
c1d1939c PDS |
387 | spinlock_t *lock, unsigned long parent_rate); |
388 | ||
389 | struct clk *tegra_clk_register_plle_tegra114(const char *name, | |
390 | const char *parent_name, | |
391 | void __iomem *clk_base, unsigned long flags, | |
c1d1939c | 392 | struct tegra_clk_pll_params *pll_params, |
c1d1939c PDS |
393 | spinlock_t *lock); |
394 | ||
dd322f04 RK |
395 | struct clk *tegra_clk_register_plle_tegra210(const char *name, |
396 | const char *parent_name, | |
397 | void __iomem *clk_base, unsigned long flags, | |
398 | struct tegra_clk_pll_params *pll_params, | |
399 | spinlock_t *lock); | |
400 | ||
401 | struct clk *tegra_clk_register_pllc_tegra210(const char *name, | |
402 | const char *parent_name, void __iomem *clk_base, | |
403 | void __iomem *pmc, unsigned long flags, | |
404 | struct tegra_clk_pll_params *pll_params, | |
405 | spinlock_t *lock); | |
406 | ||
407 | struct clk *tegra_clk_register_pllss_tegra210(const char *name, | |
408 | const char *parent_name, void __iomem *clk_base, | |
409 | unsigned long flags, | |
410 | struct tegra_clk_pll_params *pll_params, | |
411 | spinlock_t *lock); | |
412 | ||
798e910b PDS |
413 | struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, |
414 | void __iomem *clk_base, unsigned long flags, | |
415 | struct tegra_clk_pll_params *pll_params, | |
416 | spinlock_t *lock); | |
417 | ||
6929715c RK |
418 | struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, |
419 | void __iomem *clk_base, void __iomem *pmc, | |
420 | unsigned long flags, | |
421 | struct tegra_clk_pll_params *pll_params, | |
422 | spinlock_t *lock); | |
423 | ||
8f8f484b PG |
424 | /** |
425 | * struct tegra_clk_pll_out - PLL divider down clock | |
426 | * | |
427 | * @hw: handle between common and hardware-specific interfaces | |
428 | * @reg: register containing the PLL divider | |
429 | * @enb_bit_idx: bit to enable/disable PLL divider | |
430 | * @rst_bit_idx: bit to reset PLL divider | |
431 | * @lock: register lock | |
432 | * @flags: hardware-specific flags | |
433 | */ | |
434 | struct tegra_clk_pll_out { | |
435 | struct clk_hw hw; | |
436 | void __iomem *reg; | |
437 | u8 enb_bit_idx; | |
438 | u8 rst_bit_idx; | |
439 | spinlock_t *lock; | |
440 | u8 flags; | |
441 | }; | |
442 | ||
443 | #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) | |
444 | ||
445 | extern const struct clk_ops tegra_clk_pll_out_ops; | |
446 | struct clk *tegra_clk_register_pll_out(const char *name, | |
447 | const char *parent_name, void __iomem *reg, u8 enb_bit_idx, | |
448 | u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, | |
449 | spinlock_t *lock); | |
450 | ||
451 | /** | |
452 | * struct tegra_clk_periph_regs - Registers controlling peripheral clock | |
453 | * | |
454 | * @enb_reg: read the enable status | |
455 | * @enb_set_reg: write 1 to enable clock | |
456 | * @enb_clr_reg: write 1 to disable clock | |
457 | * @rst_reg: read the reset status | |
458 | * @rst_set_reg: write 1 to assert the reset of peripheral | |
459 | * @rst_clr_reg: write 1 to deassert the reset of peripheral | |
460 | */ | |
461 | struct tegra_clk_periph_regs { | |
462 | u32 enb_reg; | |
463 | u32 enb_set_reg; | |
464 | u32 enb_clr_reg; | |
465 | u32 rst_reg; | |
466 | u32 rst_set_reg; | |
467 | u32 rst_clr_reg; | |
468 | }; | |
469 | ||
470 | /** | |
471 | * struct tegra_clk_periph_gate - peripheral gate clock | |
472 | * | |
473 | * @magic: magic number to validate type | |
474 | * @hw: handle between common and hardware-specific interfaces | |
475 | * @clk_base: address of CAR controller | |
476 | * @regs: Registers to control the peripheral | |
477 | * @flags: hardware-specific flags | |
478 | * @clk_num: Clock number | |
479 | * @enable_refcnt: array to maintain reference count of the clock | |
480 | * | |
481 | * Flags: | |
482 | * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed | |
483 | * for this module. | |
484 | * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module | |
485 | * after clock enable and driver for the module is responsible for | |
486 | * doing reset. | |
487 | * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the | |
488 | * bus to flush the write operation in apb bus. This flag indicates | |
489 | * that this peripheral is in apb bus. | |
fdcccbd8 | 490 | * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug |
8f8f484b PG |
491 | */ |
492 | struct tegra_clk_periph_gate { | |
493 | u32 magic; | |
494 | struct clk_hw hw; | |
495 | void __iomem *clk_base; | |
496 | u8 flags; | |
497 | int clk_num; | |
498 | int *enable_refcnt; | |
499 | struct tegra_clk_periph_regs *regs; | |
500 | }; | |
501 | ||
502 | #define to_clk_periph_gate(_hw) \ | |
503 | container_of(_hw, struct tegra_clk_periph_gate, hw) | |
504 | ||
505 | #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 | |
506 | ||
507 | #define TEGRA_PERIPH_NO_RESET BIT(0) | |
508 | #define TEGRA_PERIPH_MANUAL_RESET BIT(1) | |
509 | #define TEGRA_PERIPH_ON_APB BIT(2) | |
fdcccbd8 | 510 | #define TEGRA_PERIPH_WAR_1005168 BIT(3) |
5bb9d267 | 511 | #define TEGRA_PERIPH_NO_DIV BIT(4) |
b29f9e92 | 512 | #define TEGRA_PERIPH_NO_GATE BIT(5) |
8f8f484b | 513 | |
8f8f484b PG |
514 | extern const struct clk_ops tegra_clk_periph_gate_ops; |
515 | struct clk *tegra_clk_register_periph_gate(const char *name, | |
516 | const char *parent_name, u8 gate_flags, void __iomem *clk_base, | |
d5ff89a8 | 517 | unsigned long flags, int clk_num, int *enable_refcnt); |
8f8f484b PG |
518 | |
519 | /** | |
520 | * struct clk-periph - peripheral clock | |
521 | * | |
522 | * @magic: magic number to validate type | |
523 | * @hw: handle between common and hardware-specific interfaces | |
524 | * @mux: mux clock | |
525 | * @divider: divider clock | |
526 | * @gate: gate clock | |
527 | * @mux_ops: mux clock ops | |
528 | * @div_ops: divider clock ops | |
529 | * @gate_ops: gate clock ops | |
530 | */ | |
531 | struct tegra_clk_periph { | |
532 | u32 magic; | |
533 | struct clk_hw hw; | |
534 | struct clk_mux mux; | |
535 | struct tegra_clk_frac_div divider; | |
536 | struct tegra_clk_periph_gate gate; | |
537 | ||
538 | const struct clk_ops *mux_ops; | |
539 | const struct clk_ops *div_ops; | |
540 | const struct clk_ops *gate_ops; | |
541 | }; | |
542 | ||
543 | #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) | |
544 | ||
545 | #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 | |
546 | ||
547 | extern const struct clk_ops tegra_clk_periph_ops; | |
548 | struct clk *tegra_clk_register_periph(const char *name, | |
549 | const char **parent_names, int num_parents, | |
550 | struct tegra_clk_periph *periph, void __iomem *clk_base, | |
a26a0298 | 551 | u32 offset, unsigned long flags); |
8f8f484b PG |
552 | struct clk *tegra_clk_register_periph_nodiv(const char *name, |
553 | const char **parent_names, int num_parents, | |
554 | struct tegra_clk_periph *periph, void __iomem *clk_base, | |
555 | u32 offset); | |
556 | ||
ce4f3313 | 557 | #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ |
8f8f484b | 558 | _div_shift, _div_width, _div_frac_width, \ |
343a607c | 559 | _div_flags, _clk_num,\ |
bc44275b | 560 | _gate_flags, _table, _lock) \ |
8f8f484b PG |
561 | { \ |
562 | .mux = { \ | |
563 | .flags = _mux_flags, \ | |
564 | .shift = _mux_shift, \ | |
ce4f3313 PDS |
565 | .mask = _mux_mask, \ |
566 | .table = _table, \ | |
bc44275b | 567 | .lock = _lock, \ |
8f8f484b PG |
568 | }, \ |
569 | .divider = { \ | |
570 | .flags = _div_flags, \ | |
571 | .shift = _div_shift, \ | |
572 | .width = _div_width, \ | |
573 | .frac_width = _div_frac_width, \ | |
bc44275b | 574 | .lock = _lock, \ |
8f8f484b PG |
575 | }, \ |
576 | .gate = { \ | |
577 | .flags = _gate_flags, \ | |
578 | .clk_num = _clk_num, \ | |
8f8f484b PG |
579 | }, \ |
580 | .mux_ops = &clk_mux_ops, \ | |
581 | .div_ops = &tegra_clk_frac_div_ops, \ | |
582 | .gate_ops = &tegra_clk_periph_gate_ops, \ | |
583 | } | |
584 | ||
585 | struct tegra_periph_init_data { | |
586 | const char *name; | |
587 | int clk_id; | |
76ebc134 PDS |
588 | union { |
589 | const char **parent_names; | |
590 | const char *parent_name; | |
591 | } p; | |
8f8f484b PG |
592 | int num_parents; |
593 | struct tegra_clk_periph periph; | |
594 | u32 offset; | |
595 | const char *con_id; | |
596 | const char *dev_id; | |
a26a0298 | 597 | unsigned long flags; |
8f8f484b PG |
598 | }; |
599 | ||
ce4f3313 PDS |
600 | #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ |
601 | _mux_shift, _mux_mask, _mux_flags, _div_shift, \ | |
d5ff89a8 | 602 | _div_width, _div_frac_width, _div_flags, \ |
343a607c | 603 | _clk_num, _gate_flags, _clk_id, _table, \ |
bc44275b | 604 | _flags, _lock) \ |
8f8f484b PG |
605 | { \ |
606 | .name = _name, \ | |
607 | .clk_id = _clk_id, \ | |
76ebc134 | 608 | .p.parent_names = _parent_names, \ |
8f8f484b | 609 | .num_parents = ARRAY_SIZE(_parent_names), \ |
ce4f3313 | 610 | .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ |
8f8f484b PG |
611 | _mux_flags, _div_shift, \ |
612 | _div_width, _div_frac_width, \ | |
613 | _div_flags, _clk_num, \ | |
bc44275b | 614 | _gate_flags, _table, _lock), \ |
8f8f484b PG |
615 | .offset = _offset, \ |
616 | .con_id = _con_id, \ | |
617 | .dev_id = _dev_id, \ | |
a26a0298 | 618 | .flags = _flags \ |
8f8f484b PG |
619 | } |
620 | ||
ce4f3313 PDS |
621 | #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ |
622 | _mux_shift, _mux_width, _mux_flags, _div_shift, \ | |
d5ff89a8 | 623 | _div_width, _div_frac_width, _div_flags, \ |
343a607c | 624 | _clk_num, _gate_flags, _clk_id) \ |
ce4f3313 PDS |
625 | TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ |
626 | _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ | |
627 | _div_shift, _div_width, _div_frac_width, _div_flags, \ | |
343a607c | 628 | _clk_num, _gate_flags, _clk_id,\ |
bc44275b | 629 | NULL, 0, NULL) |
ce4f3313 | 630 | |
8f8f484b PG |
631 | /** |
632 | * struct clk_super_mux - super clock | |
633 | * | |
634 | * @hw: handle between common and hardware-specific interfaces | |
635 | * @reg: register controlling multiplexer | |
636 | * @width: width of the multiplexer bit field | |
637 | * @flags: hardware-specific flags | |
638 | * @div2_index: bit controlling divide-by-2 | |
639 | * @pllx_index: PLLX index in the parent list | |
640 | * @lock: register lock | |
641 | * | |
642 | * Flags: | |
643 | * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates | |
644 | * that this is LP cluster clock. | |
645 | */ | |
646 | struct tegra_clk_super_mux { | |
647 | struct clk_hw hw; | |
648 | void __iomem *reg; | |
649 | u8 width; | |
650 | u8 flags; | |
651 | u8 div2_index; | |
652 | u8 pllx_index; | |
653 | spinlock_t *lock; | |
654 | }; | |
655 | ||
656 | #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) | |
657 | ||
658 | #define TEGRA_DIVIDER_2 BIT(0) | |
659 | ||
660 | extern const struct clk_ops tegra_clk_super_ops; | |
661 | struct clk *tegra_clk_register_super_mux(const char *name, | |
662 | const char **parent_names, u8 num_parents, | |
663 | unsigned long flags, void __iomem *reg, u8 clk_super_flags, | |
664 | u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); | |
665 | ||
666 | /** | |
8106462f | 667 | * struct clk_init_table - clock initialization table |
8f8f484b PG |
668 | * @clk_id: clock id as mentioned in device tree bindings |
669 | * @parent_id: parent clock id as mentioned in device tree bindings | |
670 | * @rate: rate to set | |
671 | * @state: enable/disable | |
672 | */ | |
673 | struct tegra_clk_init_table { | |
674 | unsigned int clk_id; | |
675 | unsigned int parent_id; | |
676 | unsigned long rate; | |
677 | int state; | |
678 | }; | |
679 | ||
680 | /** | |
681 | * struct clk_duplicate - duplicate clocks | |
682 | * @clk_id: clock id as mentioned in device tree bindings | |
683 | * @lookup: duplicate lookup entry for the clock | |
684 | */ | |
685 | struct tegra_clk_duplicate { | |
686 | int clk_id; | |
687 | struct clk_lookup lookup; | |
688 | }; | |
689 | ||
690 | #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ | |
691 | { \ | |
692 | .clk_id = _clk_id, \ | |
693 | .lookup = { \ | |
694 | .dev_id = _dev, \ | |
695 | .con_id = _con, \ | |
696 | }, \ | |
697 | } | |
698 | ||
b8700d50 PDS |
699 | struct tegra_clk { |
700 | int dt_id; | |
701 | bool present; | |
702 | }; | |
703 | ||
73d37e4c PDS |
704 | struct tegra_devclk { |
705 | int dt_id; | |
706 | char *dev_id; | |
707 | char *con_id; | |
708 | }; | |
66b6f3d0 MP |
709 | |
710 | void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long), | |
711 | int (*deassert)(unsigned long)); | |
73d37e4c | 712 | |
8f8f484b PG |
713 | void tegra_init_from_table(struct tegra_clk_init_table *tbl, |
714 | struct clk *clks[], int clk_max); | |
715 | ||
716 | void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, | |
717 | struct clk *clks[], int clk_max); | |
718 | ||
d5ff89a8 | 719 | struct tegra_clk_periph_regs *get_reg_bank(int clkid); |
6d5b988e | 720 | struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); |
343a607c | 721 | |
b8700d50 PDS |
722 | struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); |
723 | ||
343a607c | 724 | void tegra_add_of_provider(struct device_node *np); |
73d37e4c | 725 | void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); |
d5ff89a8 | 726 | |
6609dbe4 PDS |
727 | void tegra_audio_clk_init(void __iomem *clk_base, |
728 | void __iomem *pmc_base, struct tegra_clk *tegra_clks, | |
88d909be RK |
729 | struct tegra_audio_clk_info *audio_info, |
730 | unsigned int num_plls); | |
6609dbe4 | 731 | |
76ebc134 PDS |
732 | void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, |
733 | struct tegra_clk *tegra_clks, | |
734 | struct tegra_clk_pll_params *pll_params); | |
735 | ||
de4f30fd PDS |
736 | void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks); |
737 | void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); | |
63cc5a4d TR |
738 | int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, |
739 | unsigned long *input_freqs, unsigned int num, | |
740 | unsigned int clk_m_div, unsigned long *osc_freq, | |
741 | unsigned long *pll_ref_freq); | |
a7c8485a PDS |
742 | void tegra_super_clk_gen4_init(void __iomem *clk_base, |
743 | void __iomem *pmc_base, struct tegra_clk *tegra_clks, | |
744 | struct tegra_clk_pll_params *pll_params); | |
139fd309 BH |
745 | void tegra_super_clk_gen5_init(void __iomem *clk_base, |
746 | void __iomem *pmc_base, struct tegra_clk *tegra_clks, | |
747 | struct tegra_clk_pll_params *pll_params); | |
de4f30fd | 748 | |
31b52ba4 | 749 | #ifdef CONFIG_TEGRA_CLK_EMC |
2db04f16 MP |
750 | struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, |
751 | spinlock_t *lock); | |
31b52ba4 TR |
752 | #else |
753 | static inline struct clk *tegra_clk_register_emc(void __iomem *base, | |
754 | struct device_node *np, | |
755 | spinlock_t *lock) | |
756 | { | |
757 | return NULL; | |
758 | } | |
759 | #endif | |
2db04f16 | 760 | |
25c9ded6 PW |
761 | void tegra114_clock_tune_cpu_trimmers_high(void); |
762 | void tegra114_clock_tune_cpu_trimmers_low(void); | |
763 | void tegra114_clock_tune_cpu_trimmers_init(void); | |
1c472d8e PW |
764 | void tegra114_clock_assert_dfll_dvco_reset(void); |
765 | void tegra114_clock_deassert_dfll_dvco_reset(void); | |
25c9ded6 | 766 | |
441f199a SW |
767 | typedef void (*tegra_clk_apply_init_table_func)(void); |
768 | extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; | |
6583a630 | 769 | int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); |
407254da | 770 | u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); |
6b301a05 | 771 | int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); |
441f199a | 772 | |
8f8f484b | 773 | #endif /* TEGRA_CLK_H */ |