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45622e21 TK |
1 | /* |
2 | * AM33XX Clock init | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc | |
5 | * Tero Kristo (t-kristo@ti.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/list.h> | |
1b29e601 | 19 | #include <linux/clk.h> |
45622e21 TK |
20 | #include <linux/clk-provider.h> |
21 | #include <linux/clk/ti.h> | |
22 | ||
a5aa8a60 TK |
23 | #include "clock.h" |
24 | ||
45622e21 TK |
25 | static struct ti_dt_clk am33xx_clks[] = { |
26 | DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), | |
27 | DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), | |
28 | DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), | |
29 | DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), | |
30 | DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), | |
31 | DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), | |
32 | DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), | |
33 | DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), | |
34 | DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), | |
35 | DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), | |
36 | DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), | |
37 | DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), | |
38 | DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), | |
39 | DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), | |
45622e21 TK |
40 | DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), |
41 | DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), | |
42 | DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), | |
43 | DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"), | |
44 | DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), | |
45 | DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), | |
46 | DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), | |
47 | DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), | |
48 | DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), | |
49 | DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), | |
50 | DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), | |
51 | DT_CLK(NULL, "cefuse_fck", "cefuse_fck"), | |
52 | DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), | |
53 | DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), | |
54 | DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), | |
55 | DT_CLK("481cc000.d_can", NULL, "dcan0_fck"), | |
56 | DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), | |
57 | DT_CLK("481d0000.d_can", NULL, "dcan1_fck"), | |
58 | DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), | |
59 | DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), | |
60 | DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), | |
61 | DT_CLK(NULL, "mmu_fck", "mmu_fck"), | |
62 | DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), | |
63 | DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), | |
64 | DT_CLK(NULL, "sha0_fck", "sha0_fck"), | |
65 | DT_CLK(NULL, "aes0_fck", "aes0_fck"), | |
66 | DT_CLK(NULL, "rng_fck", "rng_fck"), | |
67 | DT_CLK(NULL, "timer1_fck", "timer1_fck"), | |
68 | DT_CLK(NULL, "timer2_fck", "timer2_fck"), | |
69 | DT_CLK(NULL, "timer3_fck", "timer3_fck"), | |
70 | DT_CLK(NULL, "timer4_fck", "timer4_fck"), | |
71 | DT_CLK(NULL, "timer5_fck", "timer5_fck"), | |
72 | DT_CLK(NULL, "timer6_fck", "timer6_fck"), | |
73 | DT_CLK(NULL, "timer7_fck", "timer7_fck"), | |
74 | DT_CLK(NULL, "usbotg_fck", "usbotg_fck"), | |
75 | DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"), | |
76 | DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), | |
77 | DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"), | |
78 | DT_CLK(NULL, "l3_gclk", "l3_gclk"), | |
79 | DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), | |
80 | DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), | |
81 | DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), | |
82 | DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"), | |
83 | DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), | |
84 | DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), | |
85 | DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"), | |
86 | DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), | |
87 | DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), | |
88 | DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), | |
89 | DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), | |
90 | DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), | |
91 | DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), | |
92 | DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), | |
93 | DT_CLK(NULL, "lcd_gclk", "lcd_gclk"), | |
94 | DT_CLK(NULL, "mmc_clk", "mmc_clk"), | |
95 | DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), | |
96 | DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), | |
97 | DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"), | |
98 | DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"), | |
99 | DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), | |
100 | DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), | |
101 | DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"), | |
102 | DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"), | |
103 | DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"), | |
104 | DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"), | |
105 | DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), | |
106 | DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), | |
107 | DT_CLK(NULL, "clkout2_ck", "clkout2_ck"), | |
108 | DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), | |
109 | DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), | |
110 | DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), | |
111 | { .node_name = NULL }, | |
112 | }; | |
113 | ||
114 | static const char *enable_init_clks[] = { | |
115 | "dpll_ddr_m2_ck", | |
116 | "dpll_mpu_m2_ck", | |
117 | "l3_gclk", | |
118 | "l4hs_gclk", | |
119 | "l4fw_gclk", | |
120 | "l4ls_gclk", | |
121 | /* Required for external peripherals like, Audio codecs */ | |
122 | "clkout2_ck", | |
123 | }; | |
124 | ||
125 | int __init am33xx_dt_clk_init(void) | |
126 | { | |
127 | struct clk *clk1, *clk2; | |
128 | ||
129 | ti_dt_clocks_register(am33xx_clks); | |
130 | ||
131 | omap2_clk_disable_autoidle_all(); | |
132 | ||
133 | omap2_clk_enable_init_clocks(enable_init_clks, | |
134 | ARRAY_SIZE(enable_init_clks)); | |
135 | ||
136 | /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always | |
137 | * physically present, in such a case HWMOD enabling of | |
138 | * clock would be failure with default parent. And timer | |
139 | * probe thinks clock is already enabled, this leads to | |
140 | * crash upon accessing timer 3 & 6 registers in probe. | |
141 | * Fix by setting parent of both these timers to master | |
142 | * oscillator clock. | |
143 | */ | |
144 | ||
145 | clk1 = clk_get_sys(NULL, "sys_clkin_ck"); | |
146 | clk2 = clk_get_sys(NULL, "timer3_fck"); | |
147 | clk_set_parent(clk2, clk1); | |
148 | ||
149 | clk2 = clk_get_sys(NULL, "timer6_fck"); | |
150 | clk_set_parent(clk2, clk1); | |
151 | /* | |
152 | * The On-Chip 32K RC Osc clock is not an accurate clock-source as per | |
153 | * the design/spec, so as a result, for example, timer which supposed | |
154 | * to get expired @60Sec, but will expire somewhere ~@40Sec, which is | |
155 | * not expected by any use-case, so change WDT1 clock source to PRCM | |
156 | * 32KHz clock. | |
157 | */ | |
158 | clk1 = clk_get_sys(NULL, "wdt1_fck"); | |
159 | clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); | |
160 | clk_set_parent(clk1, clk2); | |
161 | ||
162 | return 0; | |
163 | } |