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aafd900c TK |
1 | /* |
2 | * OMAP3 Clock init | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc | |
5 | * Tero Kristo (t-kristo@ti.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/list.h> | |
19 | #include <linux/clk-provider.h> | |
20 | #include <linux/clk/ti.h> | |
21 | ||
22 | ||
23 | static struct ti_dt_clk omap3xxx_clks[] = { | |
24 | DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"), | |
25 | DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"), | |
26 | DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"), | |
27 | DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"), | |
28 | DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), | |
29 | DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), | |
30 | DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"), | |
31 | DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"), | |
32 | DT_CLK("twl", "fck", "osc_sys_ck"), | |
33 | DT_CLK(NULL, "sys_ck", "sys_ck"), | |
34 | DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"), | |
35 | DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"), | |
36 | DT_CLK(NULL, "sys_altclk", "sys_altclk"), | |
37 | DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"), | |
38 | DT_CLK(NULL, "sys_clkout1", "sys_clkout1"), | |
39 | DT_CLK(NULL, "dpll1_ck", "dpll1_ck"), | |
40 | DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"), | |
41 | DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"), | |
42 | DT_CLK(NULL, "dpll3_ck", "dpll3_ck"), | |
43 | DT_CLK(NULL, "core_ck", "core_ck"), | |
44 | DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"), | |
45 | DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"), | |
46 | DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"), | |
47 | DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"), | |
48 | DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"), | |
49 | DT_CLK(NULL, "dpll4_ck", "dpll4_ck"), | |
50 | DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"), | |
51 | DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"), | |
52 | DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"), | |
53 | DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"), | |
54 | DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"), | |
55 | DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"), | |
56 | DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"), | |
57 | DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"), | |
58 | DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"), | |
59 | DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"), | |
60 | DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"), | |
61 | DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"), | |
62 | DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"), | |
63 | DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"), | |
64 | DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"), | |
65 | DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"), | |
66 | DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"), | |
67 | DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"), | |
68 | DT_CLK(NULL, "sys_clkout2", "sys_clkout2"), | |
69 | DT_CLK(NULL, "corex2_fck", "corex2_fck"), | |
70 | DT_CLK(NULL, "dpll1_fck", "dpll1_fck"), | |
71 | DT_CLK(NULL, "mpu_ck", "mpu_ck"), | |
72 | DT_CLK(NULL, "arm_fck", "arm_fck"), | |
73 | DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"), | |
74 | DT_CLK(NULL, "l3_ick", "l3_ick"), | |
75 | DT_CLK(NULL, "l4_ick", "l4_ick"), | |
76 | DT_CLK(NULL, "rm_ick", "rm_ick"), | |
77 | DT_CLK(NULL, "gpt10_fck", "gpt10_fck"), | |
78 | DT_CLK(NULL, "gpt11_fck", "gpt11_fck"), | |
79 | DT_CLK(NULL, "core_96m_fck", "core_96m_fck"), | |
80 | DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"), | |
81 | DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"), | |
82 | DT_CLK(NULL, "i2c3_fck", "i2c3_fck"), | |
83 | DT_CLK(NULL, "i2c2_fck", "i2c2_fck"), | |
84 | DT_CLK(NULL, "i2c1_fck", "i2c1_fck"), | |
85 | DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"), | |
86 | DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"), | |
87 | DT_CLK(NULL, "core_48m_fck", "core_48m_fck"), | |
88 | DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"), | |
89 | DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"), | |
90 | DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"), | |
91 | DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"), | |
92 | DT_CLK(NULL, "uart2_fck", "uart2_fck"), | |
93 | DT_CLK(NULL, "uart1_fck", "uart1_fck"), | |
94 | DT_CLK(NULL, "core_12m_fck", "core_12m_fck"), | |
95 | DT_CLK("omap_hdq.0", "fck", "hdq_fck"), | |
96 | DT_CLK(NULL, "hdq_fck", "hdq_fck"), | |
97 | DT_CLK(NULL, "core_l3_ick", "core_l3_ick"), | |
98 | DT_CLK(NULL, "sdrc_ick", "sdrc_ick"), | |
99 | DT_CLK(NULL, "gpmc_fck", "gpmc_fck"), | |
100 | DT_CLK(NULL, "core_l4_ick", "core_l4_ick"), | |
101 | DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"), | |
102 | DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"), | |
103 | DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"), | |
104 | DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"), | |
105 | DT_CLK("omap_hdq.0", "ick", "hdq_ick"), | |
106 | DT_CLK(NULL, "hdq_ick", "hdq_ick"), | |
107 | DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"), | |
108 | DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"), | |
109 | DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"), | |
110 | DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"), | |
111 | DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"), | |
112 | DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"), | |
113 | DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"), | |
114 | DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"), | |
115 | DT_CLK("omap_i2c.3", "ick", "i2c3_ick"), | |
116 | DT_CLK("omap_i2c.2", "ick", "i2c2_ick"), | |
117 | DT_CLK("omap_i2c.1", "ick", "i2c1_ick"), | |
118 | DT_CLK(NULL, "i2c3_ick", "i2c3_ick"), | |
119 | DT_CLK(NULL, "i2c2_ick", "i2c2_ick"), | |
120 | DT_CLK(NULL, "i2c1_ick", "i2c1_ick"), | |
121 | DT_CLK(NULL, "uart2_ick", "uart2_ick"), | |
122 | DT_CLK(NULL, "uart1_ick", "uart1_ick"), | |
123 | DT_CLK(NULL, "gpt11_ick", "gpt11_ick"), | |
124 | DT_CLK(NULL, "gpt10_ick", "gpt10_ick"), | |
125 | DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"), | |
126 | DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"), | |
127 | DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"), | |
128 | DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"), | |
129 | DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"), | |
130 | DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"), | |
131 | DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"), | |
132 | DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"), | |
133 | DT_CLK(NULL, "utmi_p1_gfclk", "dummy_ck"), | |
134 | DT_CLK(NULL, "utmi_p2_gfclk", "dummy_ck"), | |
135 | DT_CLK(NULL, "xclk60mhsp1_ck", "dummy_ck"), | |
136 | DT_CLK(NULL, "xclk60mhsp2_ck", "dummy_ck"), | |
137 | DT_CLK(NULL, "init_60m_fclk", "dummy_ck"), | |
138 | DT_CLK(NULL, "gpt1_fck", "gpt1_fck"), | |
139 | DT_CLK(NULL, "aes2_ick", "aes2_ick"), | |
140 | DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"), | |
141 | DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"), | |
142 | DT_CLK(NULL, "sha12_ick", "sha12_ick"), | |
143 | DT_CLK(NULL, "wdt2_fck", "wdt2_fck"), | |
144 | DT_CLK("omap_wdt", "ick", "wdt2_ick"), | |
145 | DT_CLK(NULL, "wdt2_ick", "wdt2_ick"), | |
146 | DT_CLK(NULL, "wdt1_ick", "wdt1_ick"), | |
147 | DT_CLK(NULL, "gpio1_ick", "gpio1_ick"), | |
148 | DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"), | |
149 | DT_CLK(NULL, "gpt12_ick", "gpt12_ick"), | |
150 | DT_CLK(NULL, "gpt1_ick", "gpt1_ick"), | |
151 | DT_CLK(NULL, "per_96m_fck", "per_96m_fck"), | |
152 | DT_CLK(NULL, "per_48m_fck", "per_48m_fck"), | |
153 | DT_CLK(NULL, "uart3_fck", "uart3_fck"), | |
154 | DT_CLK(NULL, "gpt2_fck", "gpt2_fck"), | |
155 | DT_CLK(NULL, "gpt3_fck", "gpt3_fck"), | |
156 | DT_CLK(NULL, "gpt4_fck", "gpt4_fck"), | |
157 | DT_CLK(NULL, "gpt5_fck", "gpt5_fck"), | |
158 | DT_CLK(NULL, "gpt6_fck", "gpt6_fck"), | |
159 | DT_CLK(NULL, "gpt7_fck", "gpt7_fck"), | |
160 | DT_CLK(NULL, "gpt8_fck", "gpt8_fck"), | |
161 | DT_CLK(NULL, "gpt9_fck", "gpt9_fck"), | |
162 | DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"), | |
163 | DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"), | |
164 | DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"), | |
165 | DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"), | |
166 | DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"), | |
167 | DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"), | |
168 | DT_CLK(NULL, "wdt3_fck", "wdt3_fck"), | |
169 | DT_CLK(NULL, "per_l4_ick", "per_l4_ick"), | |
170 | DT_CLK(NULL, "gpio6_ick", "gpio6_ick"), | |
171 | DT_CLK(NULL, "gpio5_ick", "gpio5_ick"), | |
172 | DT_CLK(NULL, "gpio4_ick", "gpio4_ick"), | |
173 | DT_CLK(NULL, "gpio3_ick", "gpio3_ick"), | |
174 | DT_CLK(NULL, "gpio2_ick", "gpio2_ick"), | |
175 | DT_CLK(NULL, "wdt3_ick", "wdt3_ick"), | |
176 | DT_CLK(NULL, "uart3_ick", "uart3_ick"), | |
177 | DT_CLK(NULL, "uart4_ick", "uart4_ick"), | |
178 | DT_CLK(NULL, "gpt9_ick", "gpt9_ick"), | |
179 | DT_CLK(NULL, "gpt8_ick", "gpt8_ick"), | |
180 | DT_CLK(NULL, "gpt7_ick", "gpt7_ick"), | |
181 | DT_CLK(NULL, "gpt6_ick", "gpt6_ick"), | |
182 | DT_CLK(NULL, "gpt5_ick", "gpt5_ick"), | |
183 | DT_CLK(NULL, "gpt4_ick", "gpt4_ick"), | |
184 | DT_CLK(NULL, "gpt3_ick", "gpt3_ick"), | |
185 | DT_CLK(NULL, "gpt2_ick", "gpt2_ick"), | |
186 | DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"), | |
187 | DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"), | |
188 | DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"), | |
189 | DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"), | |
190 | DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"), | |
191 | DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"), | |
192 | DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"), | |
193 | DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"), | |
194 | DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"), | |
195 | DT_CLK("etb", "emu_src_ck", "emu_src_ck"), | |
196 | DT_CLK(NULL, "emu_src_ck", "emu_src_ck"), | |
197 | DT_CLK(NULL, "pclk_fck", "pclk_fck"), | |
198 | DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"), | |
199 | DT_CLK(NULL, "atclk_fck", "atclk_fck"), | |
200 | DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"), | |
201 | DT_CLK(NULL, "traceclk_fck", "traceclk_fck"), | |
202 | DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"), | |
203 | DT_CLK(NULL, "gpt12_fck", "gpt12_fck"), | |
204 | DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), | |
205 | DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"), | |
206 | DT_CLK(NULL, "timer_sys_ck", "sys_ck"), | |
207 | DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"), | |
208 | { .node_name = NULL }, | |
209 | }; | |
210 | ||
211 | static struct ti_dt_clk omap34xx_omap36xx_clks[] = { | |
212 | DT_CLK(NULL, "aes1_ick", "aes1_ick"), | |
213 | DT_CLK("omap_rng", "ick", "rng_ick"), | |
214 | DT_CLK("omap3-rom-rng", "ick", "rng_ick"), | |
215 | DT_CLK(NULL, "sha11_ick", "sha11_ick"), | |
216 | DT_CLK(NULL, "des1_ick", "des1_ick"), | |
217 | DT_CLK(NULL, "cam_mclk", "cam_mclk"), | |
218 | DT_CLK(NULL, "cam_ick", "cam_ick"), | |
219 | DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"), | |
220 | DT_CLK(NULL, "security_l3_ick", "security_l3_ick"), | |
221 | DT_CLK(NULL, "pka_ick", "pka_ick"), | |
222 | DT_CLK(NULL, "icr_ick", "icr_ick"), | |
223 | DT_CLK("omap-aes", "ick", "aes2_ick"), | |
224 | DT_CLK("omap-sham", "ick", "sha12_ick"), | |
225 | DT_CLK(NULL, "des2_ick", "des2_ick"), | |
226 | DT_CLK(NULL, "mspro_ick", "mspro_ick"), | |
227 | DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"), | |
228 | DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"), | |
229 | DT_CLK(NULL, "sr1_fck", "sr1_fck"), | |
230 | DT_CLK(NULL, "sr2_fck", "sr2_fck"), | |
231 | DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"), | |
232 | DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"), | |
233 | DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"), | |
234 | DT_CLK(NULL, "dpll2_fck", "dpll2_fck"), | |
235 | DT_CLK(NULL, "iva2_ck", "iva2_ck"), | |
236 | DT_CLK(NULL, "modem_fck", "modem_fck"), | |
237 | DT_CLK(NULL, "sad2d_ick", "sad2d_ick"), | |
238 | DT_CLK(NULL, "mad2d_ick", "mad2d_ick"), | |
239 | DT_CLK(NULL, "mspro_fck", "mspro_fck"), | |
240 | DT_CLK(NULL, "dpll2_ck", "dpll2_ck"), | |
241 | DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"), | |
242 | { .node_name = NULL }, | |
243 | }; | |
244 | ||
245 | static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = { | |
246 | DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"), | |
247 | DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"), | |
248 | DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"), | |
249 | DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"), | |
250 | DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"), | |
251 | DT_CLK(NULL, "usim_fck", "usim_fck"), | |
252 | DT_CLK(NULL, "usim_ick", "usim_ick"), | |
253 | { .node_name = NULL }, | |
254 | }; | |
255 | ||
256 | static struct ti_dt_clk omap3430es1_clks[] = { | |
257 | DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"), | |
258 | DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"), | |
259 | DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"), | |
260 | DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"), | |
261 | DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"), | |
262 | DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"), | |
263 | DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"), | |
264 | DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"), | |
265 | DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"), | |
266 | DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"), | |
267 | DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"), | |
268 | DT_CLK(NULL, "fac_ick", "fac_ick"), | |
269 | DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"), | |
270 | DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"), | |
271 | DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"), | |
272 | DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"), | |
273 | DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"), | |
274 | { .node_name = NULL }, | |
275 | }; | |
276 | ||
277 | static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = { | |
278 | DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"), | |
279 | DT_CLK(NULL, "dpll5_ck", "dpll5_ck"), | |
280 | DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"), | |
281 | DT_CLK(NULL, "sgx_fck", "sgx_fck"), | |
282 | DT_CLK(NULL, "sgx_ick", "sgx_ick"), | |
283 | DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"), | |
284 | DT_CLK(NULL, "ts_fck", "ts_fck"), | |
285 | DT_CLK(NULL, "usbtll_fck", "usbtll_fck"), | |
286 | DT_CLK(NULL, "usbtll_ick", "usbtll_ick"), | |
287 | DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"), | |
288 | DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"), | |
289 | DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"), | |
290 | DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"), | |
291 | DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"), | |
292 | DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"), | |
293 | DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"), | |
294 | DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"), | |
295 | DT_CLK(NULL, "usbhost_ick", "usbhost_ick"), | |
296 | { .node_name = NULL }, | |
297 | }; | |
298 | ||
299 | static struct ti_dt_clk am35xx_clks[] = { | |
300 | DT_CLK(NULL, "ipss_ick", "ipss_ick"), | |
301 | DT_CLK(NULL, "rmii_ck", "rmii_ck"), | |
302 | DT_CLK(NULL, "pclk_ck", "pclk_ck"), | |
303 | DT_CLK(NULL, "emac_ick", "emac_ick"), | |
304 | DT_CLK(NULL, "emac_fck", "emac_fck"), | |
305 | DT_CLK("davinci_emac.0", NULL, "emac_ick"), | |
306 | DT_CLK("davinci_mdio.0", NULL, "emac_fck"), | |
307 | DT_CLK("vpfe-capture", "master", "vpfe_ick"), | |
308 | DT_CLK("vpfe-capture", "slave", "vpfe_fck"), | |
309 | DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"), | |
310 | DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"), | |
311 | DT_CLK(NULL, "hecc_ck", "hecc_ck"), | |
312 | DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"), | |
313 | DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"), | |
314 | { .node_name = NULL }, | |
315 | }; | |
316 | ||
317 | static struct ti_dt_clk omap36xx_clks[] = { | |
318 | DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"), | |
319 | DT_CLK(NULL, "uart4_fck", "uart4_fck"), | |
320 | { .node_name = NULL }, | |
321 | }; | |
322 | ||
323 | static const char *enable_init_clks[] = { | |
324 | "sdrc_ick", | |
325 | "gpmc_fck", | |
326 | "omapctrl_ick", | |
327 | }; | |
328 | ||
329 | enum { | |
330 | OMAP3_SOC_AM35XX, | |
331 | OMAP3_SOC_OMAP3430_ES1, | |
332 | OMAP3_SOC_OMAP3430_ES2_PLUS, | |
333 | OMAP3_SOC_OMAP3630, | |
334 | OMAP3_SOC_TI81XX, | |
335 | }; | |
336 | ||
337 | static int __init omap3xxx_dt_clk_init(int soc_type) | |
338 | { | |
339 | if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 || | |
340 | soc_type == OMAP3_SOC_OMAP3430_ES1 || | |
341 | soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS) | |
342 | ti_dt_clocks_register(omap3xxx_clks); | |
343 | ||
344 | if (soc_type == OMAP3_SOC_AM35XX) | |
345 | ti_dt_clocks_register(am35xx_clks); | |
346 | ||
347 | if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX || | |
348 | soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS) | |
349 | ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks); | |
350 | ||
351 | if (soc_type == OMAP3_SOC_OMAP3430_ES1) | |
352 | ti_dt_clocks_register(omap3430es1_clks); | |
353 | ||
354 | if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS || | |
355 | soc_type == OMAP3_SOC_OMAP3630) | |
356 | ti_dt_clocks_register(omap36xx_omap3430es2plus_clks); | |
357 | ||
358 | if (soc_type == OMAP3_SOC_OMAP3430_ES1 || | |
359 | soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS || | |
360 | soc_type == OMAP3_SOC_OMAP3630) | |
361 | ti_dt_clocks_register(omap34xx_omap36xx_clks); | |
362 | ||
363 | if (soc_type == OMAP3_SOC_OMAP3630) | |
364 | ti_dt_clocks_register(omap36xx_clks); | |
365 | ||
366 | omap2_clk_disable_autoidle_all(); | |
367 | ||
368 | omap2_clk_enable_init_clocks(enable_init_clks, | |
369 | ARRAY_SIZE(enable_init_clks)); | |
370 | ||
371 | pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", | |
372 | (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000), | |
373 | (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, | |
374 | (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000), | |
375 | (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000)); | |
376 | ||
377 | if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1) | |
378 | omap3_clk_lock_dpll5(); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | int __init omap3430_dt_clk_init(void) | |
384 | { | |
385 | return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS); | |
386 | } | |
387 | ||
388 | int __init omap3630_dt_clk_init(void) | |
389 | { | |
390 | return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630); | |
391 | } | |
392 | ||
393 | int __init am35xx_dt_clk_init(void) | |
394 | { | |
395 | return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX); | |
396 | } | |
397 | ||
398 | int __init ti81xx_dt_clk_init(void) | |
399 | { | |
400 | return omap3xxx_dt_clk_init(OMAP3_SOC_TI81XX); | |
401 | } |