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c82f8957 TK |
1 | /* |
2 | * TI Clock driver internal definitions | |
3 | * | |
4 | * Copyright (C) 2014 Texas Instruments, Inc | |
5 | * Tero Kristo (t-kristo@ti.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | #ifndef __DRIVERS_CLK_TI_CLOCK__ | |
17 | #define __DRIVERS_CLK_TI_CLOCK__ | |
18 | ||
19 | enum { | |
20 | TI_CLK_FIXED, | |
21 | TI_CLK_MUX, | |
22 | TI_CLK_DIVIDER, | |
23 | TI_CLK_COMPOSITE, | |
24 | TI_CLK_FIXED_FACTOR, | |
25 | TI_CLK_GATE, | |
26 | TI_CLK_DPLL, | |
27 | }; | |
28 | ||
29 | /* Global flags */ | |
30 | #define CLKF_INDEX_POWER_OF_TWO (1 << 0) | |
31 | #define CLKF_INDEX_STARTS_AT_ONE (1 << 1) | |
32 | #define CLKF_SET_RATE_PARENT (1 << 2) | |
33 | #define CLKF_OMAP3 (1 << 3) | |
34 | #define CLKF_AM35XX (1 << 4) | |
35 | ||
36 | /* Gate flags */ | |
37 | #define CLKF_SET_BIT_TO_DISABLE (1 << 5) | |
38 | #define CLKF_INTERFACE (1 << 6) | |
39 | #define CLKF_SSI (1 << 7) | |
40 | #define CLKF_DSS (1 << 8) | |
41 | #define CLKF_HSOTGUSB (1 << 9) | |
42 | #define CLKF_WAIT (1 << 10) | |
43 | #define CLKF_NO_WAIT (1 << 11) | |
44 | #define CLKF_HSDIV (1 << 12) | |
45 | #define CLKF_CLKDM (1 << 13) | |
46 | ||
47 | /* DPLL flags */ | |
48 | #define CLKF_LOW_POWER_STOP (1 << 5) | |
49 | #define CLKF_LOCK (1 << 6) | |
50 | #define CLKF_LOW_POWER_BYPASS (1 << 7) | |
51 | #define CLKF_PER (1 << 8) | |
52 | #define CLKF_CORE (1 << 9) | |
53 | #define CLKF_J_TYPE (1 << 10) | |
54 | ||
55 | #define CLK(dev, con, ck) \ | |
56 | { \ | |
57 | .lk = { \ | |
58 | .dev_id = dev, \ | |
59 | .con_id = con, \ | |
60 | }, \ | |
61 | .clk = ck, \ | |
62 | } | |
63 | ||
64 | struct ti_clk { | |
65 | const char *name; | |
66 | const char *clkdm_name; | |
67 | int type; | |
68 | void *data; | |
69 | struct ti_clk *patch; | |
70 | struct clk *clk; | |
71 | }; | |
72 | ||
73 | struct ti_clk_alias { | |
74 | struct ti_clk *clk; | |
75 | struct clk_lookup lk; | |
76 | struct list_head link; | |
77 | }; | |
78 | ||
79 | struct ti_clk_fixed { | |
80 | u32 frequency; | |
81 | u16 flags; | |
82 | }; | |
83 | ||
84 | struct ti_clk_mux { | |
85 | u8 bit_shift; | |
86 | int num_parents; | |
87 | u16 reg; | |
88 | u8 module; | |
89 | const char **parents; | |
90 | u16 flags; | |
91 | }; | |
92 | ||
93 | struct ti_clk_divider { | |
94 | const char *parent; | |
95 | u8 bit_shift; | |
96 | u16 max_div; | |
97 | u16 reg; | |
98 | u8 module; | |
99 | int *dividers; | |
100 | int num_dividers; | |
101 | u16 flags; | |
102 | }; | |
103 | ||
104 | struct ti_clk_fixed_factor { | |
105 | const char *parent; | |
106 | u16 div; | |
107 | u16 mult; | |
108 | u16 flags; | |
109 | }; | |
110 | ||
111 | struct ti_clk_gate { | |
112 | const char *parent; | |
113 | u8 bit_shift; | |
114 | u16 reg; | |
115 | u8 module; | |
116 | u16 flags; | |
117 | }; | |
118 | ||
119 | struct ti_clk_composite { | |
120 | struct ti_clk_divider *divider; | |
121 | struct ti_clk_mux *mux; | |
122 | struct ti_clk_gate *gate; | |
123 | u16 flags; | |
124 | }; | |
125 | ||
126 | struct ti_clk_clkdm_gate { | |
127 | const char *parent; | |
128 | u16 flags; | |
129 | }; | |
130 | ||
131 | struct ti_clk_dpll { | |
132 | int num_parents; | |
133 | u16 control_reg; | |
134 | u16 idlest_reg; | |
135 | u16 autoidle_reg; | |
136 | u16 mult_div1_reg; | |
137 | u8 module; | |
138 | const char **parents; | |
139 | u16 flags; | |
140 | u8 modes; | |
141 | u32 mult_mask; | |
142 | u32 div1_mask; | |
143 | u32 enable_mask; | |
144 | u32 autoidle_mask; | |
145 | u32 freqsel_mask; | |
146 | u32 idlest_mask; | |
147 | u32 dco_mask; | |
148 | u32 sddiv_mask; | |
149 | u16 max_multiplier; | |
150 | u16 max_divider; | |
ed405a23 | 151 | u8 min_divider; |
c82f8957 TK |
152 | u8 auto_recal_bit; |
153 | u8 recal_en_bit; | |
154 | u8 recal_st_bit; | |
155 | }; | |
156 | ||
a3314e9c TK |
157 | /* Composite clock component types */ |
158 | enum { | |
159 | CLK_COMPONENT_TYPE_GATE = 0, | |
160 | CLK_COMPONENT_TYPE_DIVIDER, | |
161 | CLK_COMPONENT_TYPE_MUX, | |
162 | CLK_COMPONENT_TYPE_MAX, | |
163 | }; | |
164 | ||
165 | /** | |
166 | * struct ti_dt_clk - OMAP DT clock alias declarations | |
167 | * @lk: clock lookup definition | |
168 | * @node_name: clock DT node to map to | |
169 | */ | |
170 | struct ti_dt_clk { | |
171 | struct clk_lookup lk; | |
172 | char *node_name; | |
173 | }; | |
174 | ||
175 | #define DT_CLK(dev, con, name) \ | |
176 | { \ | |
177 | .lk = { \ | |
178 | .dev_id = dev, \ | |
179 | .con_id = con, \ | |
180 | }, \ | |
181 | .node_name = name, \ | |
182 | } | |
183 | ||
184 | typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); | |
185 | ||
f187616b | 186 | struct clk *ti_clk_register_gate(struct ti_clk *setup); |
06524fa4 | 187 | struct clk *ti_clk_register_interface(struct ti_clk *setup); |
7c18a65c | 188 | struct clk *ti_clk_register_mux(struct ti_clk *setup); |
d96f774b | 189 | struct clk *ti_clk_register_divider(struct ti_clk *setup); |
b26bcf9b | 190 | struct clk *ti_clk_register_composite(struct ti_clk *setup); |
ed405a23 | 191 | struct clk *ti_clk_register_dpll(struct ti_clk *setup); |
7c18a65c | 192 | |
d96f774b | 193 | struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup); |
f187616b | 194 | struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup); |
7c18a65c TK |
195 | struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); |
196 | ||
c82f8957 TK |
197 | void ti_clk_patch_legacy_clks(struct ti_clk **patch); |
198 | struct clk *ti_clk_register_clk(struct ti_clk *setup); | |
199 | int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); | |
200 | ||
a3314e9c TK |
201 | void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); |
202 | void ti_dt_clocks_register(struct ti_dt_clk *oclks); | |
203 | int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, | |
204 | ti_of_clk_init_cb_t func); | |
205 | int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); | |
206 | ||
a53ad8ef | 207 | void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw); |
bf22bae7 | 208 | int of_ti_clk_autoidle_setup(struct device_node *node); |
a5aa8a60 | 209 | void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); |
bf22bae7 | 210 | |
0565fb16 | 211 | extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; |
59245ce0 | 212 | extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; |
9f37e90e | 213 | extern const struct clk_hw_omap_ops clkhwops_wait; |
ef14db09 TK |
214 | extern const struct clk_hw_omap_ops clkhwops_iclk; |
215 | extern const struct clk_hw_omap_ops clkhwops_iclk_wait; | |
d5a04ddd | 216 | extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; |
f2671d5c TK |
217 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; |
218 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; | |
219 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; | |
220 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; | |
c9a58b0a TK |
221 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; |
222 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; | |
59245ce0 | 223 | |
a3314e9c TK |
224 | extern const struct clk_ops ti_clk_divider_ops; |
225 | extern const struct clk_ops ti_clk_mux_ops; | |
226 | ||
bd86cfdc TK |
227 | int omap2_clkops_enable_clkdm(struct clk_hw *hw); |
228 | void omap2_clkops_disable_clkdm(struct clk_hw *hw); | |
229 | ||
9f37e90e TK |
230 | int omap2_dflt_clk_enable(struct clk_hw *hw); |
231 | void omap2_dflt_clk_disable(struct clk_hw *hw); | |
232 | int omap2_dflt_clk_is_enabled(struct clk_hw *hw); | |
a3314e9c TK |
233 | void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, |
234 | void __iomem **other_reg, | |
235 | u8 *other_bit); | |
236 | void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, | |
237 | void __iomem **idlest_reg, | |
238 | u8 *idlest_bit, u8 *idlest_val); | |
239 | ||
240 | void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); | |
241 | void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); | |
9f37e90e | 242 | |
b138b028 | 243 | u8 omap2_init_dpll_parent(struct clk_hw *hw); |
0565fb16 TK |
244 | int omap3_noncore_dpll_enable(struct clk_hw *hw); |
245 | void omap3_noncore_dpll_disable(struct clk_hw *hw); | |
246 | int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); | |
247 | int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, | |
248 | unsigned long parent_rate); | |
249 | int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, | |
250 | unsigned long rate, | |
251 | unsigned long parent_rate, | |
252 | u8 index); | |
4d341056 SB |
253 | int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, |
254 | struct clk_rate_request *req); | |
0565fb16 TK |
255 | long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, |
256 | unsigned long *parent_rate); | |
257 | unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, | |
258 | unsigned long parent_rate); | |
259 | ||
260 | unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); | |
261 | int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, | |
262 | unsigned long parent_rate); | |
263 | int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, | |
264 | unsigned long parent_rate, u8 index); | |
265 | void omap3_clk_lock_dpll5(void); | |
b138b028 | 266 | |
59245ce0 TK |
267 | unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, |
268 | unsigned long parent_rate); | |
269 | long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, | |
270 | unsigned long target_rate, | |
271 | unsigned long *parent_rate); | |
4d341056 SB |
272 | int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, |
273 | struct clk_rate_request *req); | |
59245ce0 | 274 | |
e9e63088 TK |
275 | extern struct ti_clk_ll_ops *ti_clk_ll_ops; |
276 | ||
c82f8957 | 277 | #endif |