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45228ef3 UH |
1 | /* |
2 | * abx500 clock implementation for ux500 platform. | |
3 | * | |
4 | * Copyright (C) 2012 ST-Ericsson SA | |
5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> | |
6 | * | |
7 | * License terms: GNU General Public License (GPL) version 2 | |
8 | */ | |
9 | ||
10 | #include <linux/err.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/mfd/abx500/ab8500.h> | |
312f0f0b UH |
15 | #include <linux/mfd/abx500/ab8500-sysctrl.h> |
16 | #include <linux/clk.h> | |
17 | #include <linux/clkdev.h> | |
18 | #include <linux/clk-provider.h> | |
19 | #include <linux/mfd/dbx500-prcmu.h> | |
20 | #include "clk.h" | |
45228ef3 UH |
21 | |
22 | /* Clock definitions for ab8500 */ | |
23 | static int ab8500_reg_clks(struct device *dev) | |
24 | { | |
312f0f0b UH |
25 | int ret; |
26 | struct clk *clk; | |
27 | ||
28 | const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"}; | |
29 | u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1}; | |
30 | u8 intclk_reg_mask[] = {0 , AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK}; | |
31 | u8 intclk_reg_bits[] = { | |
32 | 0 , | |
33 | (1 << AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT) | |
34 | }; | |
35 | ||
36 | dev_info(dev, "register clocks for ab850x\n"); | |
37 | ||
38 | /* Enable SWAT */ | |
39 | ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE); | |
40 | if (ret) | |
41 | return ret; | |
42 | ||
43 | /* ab8500_sysclk */ | |
44 | clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, | |
45 | CLK_IS_ROOT); | |
46 | clk_register_clkdev(clk, "sysclk", "ab8500-usb.0"); | |
47 | clk_register_clkdev(clk, "sysclk", "ab-iddet.0"); | |
20faa59e | 48 | clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0"); |
312f0f0b UH |
49 | clk_register_clkdev(clk, "sysclk", "shrm_bus"); |
50 | ||
51 | /* ab8500_sysclk2 */ | |
52 | clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk", | |
53 | AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, | |
54 | AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 0, 0); | |
55 | clk_register_clkdev(clk, "sysclk", "0-0070"); | |
56 | ||
57 | /* ab8500_sysclk3 */ | |
58 | clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk", | |
59 | AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, | |
60 | AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 0, 0); | |
61 | clk_register_clkdev(clk, "sysclk", "cg1960_core.0"); | |
62 | ||
63 | /* ab8500_sysclk4 */ | |
64 | clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk", | |
65 | AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, | |
66 | AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 0, 0); | |
67 | ||
68 | /* ab_ulpclk */ | |
69 | clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL, | |
70 | AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ, | |
71 | AB8500_SYSULPCLKCTRL1_ULPCLKREQ, | |
72 | 38400000, 9000, CLK_IS_ROOT); | |
20faa59e | 73 | clk_register_clkdev(clk, "ulpclk", "snd-soc-mop500.0"); |
312f0f0b UH |
74 | |
75 | /* ab8500_intclk */ | |
76 | clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2, | |
77 | intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0); | |
20faa59e | 78 | clk_register_clkdev(clk, "intclk", "snd-soc-mop500.0"); |
312f0f0b UH |
79 | clk_register_clkdev(clk, NULL, "ab8500-pwm.1"); |
80 | ||
81 | /* ab8500_audioclk */ | |
82 | clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk", | |
83 | AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, | |
84 | AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0); | |
20faa59e | 85 | clk_register_clkdev(clk, "audioclk", "ab8500-codec.0"); |
312f0f0b | 86 | |
45228ef3 UH |
87 | return 0; |
88 | } | |
89 | ||
90 | /* Clock definitions for ab8540 */ | |
91 | static int ab8540_reg_clks(struct device *dev) | |
92 | { | |
93 | return 0; | |
94 | } | |
95 | ||
96 | /* Clock definitions for ab9540 */ | |
97 | static int ab9540_reg_clks(struct device *dev) | |
98 | { | |
99 | return 0; | |
100 | } | |
101 | ||
0fe763c5 | 102 | static int abx500_clk_probe(struct platform_device *pdev) |
45228ef3 UH |
103 | { |
104 | struct ab8500 *parent = dev_get_drvdata(pdev->dev.parent); | |
105 | int ret; | |
106 | ||
107 | if (is_ab8500(parent) || is_ab8505(parent)) { | |
108 | ret = ab8500_reg_clks(&pdev->dev); | |
109 | } else if (is_ab8540(parent)) { | |
110 | ret = ab8540_reg_clks(&pdev->dev); | |
111 | } else if (is_ab9540(parent)) { | |
112 | ret = ab9540_reg_clks(&pdev->dev); | |
113 | } else { | |
114 | dev_err(&pdev->dev, "non supported plf id\n"); | |
115 | return -ENODEV; | |
116 | } | |
117 | ||
118 | return ret; | |
119 | } | |
120 | ||
121 | static struct platform_driver abx500_clk_driver = { | |
122 | .driver = { | |
123 | .name = "abx500-clk", | |
45228ef3 UH |
124 | }, |
125 | .probe = abx500_clk_probe, | |
126 | }; | |
127 | ||
128 | static int __init abx500_clk_init(void) | |
129 | { | |
130 | return platform_driver_register(&abx500_clk_driver); | |
131 | } | |
132 | ||
133 | arch_initcall(abx500_clk_init); | |
134 | ||
135 | MODULE_AUTHOR("Ulf Hansson <ulf.hansson@linaro.org"); | |
136 | MODULE_DESCRIPTION("ABX500 clk driver"); | |
137 | MODULE_LICENSE("GPL v2"); |