Commit | Line | Data |
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401301cc LW |
1 | /* |
2 | * Clock driver for the ARM RealView boards | |
3 | * Copyright (C) 2012 Linus Walleij | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
f9a6aa43 LW |
9 | #include <linux/clk.h> |
10 | #include <linux/clkdev.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/clk-provider.h> | |
14 | ||
15 | #include <mach/hardware.h> | |
16 | #include <mach/platform.h> | |
17 | ||
18 | #include "clk-icst.h" | |
19 | ||
20 | /* | |
21 | * Implementation of the ARM RealView clock trees. | |
22 | */ | |
23 | ||
f9a6aa43 LW |
24 | static const struct icst_params realview_oscvco_params = { |
25 | .ref = 24000000, | |
26 | .vco_max = ICST307_VCO_MAX, | |
27 | .vco_min = ICST307_VCO_MIN, | |
28 | .vd_min = 4 + 8, | |
29 | .vd_max = 511 + 8, | |
30 | .rd_min = 1 + 2, | |
31 | .rd_max = 127 + 2, | |
32 | .s2div = icst307_s2div, | |
33 | .idx2s = icst307_idx2s, | |
34 | }; | |
35 | ||
7a9ad671 | 36 | static const struct clk_icst_desc __initdata realview_osc0_desc = { |
f9a6aa43 | 37 | .params = &realview_oscvco_params, |
7a9ad671 LW |
38 | .vco_offset = REALVIEW_SYS_OSC0_OFFSET, |
39 | .lock_offset = REALVIEW_SYS_LOCK_OFFSET, | |
40 | }; | |
41 | ||
42 | static const struct clk_icst_desc __initdata realview_osc4_desc = { | |
43 | .params = &realview_oscvco_params, | |
44 | .vco_offset = REALVIEW_SYS_OSC4_OFFSET, | |
45 | .lock_offset = REALVIEW_SYS_LOCK_OFFSET, | |
f9a6aa43 LW |
46 | }; |
47 | ||
48 | /* | |
49 | * realview_clk_init() - set up the RealView clock tree | |
50 | */ | |
51 | void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176) | |
52 | { | |
53 | struct clk *clk; | |
54 | ||
f9a6aa43 LW |
55 | /* APB clock dummy */ |
56 | clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); | |
57 | clk_register_clkdev(clk, "apb_pclk", NULL); | |
58 | ||
59 | /* 24 MHz clock */ | |
60 | clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT, | |
61 | 24000000); | |
62 | clk_register_clkdev(clk, NULL, "dev:uart0"); | |
63 | clk_register_clkdev(clk, NULL, "dev:uart1"); | |
64 | clk_register_clkdev(clk, NULL, "dev:uart2"); | |
65 | clk_register_clkdev(clk, NULL, "fpga:kmi0"); | |
66 | clk_register_clkdev(clk, NULL, "fpga:kmi1"); | |
67 | clk_register_clkdev(clk, NULL, "fpga:mmc0"); | |
68 | clk_register_clkdev(clk, NULL, "dev:ssp0"); | |
69 | if (is_pb1176) { | |
70 | /* | |
71 | * UART3 is on the dev chip in PB1176 | |
72 | * UART4 only exists in PB1176 | |
73 | */ | |
74 | clk_register_clkdev(clk, NULL, "dev:uart3"); | |
75 | clk_register_clkdev(clk, NULL, "dev:uart4"); | |
76 | } else | |
77 | clk_register_clkdev(clk, NULL, "fpga:uart3"); | |
78 | ||
79 | ||
80 | /* 1 MHz clock */ | |
81 | clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT, | |
82 | 1000000); | |
83 | clk_register_clkdev(clk, NULL, "sp804"); | |
84 | ||
85 | /* ICST VCO clock */ | |
7a9ad671 | 86 | if (is_pb1176) |
ae6e694e | 87 | clk = icst_clk_register(NULL, &realview_osc0_desc, |
bf6edb4b | 88 | "osc0", NULL, sysbase); |
7a9ad671 | 89 | else |
ae6e694e | 90 | clk = icst_clk_register(NULL, &realview_osc4_desc, |
bf6edb4b | 91 | "osc4", NULL, sysbase); |
7a9ad671 | 92 | |
f9a6aa43 LW |
93 | clk_register_clkdev(clk, NULL, "dev:clcd"); |
94 | clk_register_clkdev(clk, NULL, "issp:clcd"); | |
95 | } |