projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4958ebb3 MC |
1 | /* |
| 2 | * Copyright (C) Maxime Coquelin 2015 | |
| 3 | * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> | |
| 4 | * License terms: GNU General Public License (GPL), version 2 | |
| 5 | */ | |
| 6 | ||
| 7 | #include <linux/kernel.h> | |
| 8 | #include <linux/clocksource.h> | |
| 9 | #include <linux/clockchips.h> | |
| 10 | #include <linux/of.h> | |
| 11 | #include <linux/of_address.h> | |
| 12 | #include <linux/clk.h> | |
| 13 | #include <linux/bitops.h> | |
| 14 | ||
| 15 | #define SYST_CSR 0x00 | |
| 16 | #define SYST_RVR 0x04 | |
| 17 | #define SYST_CVR 0x08 | |
| 18 | #define SYST_CALIB 0x0c | |
| 19 | ||
| 20 | #define SYST_CSR_ENABLE BIT(0) | |
| 21 | ||
| 22 | #define SYSTICK_LOAD_RELOAD_MASK 0x00FFFFFF | |
| 23 | ||
| 802fa498 | 24 | static int __init system_timer_of_register(struct device_node *np) |
| 4958ebb3 MC |
25 | { |
| 26 | struct clk *clk = NULL; | |
| 27 | void __iomem *base; | |
| 28 | u32 rate; | |
| 29 | int ret; | |
| 30 | ||
| 31 | base = of_iomap(np, 0); | |
| 32 | if (!base) { | |
| 33 | pr_warn("system-timer: invalid base address\n"); | |
| 802fa498 | 34 | return -ENXIO; |
| 4958ebb3 MC |
35 | } |
| 36 | ||
| 37 | ret = of_property_read_u32(np, "clock-frequency", &rate); | |
| 38 | if (ret) { | |
| 39 | clk = of_clk_get(np, 0); | |
| 802fa498 DL |
40 | if (IS_ERR(clk)) { |
| 41 | ret = PTR_ERR(clk); | |
| 4958ebb3 | 42 | goto out_unmap; |
| 802fa498 | 43 | } |
| 4958ebb3 MC |
44 | |
| 45 | ret = clk_prepare_enable(clk); | |
| 46 | if (ret) | |
| 47 | goto out_clk_put; | |
| 48 | ||
| 49 | rate = clk_get_rate(clk); | |
| 802fa498 DL |
50 | if (!rate) { |
| 51 | ret = -EINVAL; | |
| 4958ebb3 | 52 | goto out_clk_disable; |
| 802fa498 | 53 | } |
| 4958ebb3 MC |
54 | } |
| 55 | ||
| 56 | writel_relaxed(SYSTICK_LOAD_RELOAD_MASK, base + SYST_RVR); | |
| 57 | writel_relaxed(SYST_CSR_ENABLE, base + SYST_CSR); | |
| 58 | ||
| 59 | ret = clocksource_mmio_init(base + SYST_CVR, "arm_system_timer", rate, | |
| 60 | 200, 24, clocksource_mmio_readl_down); | |
| 61 | if (ret) { | |
| 62 | pr_err("failed to init clocksource (%d)\n", ret); | |
| 63 | if (clk) | |
| 64 | goto out_clk_disable; | |
| 65 | else | |
| 66 | goto out_unmap; | |
| 67 | } | |
| 68 | ||
| 69 | pr_info("ARM System timer initialized as clocksource\n"); | |
| 70 | ||
| 802fa498 | 71 | return 0; |
| 4958ebb3 MC |
72 | |
| 73 | out_clk_disable: | |
| 74 | clk_disable_unprepare(clk); | |
| 75 | out_clk_put: | |
| 76 | clk_put(clk); | |
| 77 | out_unmap: | |
| 78 | iounmap(base); | |
| 79 | pr_warn("ARM System timer register failed (%d)\n", ret); | |
| 802fa498 DL |
80 | |
| 81 | return ret; | |
| 4958ebb3 MC |
82 | } |
| 83 | ||
| 802fa498 | 84 | CLOCKSOURCE_OF_DECLARE_RET(arm_systick, "arm,armv7m-systick", |
| 4958ebb3 | 85 | system_timer_of_register); |