[deliverable/linux.git] / drivers / clocksource / cadence_ttc_timer.c

/*
 * This file contains driver for the Cadence Triple Timer Counter Rev 06
 *
 *  Copyright (C) 2011-2013 Xilinx
 *
 * based on arch/mips/kernel/time.c timer driver
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/sched_clock.h>

/*
 * This driver configures the 2 16/32-bit count-up timers as follows:
 *
 * T1: Timer 1, clocksource for generic timekeeping
 * T2: Timer 2, clockevent source for hrtimers
 * T3: Timer 3, <unused>
 *
 * The input frequency to the timer module for emulation is 2.5MHz which is
 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
 * the timers are clocked at 78.125KHz (12.8 us resolution).

 * The input frequency to the timer module in silicon is configurable and
 * obtained from device tree. The pre-scaler of 32 is used.
 */

/*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
#define TTC_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
#define TTC_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
#define TTC_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
#define TTC_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
#define TTC_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
#define TTC_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */

#define TTC_CNT_CNTRL_DISABLE_MASK	0x1

#define TTC_CLK_CNTRL_CSRC_MASK		(1 << 5)	/* clock source */
#define TTC_CLK_CNTRL_PSV_MASK		0x1e
#define TTC_CLK_CNTRL_PSV_SHIFT		1

/*
 * Setup the timers to use pre-scaling, using a fixed value for now that will
 * work across most input frequency, but it may need to be more dynamic
 */
#define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
#define PRESCALE		2048	/* The exponent must match this */
#define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
#define CLK_CNTRL_PRESCALE_EN	1
#define CNT_CNTRL_RESET		(1 << 4)

#define MAX_F_ERR 50

/**
 * struct ttc_timer - This definition defines local timer structure
 *
 * @base_addr:	Base address of timer
 * @freq:	Timer input clock frequency
 * @clk:	Associated clock source
 * @clk_rate_change_nb	Notifier block for clock rate changes
 */
struct ttc_timer {
	void __iomem *base_addr;
	unsigned long freq;
	struct clk *clk;
	struct notifier_block clk_rate_change_nb;
};

#define to_ttc_timer(x) \
		container_of(x, struct ttc_timer, clk_rate_change_nb)

struct ttc_timer_clocksource {
	u32			scale_clk_ctrl_reg_old;
	u32			scale_clk_ctrl_reg_new;
	struct ttc_timer	ttc;
	struct clocksource	cs;
};

#define to_ttc_timer_clksrc(x) \
		container_of(x, struct ttc_timer_clocksource, cs)

struct ttc_timer_clockevent {
	struct ttc_timer		ttc;
	struct clock_event_device	ce;
};

#define to_ttc_timer_clkevent(x) \
		container_of(x, struct ttc_timer_clockevent, ce)

static void __iomem *ttc_sched_clock_val_reg;

/**
 * ttc_set_interval - Set the timer interval value
 *
 * @timer:	Pointer to the timer instance
 * @cycles:	Timer interval ticks
 **/
static void ttc_set_interval(struct ttc_timer *timer,
					unsigned long cycles)
{
	u32 ctrl_reg;

	/* Disable the counter, set the counter value  and re-enable counter */
	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);

	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);

	/*
	 * Reset the counter (0x10) so that it starts from 0, one-shot
	 * mode makes this needed for timing to be right.
	 */
	ctrl_reg |= CNT_CNTRL_RESET;
	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
}

/**
 * ttc_clock_event_interrupt - Clock event timer interrupt handler
 *
 * @irq:	IRQ number of the Timer
 * @dev_id:	void pointer to the ttc_timer instance
 *
 * returns: Always IRQ_HANDLED - success
 **/
static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
{
	struct ttc_timer_clockevent *ttce = dev_id;
	struct ttc_timer *timer = &ttce->ttc;

	/* Acknowledge the interrupt and call event handler */
	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);

	ttce->ce.event_handler(&ttce->ce);

	return IRQ_HANDLED;
}

/**
 * __ttc_clocksource_read - Reads the timer counter register
 *
 * returns: Current timer counter register value
 **/
static cycle_t __ttc_clocksource_read(struct clocksource *cs)
{
	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;

	return (cycle_t)readl_relaxed(timer->base_addr +
				TTC_COUNT_VAL_OFFSET);
}

static u64 notrace ttc_sched_clock_read(void)
{
	return readl_relaxed(ttc_sched_clock_val_reg);
}

/**
 * ttc_set_next_event - Sets the time interval for next event
 *
 * @cycles:	Timer interval ticks
 * @evt:	Address of clock event instance
 *
 * returns: Always 0 - success
 **/
static int ttc_set_next_event(unsigned long cycles,
					struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;

	ttc_set_interval(timer, cycles);
	return 0;
}

/**
 * ttc_set_mode - Sets the mode of timer
 *
 * @mode:	Mode to be set
 * @evt:	Address of clock event instance
 **/
static void ttc_set_mode(enum clock_event_mode mode,
					struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;
	u32 ctrl_reg;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq,
						PRESCALE * HZ));
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		ctrl_reg = readl_relaxed(timer->base_addr +
					TTC_CNT_CNTRL_OFFSET);
		ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
		writel_relaxed(ctrl_reg,
				timer->base_addr + TTC_CNT_CNTRL_OFFSET);
		break;
	case CLOCK_EVT_MODE_RESUME:
		ctrl_reg = readl_relaxed(timer->base_addr +
					TTC_CNT_CNTRL_OFFSET);
		ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
		writel_relaxed(ctrl_reg,
				timer->base_addr + TTC_CNT_CNTRL_OFFSET);
		break;
	}
}

static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clocksource *ttccs = container_of(ttc,
			struct ttc_timer_clocksource, ttc);

	switch (event) {
	case PRE_RATE_CHANGE:
	{
		u32 psv;
		unsigned long factor, rate_low, rate_high;

		if (ndata->new_rate > ndata->old_rate) {
			factor = DIV_ROUND_CLOSEST(ndata->new_rate,
					ndata->old_rate);
			rate_low = ndata->old_rate;
			rate_high = ndata->new_rate;
		} else {
			factor = DIV_ROUND_CLOSEST(ndata->old_rate,
					ndata->new_rate);
			rate_low = ndata->new_rate;
			rate_high = ndata->old_rate;
		}

		if (!is_power_of_2(factor))
				return NOTIFY_BAD;

		if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
			return NOTIFY_BAD;

		factor = __ilog2_u32(factor);

		/*
		 * store timer clock ctrl register so we can restore it in case
		 * of an abort.
		 */
		ttccs->scale_clk_ctrl_reg_old =
			readl_relaxed(ttccs->ttc.base_addr +
			TTC_CLK_CNTRL_OFFSET);

		psv = (ttccs->scale_clk_ctrl_reg_old &
				TTC_CLK_CNTRL_PSV_MASK) >>
				TTC_CLK_CNTRL_PSV_SHIFT;
		if (ndata->new_rate < ndata->old_rate)
			psv -= factor;
		else
			psv += factor;

		/* prescaler within legal range? */
		if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
			return NOTIFY_BAD;

		ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
			~TTC_CLK_CNTRL_PSV_MASK;
		ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;


		/* scale down: adjust divider in post-change notification */
		if (ndata->new_rate < ndata->old_rate)
			return NOTIFY_DONE;

		/* scale up: adjust divider now - before frequency change */
		writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
		break;
	}
	case POST_RATE_CHANGE:
		/* scale up: pre-change notification did the adjustment */
		if (ndata->new_rate > ndata->old_rate)
			return NOTIFY_OK;

		/* scale down: adjust divider now - after frequency change */
		writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
		break;

	case ABORT_RATE_CHANGE:
		/* we have to undo the adjustment in case we scale up */
		if (ndata->new_rate < ndata->old_rate)
			return NOTIFY_OK;

		/* restore original register value */
		writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
		/* fall through */
	default:
		return NOTIFY_DONE;
	}

	return NOTIFY_DONE;
}

static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
					 u32 timer_width)
{
	struct ttc_timer_clocksource *ttccs;
	int err;

	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	if (WARN_ON(!ttccs))
		return;

	ttccs->ttc.clk = clk;

	err = clk_prepare_enable(ttccs->ttc.clk);
	if (WARN_ON(err)) {
		kfree(ttccs);
		return;
	}

	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);

	ttccs->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clocksource_cb;
	ttccs->ttc.clk_rate_change_nb.next = NULL;
	if (clk_notifier_register(ttccs->ttc.clk,
				&ttccs->ttc.clk_rate_change_nb))
		pr_warn("Unable to register clock notifier.\n");

	ttccs->ttc.base_addr = base;
	ttccs->cs.name = "ttc_clocksource";
	ttccs->cs.rating = 200;
	ttccs->cs.read = __ttc_clocksource_read;
	ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;

	/*
	 * Setup the clock source counter to be an incrementing counter
	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
	 * it by 32 also. Let it start running now.
	 */
	writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
	writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	writel_relaxed(CNT_CNTRL_RESET,
		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);

	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
	if (WARN_ON(err)) {
		kfree(ttccs);
		return;
	}

	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
	sched_clock_register(ttc_sched_clock_read, timer_width,
			     ttccs->ttc.freq / PRESCALE);
}

static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clockevent *ttcce = container_of(ttc,
			struct ttc_timer_clockevent, ttc);

	switch (event) {
	case POST_RATE_CHANGE:
		/* update cached frequency */
		ttc->freq = ndata->new_rate;

		clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);

		/* fall through */
	case PRE_RATE_CHANGE:
	case ABORT_RATE_CHANGE:
	default:
		return NOTIFY_DONE;
	}
}

static void __init ttc_setup_clockevent(struct clk *clk,
						void __iomem *base, u32 irq)
{
	struct ttc_timer_clockevent *ttcce;
	int err;

	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	if (WARN_ON(!ttcce))
		return;

	ttcce->ttc.clk = clk;

	err = clk_prepare_enable(ttcce->ttc.clk);
	if (WARN_ON(err)) {
		kfree(ttcce);
		return;
	}

	ttcce->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clockevent_cb;
	ttcce->ttc.clk_rate_change_nb.next = NULL;
	if (clk_notifier_register(ttcce->ttc.clk,
				&ttcce->ttc.clk_rate_change_nb))
		pr_warn("Unable to register clock notifier.\n");
	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);

	ttcce->ttc.base_addr = base;
	ttcce->ce.name = "ttc_clockevent";
	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	ttcce->ce.set_next_event = ttc_set_next_event;
	ttcce->ce.set_mode = ttc_set_mode;
	ttcce->ce.rating = 200;
	ttcce->ce.irq = irq;
	ttcce->ce.cpumask = cpu_possible_mask;

	/*
	 * Setup the clock event timer to be an interval timer which
	 * is prescaled by 32 using the interval interrupt. Leave it
	 * disabled for now.
	 */
	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
	writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);

	err = request_irq(irq, ttc_clock_event_interrupt,
			  IRQF_TIMER, ttcce->ce.name, ttcce);
	if (WARN_ON(err)) {
		kfree(ttcce);
		return;
	}

	clockevents_config_and_register(&ttcce->ce,
			ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
}

/**
 * ttc_timer_init - Initialize the timer
 *
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
 */
static void __init ttc_timer_init(struct device_node *timer)
{
	unsigned int irq;
	void __iomem *timer_baseaddr;
	struct clk *clk_cs, *clk_ce;
	static int initialized;
	int clksel;
	u32 timer_width = 16;

	if (initialized)
		return;

	initialized = 1;

	/*
	 * Get the 1st Triple Timer Counter (TTC) block from the device tree
	 * and use it. Note that the event timer uses the interrupt and it's the
	 * 2nd TTC hence the irq_of_parse_and_map(,1)
	 */
	timer_baseaddr = of_iomap(timer, 0);
	if (!timer_baseaddr) {
		pr_err("ERROR: invalid timer base address\n");
		BUG();
	}

	irq = irq_of_parse_and_map(timer, 1);
	if (irq <= 0) {
		pr_err("ERROR: invalid interrupt number\n");
		BUG();
	}

	of_property_read_u32(timer, "timer-width", &timer_width);

	clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_cs = of_clk_get(timer, clksel);
	if (IS_ERR(clk_cs)) {
		pr_err("ERROR: timer input clock not found\n");
		BUG();
	}

	clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_ce = of_clk_get(timer, clksel);
	if (IS_ERR(clk_ce)) {
		pr_err("ERROR: timer input clock not found\n");
		BUG();
	}

	ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
	ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);

	pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
}

CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
Commit	Line	Data
b85a3ef4	1	/*
9e09dc5f	2	* This file contains driver for the Cadence Triple Timer Counter Rev 06
b85a3ef4	3	*
e932900a	4	* Copyright (C) 2011-2013 Xilinx
b85a3ef4 JL	5	*
	6	* based on arch/mips/kernel/time.c timer driver
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
e932900a	18	#include <linux/clk.h>
b3e90722	19	#include <linux/clk-provider.h>
b85a3ef4	20	#include <linux/interrupt.h>
b85a3ef4	21	#include <linux/clockchips.h>
91dc985c JC	22	#include <linux/of_address.h>
	23	#include <linux/of_irq.h>
	24	#include <linux/slab.h>
3d77b30e	25	#include <linux/sched_clock.h>
b85a3ef4	26
e932900a	27	/*
4e2bec0c	28	* This driver configures the 2 16/32-bit count-up timers as follows:
e932900a MS	29	*
	30	* T1: Timer 1, clocksource for generic timekeeping
	31	* T2: Timer 2, clockevent source for hrtimers
	32	* T3: Timer 3, <unused>
	33	*
	34	* The input frequency to the timer module for emulation is 2.5MHz which is
	35	* common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
	36	* the timers are clocked at 78.125KHz (12.8 us resolution).
	37
	38	* The input frequency to the timer module in silicon is configurable and
	39	* obtained from device tree. The pre-scaler of 32 is used.
	40	*/
	41
b85a3ef4 JL	42	/*
	43	* Timer Register Offset Definitions of Timer 1, Increment base address by 4
	44	* and use same offsets for Timer 2
	45	*/
9e09dc5f MS	46	#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
	47	#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
	48	#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
	49	#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
	50	#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
	51	#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
f184c5ca	52
9e09dc5f	53	#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
b85a3ef4	54
30e1e285	55	#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
b3e90722 SB	56	#define TTC_CLK_CNTRL_PSV_MASK 0x1e
b3e90722 SB	57	#define TTC_CLK_CNTRL_PSV_SHIFT 1
30e1e285	58
03377e58 SB	59	/*
03377e58 SB	60	* Setup the timers to use pre-scaling, using a fixed value for now that will
91dc985c JC	61	* work across most input frequency, but it may need to be more dynamic
	62	*/
	63	#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
	64	#define PRESCALE 2048 /* The exponent must match this */
	65	#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
	66	#define CLK_CNTRL_PRESCALE_EN 1
e932900a	67	#define CNT_CNTRL_RESET (1 << 4)
b85a3ef4	68
b3e90722 SB	69	#define MAX_F_ERR 50
b3e90722 SB	70
b85a3ef4	71	/**
9e09dc5f	72	* struct ttc_timer - This definition defines local timer structure
b85a3ef4 JL	73	*
b85a3ef4 JL	74	* @base_addr: Base address of timer
c1dcc927	75	* @freq: Timer input clock frequency
e932900a MS	76	* @clk: Associated clock source
	77	* @clk_rate_change_nb Notifier block for clock rate changes
	78	*/
9e09dc5f	79	struct ttc_timer {
e932900a	80	void __iomem *base_addr;
c1dcc927	81	unsigned long freq;
e932900a MS	82	struct clk *clk;
e932900a MS	83	struct notifier_block clk_rate_change_nb;
91dc985c JC	84	};
91dc985c JC	85
9e09dc5f MS	86	#define to_ttc_timer(x) \
9e09dc5f MS	87	container_of(x, struct ttc_timer, clk_rate_change_nb)
e932900a	88
9e09dc5f	89	struct ttc_timer_clocksource {
b3e90722 SB	90	u32 scale_clk_ctrl_reg_old;
b3e90722 SB	91	u32 scale_clk_ctrl_reg_new;
9e09dc5f	92	struct ttc_timer ttc;
91dc985c	93	struct clocksource cs;
b85a3ef4 JL	94	};
b85a3ef4 JL	95
9e09dc5f MS	96	#define to_ttc_timer_clksrc(x) \
9e09dc5f MS	97	container_of(x, struct ttc_timer_clocksource, cs)
91dc985c	98
9e09dc5f MS	99	struct ttc_timer_clockevent {
9e09dc5f MS	100	struct ttc_timer ttc;
91dc985c	101	struct clock_event_device ce;
91dc985c JC	102	};
91dc985c JC	103
9e09dc5f MS	104	#define to_ttc_timer_clkevent(x) \
9e09dc5f MS	105	container_of(x, struct ttc_timer_clockevent, ce)
b85a3ef4	106
3d77b30e SB	107	static void __iomem *ttc_sched_clock_val_reg;
3d77b30e SB	108
b85a3ef4	109	/**
9e09dc5f	110	* ttc_set_interval - Set the timer interval value
b85a3ef4 JL	111	*
	112	* @timer: Pointer to the timer instance
	113	* @cycles: Timer interval ticks
	114	**/
9e09dc5f	115	static void ttc_set_interval(struct ttc_timer *timer,
b85a3ef4 JL	116	unsigned long cycles)
	117	{
	118	u32 ctrl_reg;
	119
	120	/* Disable the counter, set the counter value and re-enable counter */
87ab4361	121	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
9e09dc5f	122	ctrl_reg \|= TTC_CNT_CNTRL_DISABLE_MASK;
87ab4361	123	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4	124
87ab4361	125	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
b85a3ef4	126
03377e58 SB	127	/*
	128	* Reset the counter (0x10) so that it starts from 0, one-shot
	129	* mode makes this needed for timing to be right.
	130	*/
91dc985c	131	ctrl_reg \|= CNT_CNTRL_RESET;
9e09dc5f	132	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
87ab4361	133	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	134	}
	135
	136	/**
9e09dc5f	137	* ttc_clock_event_interrupt - Clock event timer interrupt handler
b85a3ef4 JL	138	*
b85a3ef4 JL	139	* @irq: IRQ number of the Timer
9e09dc5f	140	* @dev_id: void pointer to the ttc_timer instance
b85a3ef4 JL	141	*
	142	* returns: Always IRQ_HANDLED - success
	143	**/
9e09dc5f	144	static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
b85a3ef4	145	{
9e09dc5f MS	146	struct ttc_timer_clockevent *ttce = dev_id;
9e09dc5f MS	147	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4 JL	148
b85a3ef4 JL	149	/* Acknowledge the interrupt and call event handler */
87ab4361	150	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
b85a3ef4	151
9e09dc5f	152	ttce->ce.event_handler(&ttce->ce);
b85a3ef4 JL	153
	154	return IRQ_HANDLED;
	155	}
	156
b85a3ef4	157	/**
9e09dc5f	158	* __ttc_clocksource_read - Reads the timer counter register
b85a3ef4 JL	159	*
	160	* returns: Current timer counter register value
	161	**/
9e09dc5f	162	static cycle_t __ttc_clocksource_read(struct clocksource *cs)
b85a3ef4	163	{
9e09dc5f	164	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
b85a3ef4	165
87ab4361	166	return (cycle_t)readl_relaxed(timer->base_addr +
9e09dc5f	167	TTC_COUNT_VAL_OFFSET);
b85a3ef4 JL	168	}
b85a3ef4 JL	169
dfded009	170	static u64 notrace ttc_sched_clock_read(void)
3d77b30e	171	{
87ab4361	172	return readl_relaxed(ttc_sched_clock_val_reg);
3d77b30e SB	173	}
3d77b30e SB	174
b85a3ef4	175	/**
9e09dc5f	176	* ttc_set_next_event - Sets the time interval for next event
b85a3ef4 JL	177	*
	178	* @cycles: Timer interval ticks
	179	* @evt: Address of clock event instance
	180	*
	181	* returns: Always 0 - success
	182	**/
9e09dc5f	183	static int ttc_set_next_event(unsigned long cycles,
b85a3ef4 JL	184	struct clock_event_device *evt)
b85a3ef4 JL	185	{
9e09dc5f MS	186	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
9e09dc5f MS	187	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4	188
9e09dc5f	189	ttc_set_interval(timer, cycles);
b85a3ef4 JL	190	return 0;
	191	}
	192
	193	/**
9e09dc5f	194	* ttc_set_mode - Sets the mode of timer
b85a3ef4 JL	195	*
	196	* @mode: Mode to be set
	197	* @evt: Address of clock event instance
	198	**/
9e09dc5f	199	static void ttc_set_mode(enum clock_event_mode mode,
b85a3ef4 JL	200	struct clock_event_device *evt)
b85a3ef4 JL	201	{
9e09dc5f MS	202	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
9e09dc5f MS	203	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4 JL	204	u32 ctrl_reg;
	205
	206	switch (mode) {
	207	case CLOCK_EVT_MODE_PERIODIC:
c1dcc927 SB	208	ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq,
c1dcc927 SB	209	PRESCALE * HZ));
b85a3ef4 JL	210	break;
	211	case CLOCK_EVT_MODE_ONESHOT:
	212	case CLOCK_EVT_MODE_UNUSED:
	213	case CLOCK_EVT_MODE_SHUTDOWN:
87ab4361	214	ctrl_reg = readl_relaxed(timer->base_addr +
9e09dc5f MS	215	TTC_CNT_CNTRL_OFFSET);
9e09dc5f MS	216	ctrl_reg \|= TTC_CNT_CNTRL_DISABLE_MASK;
87ab4361	217	writel_relaxed(ctrl_reg,
9e09dc5f	218	timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	219	break;
b85a3ef4 JL	220	case CLOCK_EVT_MODE_RESUME:
87ab4361	221	ctrl_reg = readl_relaxed(timer->base_addr +
9e09dc5f MS	222	TTC_CNT_CNTRL_OFFSET);
9e09dc5f MS	223	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
87ab4361	224	writel_relaxed(ctrl_reg,
9e09dc5f	225	timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	226	break;
	227	}
	228	}
	229
9e09dc5f	230	static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
e932900a MS	231	unsigned long event, void *data)
	232	{
	233	struct clk_notifier_data *ndata = data;
9e09dc5f MS	234	struct ttc_timer *ttc = to_ttc_timer(nb);
	235	struct ttc_timer_clocksource *ttccs = container_of(ttc,
	236	struct ttc_timer_clocksource, ttc);
e932900a MS	237
e932900a MS	238	switch (event) {
b3e90722 SB	239	case PRE_RATE_CHANGE:
	240	{
	241	u32 psv;
	242	unsigned long factor, rate_low, rate_high;
	243
	244	if (ndata->new_rate > ndata->old_rate) {
	245	factor = DIV_ROUND_CLOSEST(ndata->new_rate,
	246	ndata->old_rate);
	247	rate_low = ndata->old_rate;
	248	rate_high = ndata->new_rate;
	249	} else {
	250	factor = DIV_ROUND_CLOSEST(ndata->old_rate,
	251	ndata->new_rate);
	252	rate_low = ndata->new_rate;
	253	rate_high = ndata->old_rate;
	254	}
	255
	256	if (!is_power_of_2(factor))
	257	return NOTIFY_BAD;
	258
	259	if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
	260	return NOTIFY_BAD;
	261
	262	factor = __ilog2_u32(factor);
	263
e932900a	264	/*
b3e90722 SB	265	* store timer clock ctrl register so we can restore it in case
b3e90722 SB	266	* of an abort.
e932900a	267	*/
b3e90722	268	ttccs->scale_clk_ctrl_reg_old =
87ab4361 MS	269	readl_relaxed(ttccs->ttc.base_addr +
87ab4361 MS	270	TTC_CLK_CNTRL_OFFSET);
b3e90722 SB	271
	272	psv = (ttccs->scale_clk_ctrl_reg_old &
	273	TTC_CLK_CNTRL_PSV_MASK) >>
	274	TTC_CLK_CNTRL_PSV_SHIFT;
	275	if (ndata->new_rate < ndata->old_rate)
	276	psv -= factor;
	277	else
	278	psv += factor;
	279
	280	/* prescaler within legal range? */
	281	if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
	282	return NOTIFY_BAD;
	283
	284	ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
	285	~TTC_CLK_CNTRL_PSV_MASK;
	286	ttccs->scale_clk_ctrl_reg_new \|= psv << TTC_CLK_CNTRL_PSV_SHIFT;
	287
	288
	289	/* scale down: adjust divider in post-change notification */
	290	if (ndata->new_rate < ndata->old_rate)
	291	return NOTIFY_DONE;
	292
	293	/* scale up: adjust divider now - before frequency change */
87ab4361 MS	294	writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
87ab4361 MS	295	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
b3e90722 SB	296	break;
	297	}
	298	case POST_RATE_CHANGE:
	299	/* scale up: pre-change notification did the adjustment */
	300	if (ndata->new_rate > ndata->old_rate)
	301	return NOTIFY_OK;
	302
	303	/* scale down: adjust divider now - after frequency change */
87ab4361 MS	304	writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
87ab4361 MS	305	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
b3e90722 SB	306	break;
b3e90722 SB	307
e932900a	308	case ABORT_RATE_CHANGE:
b3e90722 SB	309	/* we have to undo the adjustment in case we scale up */
	310	if (ndata->new_rate < ndata->old_rate)
	311	return NOTIFY_OK;
	312
	313	/* restore original register value */
87ab4361 MS	314	writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
87ab4361 MS	315	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
b3e90722	316	/* fall through */
e932900a MS	317	default:
	318	return NOTIFY_DONE;
	319	}
b3e90722 SB	320
b3e90722 SB	321	return NOTIFY_DONE;
e932900a MS	322	}
e932900a MS	323
4e2bec0c MS	324	static void __init ttc_setup_clocksource(struct clk clk, void __iomem base,
4e2bec0c MS	325	u32 timer_width)
91dc985c	326	{
9e09dc5f	327	struct ttc_timer_clocksource *ttccs;
91dc985c	328	int err;
91dc985c JC	329
	330	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	331	if (WARN_ON(!ttccs))
	332	return;
	333
9e09dc5f	334	ttccs->ttc.clk = clk;
91dc985c	335
9e09dc5f	336	err = clk_prepare_enable(ttccs->ttc.clk);
c5263bb8 MS	337	if (WARN_ON(err)) {
c5263bb8 MS	338	kfree(ttccs);
91dc985c	339	return;
c5263bb8	340	}
91dc985c	341
c1dcc927 SB	342	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
c1dcc927 SB	343
9e09dc5f MS	344	ttccs->ttc.clk_rate_change_nb.notifier_call =
	345	ttc_rate_change_clocksource_cb;
	346	ttccs->ttc.clk_rate_change_nb.next = NULL;
	347	if (clk_notifier_register(ttccs->ttc.clk,
	348	&ttccs->ttc.clk_rate_change_nb))
e932900a	349	pr_warn("Unable to register clock notifier.\n");
91dc985c	350
9e09dc5f MS	351	ttccs->ttc.base_addr = base;
9e09dc5f MS	352	ttccs->cs.name = "ttc_clocksource";
91dc985c	353	ttccs->cs.rating = 200;
9e09dc5f	354	ttccs->cs.read = __ttc_clocksource_read;
4e2bec0c	355	ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
91dc985c JC	356	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
91dc985c JC	357
e932900a MS	358	/*
	359	* Setup the clock source counter to be an incrementing counter
	360	* with no interrupt and it rolls over at 0xFFFF. Pre-scale
	361	* it by 32 also. Let it start running now.
	362	*/
87ab4361 MS	363	writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
87ab4361 MS	364	writel_relaxed(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
9e09dc5f	365	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
87ab4361	366	writel_relaxed(CNT_CNTRL_RESET,
9e09dc5f	367	ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
91dc985c	368
c1dcc927	369	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
c5263bb8 MS	370	if (WARN_ON(err)) {
c5263bb8 MS	371	kfree(ttccs);
91dc985c	372	return;
c5263bb8	373	}
3d77b30e SB	374
3d77b30e SB	375	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
4e2bec0c MS	376	sched_clock_register(ttc_sched_clock_read, timer_width,
4e2bec0c MS	377	ttccs->ttc.freq / PRESCALE);
91dc985c JC	378	}
91dc985c JC	379
9e09dc5f	380	static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
e932900a MS	381	unsigned long event, void *data)
	382	{
	383	struct clk_notifier_data *ndata = data;
9e09dc5f MS	384	struct ttc_timer *ttc = to_ttc_timer(nb);
	385	struct ttc_timer_clockevent *ttcce = container_of(ttc,
	386	struct ttc_timer_clockevent, ttc);
e932900a MS	387
	388	switch (event) {
	389	case POST_RATE_CHANGE:
c1dcc927 SB	390	/* update cached frequency */
	391	ttc->freq = ndata->new_rate;
	392
5f0ba3b4 SB	393	clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
5f0ba3b4 SB	394
e932900a	395	/* fall through */
e932900a MS	396	case PRE_RATE_CHANGE:
	397	case ABORT_RATE_CHANGE:
	398	default:
	399	return NOTIFY_DONE;
	400	}
	401	}
	402
9e09dc5f	403	static void __init ttc_setup_clockevent(struct clk *clk,
e932900a	404	void __iomem *base, u32 irq)
91dc985c	405	{
9e09dc5f	406	struct ttc_timer_clockevent *ttcce;
e932900a	407	int err;
91dc985c JC	408
	409	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	410	if (WARN_ON(!ttcce))
	411	return;
	412
9e09dc5f	413	ttcce->ttc.clk = clk;
91dc985c	414
9e09dc5f	415	err = clk_prepare_enable(ttcce->ttc.clk);
c5263bb8 MS	416	if (WARN_ON(err)) {
c5263bb8 MS	417	kfree(ttcce);
91dc985c	418	return;
c5263bb8	419	}
91dc985c	420
9e09dc5f MS	421	ttcce->ttc.clk_rate_change_nb.notifier_call =
	422	ttc_rate_change_clockevent_cb;
	423	ttcce->ttc.clk_rate_change_nb.next = NULL;
	424	if (clk_notifier_register(ttcce->ttc.clk,
	425	&ttcce->ttc.clk_rate_change_nb))
e932900a	426	pr_warn("Unable to register clock notifier.\n");
c1dcc927	427	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
91dc985c	428
9e09dc5f MS	429	ttcce->ttc.base_addr = base;
9e09dc5f MS	430	ttcce->ce.name = "ttc_clockevent";
91dc985c	431	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
9e09dc5f MS	432	ttcce->ce.set_next_event = ttc_set_next_event;
9e09dc5f MS	433	ttcce->ce.set_mode = ttc_set_mode;
91dc985c JC	434	ttcce->ce.rating = 200;
91dc985c JC	435	ttcce->ce.irq = irq;
87e4ee75	436	ttcce->ce.cpumask = cpu_possible_mask;
91dc985c	437
e932900a MS	438	/*
	439	* Setup the clock event timer to be an interval timer which
	440	* is prescaled by 32 using the interval interrupt. Leave it
	441	* disabled for now.
	442	*/
87ab4361 MS	443	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
87ab4361 MS	444	writel_relaxed(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
9e09dc5f	445	ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
87ab4361	446	writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
91dc985c	447
9e09dc5f	448	err = request_irq(irq, ttc_clock_event_interrupt,
38c30a84	449	IRQF_TIMER, ttcce->ce.name, ttcce);
c5263bb8 MS	450	if (WARN_ON(err)) {
c5263bb8 MS	451	kfree(ttcce);
91dc985c	452	return;
c5263bb8	453	}
91dc985c JC	454
91dc985c JC	455	clockevents_config_and_register(&ttcce->ce,
c1dcc927	456	ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
91dc985c JC	457	}
91dc985c JC	458
b85a3ef4	459	/**
9e09dc5f	460	* ttc_timer_init - Initialize the timer
b85a3ef4 JL	461	*
	462	* Initializes the timer hardware and register the clock source and clock event
	463	* timers with Linux kernal timer framework
e932900a	464	*/
9e09dc5f	465	static void __init ttc_timer_init(struct device_node *timer)
e932900a MS	466	{
	467	unsigned int irq;
	468	void __iomem *timer_baseaddr;
30e1e285	469	struct clk clk_cs, clk_ce;
c5263bb8	470	static int initialized;
30e1e285	471	int clksel;
4e2bec0c	472	u32 timer_width = 16;
c5263bb8 MS	473
	474	if (initialized)
	475	return;
	476
	477	initialized = 1;
e932900a MS	478
	479	/*
	480	* Get the 1st Triple Timer Counter (TTC) block from the device tree
	481	* and use it. Note that the event timer uses the interrupt and it's the
	482	* 2nd TTC hence the irq_of_parse_and_map(,1)
	483	*/
	484	timer_baseaddr = of_iomap(timer, 0);
	485	if (!timer_baseaddr) {
	486	pr_err("ERROR: invalid timer base address\n");
	487	BUG();
	488	}
	489
	490	irq = irq_of_parse_and_map(timer, 1);
	491	if (irq <= 0) {
	492	pr_err("ERROR: invalid interrupt number\n");
	493	BUG();
	494	}
	495
4e2bec0c MS	496	of_property_read_u32(timer, "timer-width", &timer_width);
4e2bec0c MS	497
87ab4361	498	clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
30e1e285 SB	499	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	500	clk_cs = of_clk_get(timer, clksel);
	501	if (IS_ERR(clk_cs)) {
	502	pr_err("ERROR: timer input clock not found\n");
	503	BUG();
	504	}
	505
87ab4361	506	clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
30e1e285 SB	507	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	508	clk_ce = of_clk_get(timer, clksel);
	509	if (IS_ERR(clk_ce)) {
e932900a MS	510	pr_err("ERROR: timer input clock not found\n");
	511	BUG();
	512	}
	513
4e2bec0c	514	ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
30e1e285	515	ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
e932900a MS	516
	517	pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
	518	}
	519
9e09dc5f	520	CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);