Commit | Line | Data |
---|---|---|
b85a3ef4 | 1 | /* |
9e09dc5f | 2 | * This file contains driver for the Cadence Triple Timer Counter Rev 06 |
b85a3ef4 | 3 | * |
e932900a | 4 | * Copyright (C) 2011-2013 Xilinx |
b85a3ef4 JL |
5 | * |
6 | * based on arch/mips/kernel/time.c timer driver | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
e932900a | 18 | #include <linux/clk.h> |
b85a3ef4 | 19 | #include <linux/interrupt.h> |
b85a3ef4 | 20 | #include <linux/clockchips.h> |
91dc985c JC |
21 | #include <linux/of_address.h> |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/slab.h> | |
3d77b30e | 24 | #include <linux/sched_clock.h> |
b85a3ef4 | 25 | |
e932900a | 26 | /* |
4e2bec0c | 27 | * This driver configures the 2 16/32-bit count-up timers as follows: |
e932900a MS |
28 | * |
29 | * T1: Timer 1, clocksource for generic timekeeping | |
30 | * T2: Timer 2, clockevent source for hrtimers | |
31 | * T3: Timer 3, <unused> | |
32 | * | |
33 | * The input frequency to the timer module for emulation is 2.5MHz which is | |
34 | * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, | |
35 | * the timers are clocked at 78.125KHz (12.8 us resolution). | |
36 | ||
37 | * The input frequency to the timer module in silicon is configurable and | |
38 | * obtained from device tree. The pre-scaler of 32 is used. | |
39 | */ | |
40 | ||
b85a3ef4 JL |
41 | /* |
42 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 | |
43 | * and use same offsets for Timer 2 | |
44 | */ | |
9e09dc5f MS |
45 | #define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ |
46 | #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ | |
47 | #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ | |
48 | #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ | |
49 | #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ | |
50 | #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ | |
f184c5ca | 51 | |
9e09dc5f | 52 | #define TTC_CNT_CNTRL_DISABLE_MASK 0x1 |
b85a3ef4 | 53 | |
30e1e285 | 54 | #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */ |
b3e90722 SB |
55 | #define TTC_CLK_CNTRL_PSV_MASK 0x1e |
56 | #define TTC_CLK_CNTRL_PSV_SHIFT 1 | |
30e1e285 | 57 | |
03377e58 SB |
58 | /* |
59 | * Setup the timers to use pre-scaling, using a fixed value for now that will | |
91dc985c JC |
60 | * work across most input frequency, but it may need to be more dynamic |
61 | */ | |
62 | #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ | |
63 | #define PRESCALE 2048 /* The exponent must match this */ | |
64 | #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) | |
65 | #define CLK_CNTRL_PRESCALE_EN 1 | |
e932900a | 66 | #define CNT_CNTRL_RESET (1 << 4) |
b85a3ef4 | 67 | |
b3e90722 SB |
68 | #define MAX_F_ERR 50 |
69 | ||
b85a3ef4 | 70 | /** |
9e09dc5f | 71 | * struct ttc_timer - This definition defines local timer structure |
b85a3ef4 JL |
72 | * |
73 | * @base_addr: Base address of timer | |
c1dcc927 | 74 | * @freq: Timer input clock frequency |
e932900a MS |
75 | * @clk: Associated clock source |
76 | * @clk_rate_change_nb Notifier block for clock rate changes | |
77 | */ | |
9e09dc5f | 78 | struct ttc_timer { |
e932900a | 79 | void __iomem *base_addr; |
c1dcc927 | 80 | unsigned long freq; |
e932900a MS |
81 | struct clk *clk; |
82 | struct notifier_block clk_rate_change_nb; | |
91dc985c JC |
83 | }; |
84 | ||
9e09dc5f MS |
85 | #define to_ttc_timer(x) \ |
86 | container_of(x, struct ttc_timer, clk_rate_change_nb) | |
e932900a | 87 | |
9e09dc5f | 88 | struct ttc_timer_clocksource { |
b3e90722 SB |
89 | u32 scale_clk_ctrl_reg_old; |
90 | u32 scale_clk_ctrl_reg_new; | |
9e09dc5f | 91 | struct ttc_timer ttc; |
91dc985c | 92 | struct clocksource cs; |
b85a3ef4 JL |
93 | }; |
94 | ||
9e09dc5f MS |
95 | #define to_ttc_timer_clksrc(x) \ |
96 | container_of(x, struct ttc_timer_clocksource, cs) | |
91dc985c | 97 | |
9e09dc5f MS |
98 | struct ttc_timer_clockevent { |
99 | struct ttc_timer ttc; | |
91dc985c | 100 | struct clock_event_device ce; |
91dc985c JC |
101 | }; |
102 | ||
9e09dc5f MS |
103 | #define to_ttc_timer_clkevent(x) \ |
104 | container_of(x, struct ttc_timer_clockevent, ce) | |
b85a3ef4 | 105 | |
3d77b30e SB |
106 | static void __iomem *ttc_sched_clock_val_reg; |
107 | ||
b85a3ef4 | 108 | /** |
9e09dc5f | 109 | * ttc_set_interval - Set the timer interval value |
b85a3ef4 JL |
110 | * |
111 | * @timer: Pointer to the timer instance | |
112 | * @cycles: Timer interval ticks | |
113 | **/ | |
9e09dc5f | 114 | static void ttc_set_interval(struct ttc_timer *timer, |
b85a3ef4 JL |
115 | unsigned long cycles) |
116 | { | |
117 | u32 ctrl_reg; | |
118 | ||
119 | /* Disable the counter, set the counter value and re-enable counter */ | |
87ab4361 | 120 | ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
9e09dc5f | 121 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; |
87ab4361 | 122 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4 | 123 | |
87ab4361 | 124 | writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); |
b85a3ef4 | 125 | |
03377e58 SB |
126 | /* |
127 | * Reset the counter (0x10) so that it starts from 0, one-shot | |
128 | * mode makes this needed for timing to be right. | |
129 | */ | |
91dc985c | 130 | ctrl_reg |= CNT_CNTRL_RESET; |
9e09dc5f | 131 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
87ab4361 | 132 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4 JL |
133 | } |
134 | ||
135 | /** | |
9e09dc5f | 136 | * ttc_clock_event_interrupt - Clock event timer interrupt handler |
b85a3ef4 JL |
137 | * |
138 | * @irq: IRQ number of the Timer | |
9e09dc5f | 139 | * @dev_id: void pointer to the ttc_timer instance |
b85a3ef4 JL |
140 | * |
141 | * returns: Always IRQ_HANDLED - success | |
142 | **/ | |
9e09dc5f | 143 | static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) |
b85a3ef4 | 144 | { |
9e09dc5f MS |
145 | struct ttc_timer_clockevent *ttce = dev_id; |
146 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 JL |
147 | |
148 | /* Acknowledge the interrupt and call event handler */ | |
87ab4361 | 149 | readl_relaxed(timer->base_addr + TTC_ISR_OFFSET); |
b85a3ef4 | 150 | |
9e09dc5f | 151 | ttce->ce.event_handler(&ttce->ce); |
b85a3ef4 JL |
152 | |
153 | return IRQ_HANDLED; | |
154 | } | |
155 | ||
b85a3ef4 | 156 | /** |
9e09dc5f | 157 | * __ttc_clocksource_read - Reads the timer counter register |
b85a3ef4 JL |
158 | * |
159 | * returns: Current timer counter register value | |
160 | **/ | |
9e09dc5f | 161 | static cycle_t __ttc_clocksource_read(struct clocksource *cs) |
b85a3ef4 | 162 | { |
9e09dc5f | 163 | struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; |
b85a3ef4 | 164 | |
87ab4361 | 165 | return (cycle_t)readl_relaxed(timer->base_addr + |
9e09dc5f | 166 | TTC_COUNT_VAL_OFFSET); |
b85a3ef4 JL |
167 | } |
168 | ||
dfded009 | 169 | static u64 notrace ttc_sched_clock_read(void) |
3d77b30e | 170 | { |
87ab4361 | 171 | return readl_relaxed(ttc_sched_clock_val_reg); |
3d77b30e SB |
172 | } |
173 | ||
b85a3ef4 | 174 | /** |
9e09dc5f | 175 | * ttc_set_next_event - Sets the time interval for next event |
b85a3ef4 JL |
176 | * |
177 | * @cycles: Timer interval ticks | |
178 | * @evt: Address of clock event instance | |
179 | * | |
180 | * returns: Always 0 - success | |
181 | **/ | |
9e09dc5f | 182 | static int ttc_set_next_event(unsigned long cycles, |
b85a3ef4 JL |
183 | struct clock_event_device *evt) |
184 | { | |
9e09dc5f MS |
185 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
186 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 | 187 | |
9e09dc5f | 188 | ttc_set_interval(timer, cycles); |
b85a3ef4 JL |
189 | return 0; |
190 | } | |
191 | ||
192 | /** | |
5c0a4bbe | 193 | * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer |
b85a3ef4 | 194 | * |
b85a3ef4 JL |
195 | * @evt: Address of clock event instance |
196 | **/ | |
5c0a4bbe | 197 | static int ttc_shutdown(struct clock_event_device *evt) |
b85a3ef4 | 198 | { |
9e09dc5f MS |
199 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
200 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 JL |
201 | u32 ctrl_reg; |
202 | ||
5c0a4bbe VK |
203 | ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
204 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; | |
205 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
206 | return 0; | |
207 | } | |
208 | ||
209 | static int ttc_set_periodic(struct clock_event_device *evt) | |
210 | { | |
211 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); | |
212 | struct ttc_timer *timer = &ttce->ttc; | |
213 | ||
214 | ttc_set_interval(timer, | |
215 | DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ)); | |
216 | return 0; | |
217 | } | |
218 | ||
219 | static int ttc_resume(struct clock_event_device *evt) | |
220 | { | |
221 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); | |
222 | struct ttc_timer *timer = &ttce->ttc; | |
223 | u32 ctrl_reg; | |
224 | ||
225 | ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
226 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; | |
227 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
228 | return 0; | |
b85a3ef4 JL |
229 | } |
230 | ||
9e09dc5f | 231 | static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, |
e932900a MS |
232 | unsigned long event, void *data) |
233 | { | |
234 | struct clk_notifier_data *ndata = data; | |
9e09dc5f MS |
235 | struct ttc_timer *ttc = to_ttc_timer(nb); |
236 | struct ttc_timer_clocksource *ttccs = container_of(ttc, | |
237 | struct ttc_timer_clocksource, ttc); | |
e932900a MS |
238 | |
239 | switch (event) { | |
b3e90722 SB |
240 | case PRE_RATE_CHANGE: |
241 | { | |
242 | u32 psv; | |
243 | unsigned long factor, rate_low, rate_high; | |
244 | ||
245 | if (ndata->new_rate > ndata->old_rate) { | |
246 | factor = DIV_ROUND_CLOSEST(ndata->new_rate, | |
247 | ndata->old_rate); | |
248 | rate_low = ndata->old_rate; | |
249 | rate_high = ndata->new_rate; | |
250 | } else { | |
251 | factor = DIV_ROUND_CLOSEST(ndata->old_rate, | |
252 | ndata->new_rate); | |
253 | rate_low = ndata->new_rate; | |
254 | rate_high = ndata->old_rate; | |
255 | } | |
256 | ||
257 | if (!is_power_of_2(factor)) | |
258 | return NOTIFY_BAD; | |
259 | ||
260 | if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR) | |
261 | return NOTIFY_BAD; | |
262 | ||
263 | factor = __ilog2_u32(factor); | |
264 | ||
e932900a | 265 | /* |
b3e90722 SB |
266 | * store timer clock ctrl register so we can restore it in case |
267 | * of an abort. | |
e932900a | 268 | */ |
b3e90722 | 269 | ttccs->scale_clk_ctrl_reg_old = |
87ab4361 MS |
270 | readl_relaxed(ttccs->ttc.base_addr + |
271 | TTC_CLK_CNTRL_OFFSET); | |
b3e90722 SB |
272 | |
273 | psv = (ttccs->scale_clk_ctrl_reg_old & | |
274 | TTC_CLK_CNTRL_PSV_MASK) >> | |
275 | TTC_CLK_CNTRL_PSV_SHIFT; | |
276 | if (ndata->new_rate < ndata->old_rate) | |
277 | psv -= factor; | |
278 | else | |
279 | psv += factor; | |
280 | ||
281 | /* prescaler within legal range? */ | |
282 | if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT)) | |
283 | return NOTIFY_BAD; | |
284 | ||
285 | ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old & | |
286 | ~TTC_CLK_CNTRL_PSV_MASK; | |
287 | ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT; | |
288 | ||
289 | ||
290 | /* scale down: adjust divider in post-change notification */ | |
291 | if (ndata->new_rate < ndata->old_rate) | |
292 | return NOTIFY_DONE; | |
293 | ||
294 | /* scale up: adjust divider now - before frequency change */ | |
87ab4361 MS |
295 | writel_relaxed(ttccs->scale_clk_ctrl_reg_new, |
296 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); | |
b3e90722 SB |
297 | break; |
298 | } | |
299 | case POST_RATE_CHANGE: | |
300 | /* scale up: pre-change notification did the adjustment */ | |
301 | if (ndata->new_rate > ndata->old_rate) | |
302 | return NOTIFY_OK; | |
303 | ||
304 | /* scale down: adjust divider now - after frequency change */ | |
87ab4361 MS |
305 | writel_relaxed(ttccs->scale_clk_ctrl_reg_new, |
306 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); | |
b3e90722 SB |
307 | break; |
308 | ||
e932900a | 309 | case ABORT_RATE_CHANGE: |
b3e90722 SB |
310 | /* we have to undo the adjustment in case we scale up */ |
311 | if (ndata->new_rate < ndata->old_rate) | |
312 | return NOTIFY_OK; | |
313 | ||
314 | /* restore original register value */ | |
87ab4361 MS |
315 | writel_relaxed(ttccs->scale_clk_ctrl_reg_old, |
316 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); | |
b3e90722 | 317 | /* fall through */ |
e932900a MS |
318 | default: |
319 | return NOTIFY_DONE; | |
320 | } | |
b3e90722 SB |
321 | |
322 | return NOTIFY_DONE; | |
e932900a MS |
323 | } |
324 | ||
4e2bec0c MS |
325 | static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base, |
326 | u32 timer_width) | |
91dc985c | 327 | { |
9e09dc5f | 328 | struct ttc_timer_clocksource *ttccs; |
91dc985c | 329 | int err; |
91dc985c JC |
330 | |
331 | ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); | |
332 | if (WARN_ON(!ttccs)) | |
333 | return; | |
334 | ||
9e09dc5f | 335 | ttccs->ttc.clk = clk; |
91dc985c | 336 | |
9e09dc5f | 337 | err = clk_prepare_enable(ttccs->ttc.clk); |
c5263bb8 MS |
338 | if (WARN_ON(err)) { |
339 | kfree(ttccs); | |
91dc985c | 340 | return; |
c5263bb8 | 341 | } |
91dc985c | 342 | |
c1dcc927 SB |
343 | ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk); |
344 | ||
9e09dc5f MS |
345 | ttccs->ttc.clk_rate_change_nb.notifier_call = |
346 | ttc_rate_change_clocksource_cb; | |
347 | ttccs->ttc.clk_rate_change_nb.next = NULL; | |
348 | if (clk_notifier_register(ttccs->ttc.clk, | |
349 | &ttccs->ttc.clk_rate_change_nb)) | |
e932900a | 350 | pr_warn("Unable to register clock notifier.\n"); |
91dc985c | 351 | |
9e09dc5f MS |
352 | ttccs->ttc.base_addr = base; |
353 | ttccs->cs.name = "ttc_clocksource"; | |
91dc985c | 354 | ttccs->cs.rating = 200; |
9e09dc5f | 355 | ttccs->cs.read = __ttc_clocksource_read; |
4e2bec0c | 356 | ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width); |
91dc985c JC |
357 | ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; |
358 | ||
e932900a MS |
359 | /* |
360 | * Setup the clock source counter to be an incrementing counter | |
361 | * with no interrupt and it rolls over at 0xFFFF. Pre-scale | |
362 | * it by 32 also. Let it start running now. | |
363 | */ | |
87ab4361 MS |
364 | writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); |
365 | writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, | |
9e09dc5f | 366 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
87ab4361 | 367 | writel_relaxed(CNT_CNTRL_RESET, |
9e09dc5f | 368 | ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
91dc985c | 369 | |
c1dcc927 | 370 | err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE); |
c5263bb8 MS |
371 | if (WARN_ON(err)) { |
372 | kfree(ttccs); | |
91dc985c | 373 | return; |
c5263bb8 | 374 | } |
3d77b30e SB |
375 | |
376 | ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; | |
4e2bec0c MS |
377 | sched_clock_register(ttc_sched_clock_read, timer_width, |
378 | ttccs->ttc.freq / PRESCALE); | |
91dc985c JC |
379 | } |
380 | ||
9e09dc5f | 381 | static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, |
e932900a MS |
382 | unsigned long event, void *data) |
383 | { | |
384 | struct clk_notifier_data *ndata = data; | |
9e09dc5f MS |
385 | struct ttc_timer *ttc = to_ttc_timer(nb); |
386 | struct ttc_timer_clockevent *ttcce = container_of(ttc, | |
387 | struct ttc_timer_clockevent, ttc); | |
e932900a MS |
388 | |
389 | switch (event) { | |
390 | case POST_RATE_CHANGE: | |
c1dcc927 SB |
391 | /* update cached frequency */ |
392 | ttc->freq = ndata->new_rate; | |
393 | ||
5f0ba3b4 SB |
394 | clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE); |
395 | ||
e932900a | 396 | /* fall through */ |
e932900a MS |
397 | case PRE_RATE_CHANGE: |
398 | case ABORT_RATE_CHANGE: | |
399 | default: | |
400 | return NOTIFY_DONE; | |
401 | } | |
402 | } | |
403 | ||
9e09dc5f | 404 | static void __init ttc_setup_clockevent(struct clk *clk, |
e932900a | 405 | void __iomem *base, u32 irq) |
91dc985c | 406 | { |
9e09dc5f | 407 | struct ttc_timer_clockevent *ttcce; |
e932900a | 408 | int err; |
91dc985c JC |
409 | |
410 | ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); | |
411 | if (WARN_ON(!ttcce)) | |
412 | return; | |
413 | ||
9e09dc5f | 414 | ttcce->ttc.clk = clk; |
91dc985c | 415 | |
9e09dc5f | 416 | err = clk_prepare_enable(ttcce->ttc.clk); |
c5263bb8 MS |
417 | if (WARN_ON(err)) { |
418 | kfree(ttcce); | |
91dc985c | 419 | return; |
c5263bb8 | 420 | } |
91dc985c | 421 | |
9e09dc5f MS |
422 | ttcce->ttc.clk_rate_change_nb.notifier_call = |
423 | ttc_rate_change_clockevent_cb; | |
424 | ttcce->ttc.clk_rate_change_nb.next = NULL; | |
425 | if (clk_notifier_register(ttcce->ttc.clk, | |
426 | &ttcce->ttc.clk_rate_change_nb)) | |
e932900a | 427 | pr_warn("Unable to register clock notifier.\n"); |
c1dcc927 | 428 | ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk); |
91dc985c | 429 | |
9e09dc5f MS |
430 | ttcce->ttc.base_addr = base; |
431 | ttcce->ce.name = "ttc_clockevent"; | |
91dc985c | 432 | ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
9e09dc5f | 433 | ttcce->ce.set_next_event = ttc_set_next_event; |
5c0a4bbe VK |
434 | ttcce->ce.set_state_shutdown = ttc_shutdown; |
435 | ttcce->ce.set_state_periodic = ttc_set_periodic; | |
436 | ttcce->ce.set_state_oneshot = ttc_shutdown; | |
437 | ttcce->ce.tick_resume = ttc_resume; | |
91dc985c JC |
438 | ttcce->ce.rating = 200; |
439 | ttcce->ce.irq = irq; | |
87e4ee75 | 440 | ttcce->ce.cpumask = cpu_possible_mask; |
91dc985c | 441 | |
e932900a MS |
442 | /* |
443 | * Setup the clock event timer to be an interval timer which | |
444 | * is prescaled by 32 using the interval interrupt. Leave it | |
445 | * disabled for now. | |
446 | */ | |
87ab4361 MS |
447 | writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
448 | writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, | |
9e09dc5f | 449 | ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
87ab4361 | 450 | writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); |
91dc985c | 451 | |
9e09dc5f | 452 | err = request_irq(irq, ttc_clock_event_interrupt, |
38c30a84 | 453 | IRQF_TIMER, ttcce->ce.name, ttcce); |
c5263bb8 MS |
454 | if (WARN_ON(err)) { |
455 | kfree(ttcce); | |
91dc985c | 456 | return; |
c5263bb8 | 457 | } |
91dc985c JC |
458 | |
459 | clockevents_config_and_register(&ttcce->ce, | |
c1dcc927 | 460 | ttcce->ttc.freq / PRESCALE, 1, 0xfffe); |
91dc985c JC |
461 | } |
462 | ||
b85a3ef4 | 463 | /** |
9e09dc5f | 464 | * ttc_timer_init - Initialize the timer |
b85a3ef4 JL |
465 | * |
466 | * Initializes the timer hardware and register the clock source and clock event | |
467 | * timers with Linux kernal timer framework | |
e932900a | 468 | */ |
9e09dc5f | 469 | static void __init ttc_timer_init(struct device_node *timer) |
e932900a MS |
470 | { |
471 | unsigned int irq; | |
472 | void __iomem *timer_baseaddr; | |
30e1e285 | 473 | struct clk *clk_cs, *clk_ce; |
c5263bb8 | 474 | static int initialized; |
30e1e285 | 475 | int clksel; |
4e2bec0c | 476 | u32 timer_width = 16; |
c5263bb8 MS |
477 | |
478 | if (initialized) | |
479 | return; | |
480 | ||
481 | initialized = 1; | |
e932900a MS |
482 | |
483 | /* | |
484 | * Get the 1st Triple Timer Counter (TTC) block from the device tree | |
485 | * and use it. Note that the event timer uses the interrupt and it's the | |
486 | * 2nd TTC hence the irq_of_parse_and_map(,1) | |
487 | */ | |
488 | timer_baseaddr = of_iomap(timer, 0); | |
489 | if (!timer_baseaddr) { | |
490 | pr_err("ERROR: invalid timer base address\n"); | |
491 | BUG(); | |
492 | } | |
493 | ||
494 | irq = irq_of_parse_and_map(timer, 1); | |
495 | if (irq <= 0) { | |
496 | pr_err("ERROR: invalid interrupt number\n"); | |
497 | BUG(); | |
498 | } | |
499 | ||
4e2bec0c MS |
500 | of_property_read_u32(timer, "timer-width", &timer_width); |
501 | ||
87ab4361 | 502 | clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); |
30e1e285 SB |
503 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); |
504 | clk_cs = of_clk_get(timer, clksel); | |
505 | if (IS_ERR(clk_cs)) { | |
506 | pr_err("ERROR: timer input clock not found\n"); | |
507 | BUG(); | |
508 | } | |
509 | ||
87ab4361 | 510 | clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); |
30e1e285 SB |
511 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); |
512 | clk_ce = of_clk_get(timer, clksel); | |
513 | if (IS_ERR(clk_ce)) { | |
e932900a MS |
514 | pr_err("ERROR: timer input clock not found\n"); |
515 | BUG(); | |
516 | } | |
517 | ||
4e2bec0c | 518 | ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width); |
30e1e285 | 519 | ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); |
e932900a MS |
520 | |
521 | pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); | |
522 | } | |
523 | ||
9e09dc5f | 524 | CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); |