[deliverable/linux.git] / drivers / clocksource / dw_apb_timer.c

/*
 * (C) Copyright 2009 Intel Corporation
 * Author: Jacob Pan (jacob.jun.pan@intel.com)
 *
 * Shared with ARM platforms, Jamie Iles, Picochip 2011
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Support for the Synopsys DesignWare APB Timers.
 */
#include <linux/dw_apb_timer.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/slab.h>

#define APBT_MIN_PERIOD			4
#define APBT_MIN_DELTA_USEC		200

#define APBTMR_N_LOAD_COUNT		0x00
#define APBTMR_N_CURRENT_VALUE		0x04
#define APBTMR_N_CONTROL		0x08
#define APBTMR_N_EOI			0x0c
#define APBTMR_N_INT_STATUS		0x10

#define APBTMRS_INT_STATUS		0xa0
#define APBTMRS_EOI			0xa4
#define APBTMRS_RAW_INT_STATUS		0xa8
#define APBTMRS_COMP_VERSION		0xac

#define APBTMR_CONTROL_ENABLE		(1 << 0)
/* 1: periodic, 0:free running. */
#define APBTMR_CONTROL_MODE_PERIODIC	(1 << 1)
#define APBTMR_CONTROL_INT		(1 << 2)

static inline struct dw_apb_clock_event_device *
ced_to_dw_apb_ced(struct clock_event_device *evt)
{
	return container_of(evt, struct dw_apb_clock_event_device, ced);
}

static inline struct dw_apb_clocksource *
clocksource_to_dw_apb_clocksource(struct clocksource *cs)
{
	return container_of(cs, struct dw_apb_clocksource, cs);
}

static unsigned long apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
{
	return readl(timer->base + offs);
}

static void apbt_writel(struct dw_apb_timer *timer, unsigned long val,
		 unsigned long offs)
{
	writel(val, timer->base + offs);
}

static void apbt_disable_int(struct dw_apb_timer *timer)
{
	unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);

	ctrl |= APBTMR_CONTROL_INT;
	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
}

/**
 * dw_apb_clockevent_pause() - stop the clock_event_device from running
 *
 * @dw_ced:	The APB clock to stop generating events.
 */
void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
{
	disable_irq(dw_ced->timer.irq);
	apbt_disable_int(&dw_ced->timer);
}

static void apbt_eoi(struct dw_apb_timer *timer)
{
	apbt_readl(timer, APBTMR_N_EOI);
}

static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
{
	struct clock_event_device *evt = data;
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);

	if (!evt->event_handler) {
		pr_info("Spurious APBT timer interrupt %d", irq);
		return IRQ_NONE;
	}

	if (dw_ced->eoi)
		dw_ced->eoi(&dw_ced->timer);

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static void apbt_enable_int(struct dw_apb_timer *timer)
{
	unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
	/* clear pending intr */
	apbt_readl(timer, APBTMR_N_EOI);
	ctrl &= ~APBTMR_CONTROL_INT;
	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
}

static int apbt_shutdown(struct clock_event_device *evt)
{
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	unsigned long ctrl;

	pr_debug("%s CPU %d state=shutdown\n", __func__,
		 cpumask_first(evt->cpumask));

	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	ctrl &= ~APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	return 0;
}

static int apbt_set_oneshot(struct clock_event_device *evt)
{
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	unsigned long ctrl;

	pr_debug("%s CPU %d state=oneshot\n", __func__,
		 cpumask_first(evt->cpumask));

	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	/*
	 * set free running mode, this mode will let timer reload max
	 * timeout which will give time (3min on 25MHz clock) to rearm
	 * the next event, therefore emulate the one-shot mode.
	 */
	ctrl &= ~APBTMR_CONTROL_ENABLE;
	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;

	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	/* write again to set free running mode */
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);

	/*
	 * DW APB p. 46, load counter with all 1s before starting free
	 * running mode.
	 */
	apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
	ctrl &= ~APBTMR_CONTROL_INT;
	ctrl |= APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	return 0;
}

static int apbt_set_periodic(struct clock_event_device *evt)
{
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
	unsigned long ctrl;

	pr_debug("%s CPU %d state=periodic\n", __func__,
		 cpumask_first(evt->cpumask));

	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	/*
	 * DW APB p. 46, have to disable timer before load counter,
	 * may cause sync problem.
	 */
	ctrl &= ~APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	udelay(1);
	pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
	apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
	ctrl |= APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	return 0;
}

static int apbt_resume(struct clock_event_device *evt)
{
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);

	pr_debug("%s CPU %d state=resume\n", __func__,
		 cpumask_first(evt->cpumask));

	apbt_enable_int(&dw_ced->timer);
	return 0;
}

static int apbt_next_event(unsigned long delta,
			   struct clock_event_device *evt)
{
	unsigned long ctrl;
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);

	/* Disable timer */
	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	ctrl &= ~APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	/* write new count */
	apbt_writel(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
	ctrl |= APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);

	return 0;
}

/**
 * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
 *
 * @cpu:	The CPU the events will be targeted at.
 * @name:	The name used for the timer and the IRQ for it.
 * @rating:	The rating to give the timer.
 * @base:	I/O base for the timer registers.
 * @irq:	The interrupt number to use for the timer.
 * @freq:	The frequency that the timer counts at.
 *
 * This creates a clock_event_device for using with the generic clock layer
 * but does not start and register it.  This should be done with
 * dw_apb_clockevent_register() as the next step.  If this is the first time
 * it has been called for a timer then the IRQ will be requested, if not it
 * just be enabled to allow CPU hotplug to avoid repeatedly requesting and
 * releasing the IRQ.
 */
struct dw_apb_clock_event_device *
dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
		       void __iomem *base, int irq, unsigned long freq)
{
	struct dw_apb_clock_event_device *dw_ced =
		kzalloc(sizeof(*dw_ced), GFP_KERNEL);
	int err;

	if (!dw_ced)
		return NULL;

	dw_ced->timer.base = base;
	dw_ced->timer.irq = irq;
	dw_ced->timer.freq = freq;

	clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD);
	dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff,
						       &dw_ced->ced);
	dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
	dw_ced->ced.cpumask = cpumask_of(cpu);
	dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC |
				CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
	dw_ced->ced.set_state_shutdown = apbt_shutdown;
	dw_ced->ced.set_state_periodic = apbt_set_periodic;
	dw_ced->ced.set_state_oneshot = apbt_set_oneshot;
	dw_ced->ced.tick_resume = apbt_resume;
	dw_ced->ced.set_next_event = apbt_next_event;
	dw_ced->ced.irq = dw_ced->timer.irq;
	dw_ced->ced.rating = rating;
	dw_ced->ced.name = name;

	dw_ced->irqaction.name		= dw_ced->ced.name;
	dw_ced->irqaction.handler	= dw_apb_clockevent_irq;
	dw_ced->irqaction.dev_id	= &dw_ced->ced;
	dw_ced->irqaction.irq		= irq;
	dw_ced->irqaction.flags		= IRQF_TIMER | IRQF_IRQPOLL |
					  IRQF_NOBALANCING;

	dw_ced->eoi = apbt_eoi;
	err = setup_irq(irq, &dw_ced->irqaction);
	if (err) {
		pr_err("failed to request timer irq\n");
		kfree(dw_ced);
		dw_ced = NULL;
	}

	return dw_ced;
}

/**
 * dw_apb_clockevent_resume() - resume a clock that has been paused.
 *
 * @dw_ced:	The APB clock to resume.
 */
void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
{
	enable_irq(dw_ced->timer.irq);
}

/**
 * dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
 *
 * @dw_ced:	The APB clock to stop generating the events.
 */
void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
{
	free_irq(dw_ced->timer.irq, &dw_ced->ced);
}

/**
 * dw_apb_clockevent_register() - register the clock with the generic layer
 *
 * @dw_ced:	The APB clock to register as a clock_event_device.
 */
void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced)
{
	apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
	clockevents_register_device(&dw_ced->ced);
	apbt_enable_int(&dw_ced->timer);
}

/**
 * dw_apb_clocksource_start() - start the clocksource counting.
 *
 * @dw_cs:	The clocksource to start.
 *
 * This is used to start the clocksource before registration and can be used
 * to enable calibration of timers.
 */
void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs)
{
	/*
	 * start count down from 0xffff_ffff. this is done by toggling the
	 * enable bit then load initial load count to ~0.
	 */
	unsigned long ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);

	ctrl &= ~APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
	apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
	/* enable, mask interrupt */
	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
	ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
	/* read it once to get cached counter value initialized */
	dw_apb_clocksource_read(dw_cs);
}

static cycle_t __apbt_read_clocksource(struct clocksource *cs)
{
	unsigned long current_count;
	struct dw_apb_clocksource *dw_cs =
		clocksource_to_dw_apb_clocksource(cs);

	current_count = apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);

	return (cycle_t)~current_count;
}

static void apbt_restart_clocksource(struct clocksource *cs)
{
	struct dw_apb_clocksource *dw_cs =
		clocksource_to_dw_apb_clocksource(cs);

	dw_apb_clocksource_start(dw_cs);
}

/**
 * dw_apb_clocksource_init() - use an APB timer as a clocksource.
 *
 * @rating:	The rating to give the clocksource.
 * @name:	The name for the clocksource.
 * @base:	The I/O base for the timer registers.
 * @freq:	The frequency that the timer counts at.
 *
 * This creates a clocksource using an APB timer but does not yet register it
 * with the clocksource system.  This should be done with
 * dw_apb_clocksource_register() as the next step.
 */
struct dw_apb_clocksource *
dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
			unsigned long freq)
{
	struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL);

	if (!dw_cs)
		return NULL;

	dw_cs->timer.base = base;
	dw_cs->timer.freq = freq;
	dw_cs->cs.name = name;
	dw_cs->cs.rating = rating;
	dw_cs->cs.read = __apbt_read_clocksource;
	dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
	dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	dw_cs->cs.resume = apbt_restart_clocksource;

	return dw_cs;
}

/**
 * dw_apb_clocksource_register() - register the APB clocksource.
 *
 * @dw_cs:	The clocksource to register.
 */
void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
{
	clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
}

/**
 * dw_apb_clocksource_read() - read the current value of a clocksource.
 *
 * @dw_cs:	The clocksource to read.
 */
cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
{
	return (cycle_t)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
}
Commit	Line	Data
06c3df49 JI	1	/*
	2	* (C) Copyright 2009 Intel Corporation
	3	* Author: Jacob Pan (jacob.jun.pan@intel.com)
	4	*
	5	* Shared with ARM platforms, Jamie Iles, Picochip 2011
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Support for the Synopsys DesignWare APB Timers.
	12	*/
	13	#include <linux/dw_apb_timer.h>
	14	#include <linux/delay.h>
	15	#include <linux/kernel.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <linux/io.h>
	19	#include <linux/slab.h>
	20
	21	#define APBT_MIN_PERIOD 4
	22	#define APBT_MIN_DELTA_USEC 200
	23
d3d8fee4 JS	24	#define APBTMR_N_LOAD_COUNT 0x00
	25	#define APBTMR_N_CURRENT_VALUE 0x04
	26	#define APBTMR_N_CONTROL 0x08
	27	#define APBTMR_N_EOI 0x0c
	28	#define APBTMR_N_INT_STATUS 0x10
	29
06c3df49 JI	30	#define APBTMRS_INT_STATUS 0xa0
	31	#define APBTMRS_EOI 0xa4
	32	#define APBTMRS_RAW_INT_STATUS 0xa8
	33	#define APBTMRS_COMP_VERSION 0xac
	34
	35	#define APBTMR_CONTROL_ENABLE (1 << 0)
	36	/* 1: periodic, 0:free running. */
	37	#define APBTMR_CONTROL_MODE_PERIODIC (1 << 1)
	38	#define APBTMR_CONTROL_INT (1 << 2)
	39
	40	static inline struct dw_apb_clock_event_device *
	41	ced_to_dw_apb_ced(struct clock_event_device *evt)
	42	{
	43	return container_of(evt, struct dw_apb_clock_event_device, ced);
	44	}
	45
	46	static inline struct dw_apb_clocksource *
	47	clocksource_to_dw_apb_clocksource(struct clocksource *cs)
	48	{
	49	return container_of(cs, struct dw_apb_clocksource, cs);
	50	}
	51
	52	static unsigned long apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
	53	{
	54	return readl(timer->base + offs);
	55	}
	56
	57	static void apbt_writel(struct dw_apb_timer *timer, unsigned long val,
	58	unsigned long offs)
	59	{
	60	writel(val, timer->base + offs);
	61	}
	62
	63	static void apbt_disable_int(struct dw_apb_timer *timer)
	64	{
	65	unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
	66
	67	ctrl \|= APBTMR_CONTROL_INT;
	68	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
	69	}
	70
	71	/**
	72	* dw_apb_clockevent_pause() - stop the clock_event_device from running
	73	*
	74	* @dw_ced: The APB clock to stop generating events.
	75	*/
	76	void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
	77	{
	78	disable_irq(dw_ced->timer.irq);
	79	apbt_disable_int(&dw_ced->timer);
	80	}
	81
	82	static void apbt_eoi(struct dw_apb_timer *timer)
	83	{
	84	apbt_readl(timer, APBTMR_N_EOI);
	85	}
	86
	87	static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
	88	{
	89	struct clock_event_device *evt = data;
	90	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	91
	92	if (!evt->event_handler) {
	93	pr_info("Spurious APBT timer interrupt %d", irq);
94	return IRQ_NONE;
95	}
96
97	if (dw_ced->eoi)
98	dw_ced->eoi(&dw_ced->timer);
99
100	evt->event_handler(evt);
101	return IRQ_HANDLED;
102	}
103
104	static void apbt_enable_int(struct dw_apb_timer *timer)
105	{
106	unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
107	/* clear pending intr */
108	apbt_readl(timer, APBTMR_N_EOI);
109	ctrl &= ~APBTMR_CONTROL_INT;
110	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
111	}
112
226be92b	113	static int apbt_shutdown(struct clock_event_device *evt)
06c3df49	114	{
226be92b	115	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
06c3df49	116	unsigned long ctrl;
226be92b VK	117
	118	pr_debug("%s CPU %d state=shutdown\n", __func__,
	119	cpumask_first(evt->cpumask));
	120
	121	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	122	ctrl &= ~APBTMR_CONTROL_ENABLE;
	123	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	124	return 0;
	125	}
	126
	127	static int apbt_set_oneshot(struct clock_event_device *evt)
	128	{
06c3df49	129	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
226be92b	130	unsigned long ctrl;
06c3df49	131
226be92b VK	132	pr_debug("%s CPU %d state=oneshot\n", __func__,
	133	cpumask_first(evt->cpumask));
	134
	135	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	136	/*
	137	* set free running mode, this mode will let timer reload max
	138	* timeout which will give time (3min on 25MHz clock) to rearm
	139	* the next event, therefore emulate the one-shot mode.
	140	*/
	141	ctrl &= ~APBTMR_CONTROL_ENABLE;
	142	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
	143
	144	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	145	/* write again to set free running mode */
	146	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	147
	148	/*
	149	* DW APB p. 46, load counter with all 1s before starting free
	150	* running mode.
	151	*/
	152	apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
	153	ctrl &= ~APBTMR_CONTROL_INT;
	154	ctrl \|= APBTMR_CONTROL_ENABLE;
	155	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	156	return 0;
	157	}
	158
	159	static int apbt_set_periodic(struct clock_event_device *evt)
	160	{
	161	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	162	unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
	163	unsigned long ctrl;
	164
	165	pr_debug("%s CPU %d state=periodic\n", __func__,
	166	cpumask_first(evt->cpumask));
	167
	168	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	169	ctrl \|= APBTMR_CONTROL_MODE_PERIODIC;
	170	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	171	/*
	172	* DW APB p. 46, have to disable timer before load counter,
	173	* may cause sync problem.
	174	*/
	175	ctrl &= ~APBTMR_CONTROL_ENABLE;
	176	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	177	udelay(1);
	178	pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
	179	apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
	180	ctrl \|= APBTMR_CONTROL_ENABLE;
	181	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	182	return 0;
	183	}
	184
	185	static int apbt_resume(struct clock_event_device *evt)
	186	{
	187	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	188
	189	pr_debug("%s CPU %d state=resume\n", __func__,
	190	cpumask_first(evt->cpumask));
	191
	192	apbt_enable_int(&dw_ced->timer);
	193	return 0;
06c3df49 JI	194	}
	195
	196	static int apbt_next_event(unsigned long delta,
	197	struct clock_event_device *evt)
	198	{
	199	unsigned long ctrl;
	200	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	201
	202	/* Disable timer */
	203	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	204	ctrl &= ~APBTMR_CONTROL_ENABLE;
	205	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	206	/* write new count */
	207	apbt_writel(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
	208	ctrl \|= APBTMR_CONTROL_ENABLE;
	209	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	210
	211	return 0;
	212	}
	213
	214	/**
	215	* dw_apb_clockevent_init() - use an APB timer as a clock_event_device
	216	*
	217	* @cpu: The CPU the events will be targeted at.
	218	* @name: The name used for the timer and the IRQ for it.
	219	* @rating: The rating to give the timer.
	220	* @base: I/O base for the timer registers.
	221	* @irq: The interrupt number to use for the timer.
	222	* @freq: The frequency that the timer counts at.
	223	*
	224	* This creates a clock_event_device for using with the generic clock layer
	225	* but does not start and register it. This should be done with
	226	* dw_apb_clockevent_register() as the next step. If this is the first time
	227	* it has been called for a timer then the IRQ will be requested, if not it
	228	* just be enabled to allow CPU hotplug to avoid repeatedly requesting and
	229	* releasing the IRQ.
	230	*/
	231	struct dw_apb_clock_event_device *
	232	dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
	233	void __iomem *base, int irq, unsigned long freq)
	234	{
	235	struct dw_apb_clock_event_device *dw_ced =
	236	kzalloc(sizeof(*dw_ced), GFP_KERNEL);
	237	int err;
	238
	239	if (!dw_ced)
	240	return NULL;
	241
	242	dw_ced->timer.base = base;
	243	dw_ced->timer.irq = irq;
	244	dw_ced->timer.freq = freq;
	245
	246	clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD);
	247	dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff,
	248	&dw_ced->ced);
	249	dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
	250	dw_ced->ced.cpumask = cpumask_of(cpu);
8b5f0010 JZ	251	dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC \|
8b5f0010 JZ	252	CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_DYNIRQ;
226be92b VK	253	dw_ced->ced.set_state_shutdown = apbt_shutdown;
	254	dw_ced->ced.set_state_periodic = apbt_set_periodic;
	255	dw_ced->ced.set_state_oneshot = apbt_set_oneshot;
	256	dw_ced->ced.tick_resume = apbt_resume;
06c3df49 JI	257	dw_ced->ced.set_next_event = apbt_next_event;
	258	dw_ced->ced.irq = dw_ced->timer.irq;
	259	dw_ced->ced.rating = rating;
	260	dw_ced->ced.name = name;
	261
	262	dw_ced->irqaction.name = dw_ced->ced.name;
	263	dw_ced->irqaction.handler = dw_apb_clockevent_irq;
	264	dw_ced->irqaction.dev_id = &dw_ced->ced;
	265	dw_ced->irqaction.irq = irq;
	266	dw_ced->irqaction.flags = IRQF_TIMER \| IRQF_IRQPOLL \|
38c30a84	267	IRQF_NOBALANCING;
06c3df49 JI	268
	269	dw_ced->eoi = apbt_eoi;
	270	err = setup_irq(irq, &dw_ced->irqaction);
	271	if (err) {
	272	pr_err("failed to request timer irq\n");
	273	kfree(dw_ced);
	274	dw_ced = NULL;
	275	}
	276
	277	return dw_ced;
	278	}
	279
	280	/**
	281	* dw_apb_clockevent_resume() - resume a clock that has been paused.
	282	*
	283	* @dw_ced: The APB clock to resume.
	284	*/
	285	void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
	286	{
	287	enable_irq(dw_ced->timer.irq);
	288	}
	289
	290	/**
	291	* dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
	292	*
	293	* @dw_ced: The APB clock to stop generating the events.
	294	*/
	295	void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
	296	{
	297	free_irq(dw_ced->timer.irq, &dw_ced->ced);
	298	}
	299
	300	/**
	301	* dw_apb_clockevent_register() - register the clock with the generic layer
	302	*
	303	* @dw_ced: The APB clock to register as a clock_event_device.
	304	*/
	305	void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced)
	306	{
	307	apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
	308	clockevents_register_device(&dw_ced->ced);
	309	apbt_enable_int(&dw_ced->timer);
	310	}
	311
	312	/**
	313	* dw_apb_clocksource_start() - start the clocksource counting.
	314	*
	315	* @dw_cs: The clocksource to start.
	316	*
	317	* This is used to start the clocksource before registration and can be used
	318	* to enable calibration of timers.
	319	*/
	320	void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs)
	321	{
	322	/*
	323	* start count down from 0xffff_ffff. this is done by toggling the
	324	* enable bit then load initial load count to ~0.
	325	*/
	326	unsigned long ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);
	327
	328	ctrl &= ~APBTMR_CONTROL_ENABLE;
	329	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
	330	apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
	331	/* enable, mask interrupt */
332	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
333	ctrl \|= (APBTMR_CONTROL_ENABLE \| APBTMR_CONTROL_INT);
334	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
335	/* read it once to get cached counter value initialized */
336	dw_apb_clocksource_read(dw_cs);
337	}
338
339	static cycle_t __apbt_read_clocksource(struct clocksource *cs)
340	{
341	unsigned long current_count;
342	struct dw_apb_clocksource *dw_cs =
343	clocksource_to_dw_apb_clocksource(cs);
344
345	current_count = apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
346
347	return (cycle_t)~current_count;
348	}
349
350	static void apbt_restart_clocksource(struct clocksource *cs)
351	{
352	struct dw_apb_clocksource *dw_cs =
353	clocksource_to_dw_apb_clocksource(cs);
354
355	dw_apb_clocksource_start(dw_cs);
356	}
357
358	/**
359	* dw_apb_clocksource_init() - use an APB timer as a clocksource.
360	*
361	* @rating: The rating to give the clocksource.
362	* @name: The name for the clocksource.
363	* @base: The I/O base for the timer registers.
364	* @freq: The frequency that the timer counts at.
365	*
366	* This creates a clocksource using an APB timer but does not yet register it
367	* with the clocksource system. This should be done with
368	* dw_apb_clocksource_register() as the next step.
369	*/
370	struct dw_apb_clocksource *
a1330228	371	dw_apb_clocksource_init(unsigned rating, const char name, void __iomem base,
06c3df49 JI	372	unsigned long freq)
	373	{
	374	struct dw_apb_clocksource dw_cs = kzalloc(sizeof(dw_cs), GFP_KERNEL);
	375
	376	if (!dw_cs)
	377	return NULL;
	378
	379	dw_cs->timer.base = base;
	380	dw_cs->timer.freq = freq;
	381	dw_cs->cs.name = name;
	382	dw_cs->cs.rating = rating;
	383	dw_cs->cs.read = __apbt_read_clocksource;
	384	dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
	385	dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	386	dw_cs->cs.resume = apbt_restart_clocksource;
	387
	388	return dw_cs;
	389	}
	390
	391	/**
	392	* dw_apb_clocksource_register() - register the APB clocksource.
	393	*
	394	* @dw_cs: The clocksource to register.
	395	*/
	396	void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
	397	{
	398	clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
	399	}
	400
	401	/**
	402	* dw_apb_clocksource_read() - read the current value of a clocksource.
	403	*
	404	* @dw_cs: The clocksource to read.
	405	*/
	406	cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
	407	{
	408	return (cycle_t)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
	409	}