[deliverable/linux.git] / drivers / clocksource / exynos_mct.c

/* linux/arch/arm/mach-exynos4/mct.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4 MCT(Multi-Core Timer) support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/clocksource.h>

#include <asm/mach/time.h>

#define EXYNOS4_MCTREG(x)		(x)
#define EXYNOS4_MCT_G_CNT_L		EXYNOS4_MCTREG(0x100)
#define EXYNOS4_MCT_G_CNT_U		EXYNOS4_MCTREG(0x104)
#define EXYNOS4_MCT_G_CNT_WSTAT		EXYNOS4_MCTREG(0x110)
#define EXYNOS4_MCT_G_COMP0_L		EXYNOS4_MCTREG(0x200)
#define EXYNOS4_MCT_G_COMP0_U		EXYNOS4_MCTREG(0x204)
#define EXYNOS4_MCT_G_COMP0_ADD_INCR	EXYNOS4_MCTREG(0x208)
#define EXYNOS4_MCT_G_TCON		EXYNOS4_MCTREG(0x240)
#define EXYNOS4_MCT_G_INT_CSTAT		EXYNOS4_MCTREG(0x244)
#define EXYNOS4_MCT_G_INT_ENB		EXYNOS4_MCTREG(0x248)
#define EXYNOS4_MCT_G_WSTAT		EXYNOS4_MCTREG(0x24C)
#define _EXYNOS4_MCT_L_BASE		EXYNOS4_MCTREG(0x300)
#define EXYNOS4_MCT_L_BASE(x)		(_EXYNOS4_MCT_L_BASE + (0x100 * x))
#define EXYNOS4_MCT_L_MASK		(0xffffff00)

#define MCT_L_TCNTB_OFFSET		(0x00)
#define MCT_L_ICNTB_OFFSET		(0x08)
#define MCT_L_TCON_OFFSET		(0x20)
#define MCT_L_INT_CSTAT_OFFSET		(0x30)
#define MCT_L_INT_ENB_OFFSET		(0x34)
#define MCT_L_WSTAT_OFFSET		(0x40)
#define MCT_G_TCON_START		(1 << 8)
#define MCT_G_TCON_COMP0_AUTO_INC	(1 << 1)
#define MCT_G_TCON_COMP0_ENABLE		(1 << 0)
#define MCT_L_TCON_INTERVAL_MODE	(1 << 2)
#define MCT_L_TCON_INT_START		(1 << 1)
#define MCT_L_TCON_TIMER_START		(1 << 0)

#define TICK_BASE_CNT	1

enum {
	MCT_INT_SPI,
	MCT_INT_PPI
};

enum {
	MCT_G0_IRQ,
	MCT_G1_IRQ,
	MCT_G2_IRQ,
	MCT_G3_IRQ,
	MCT_L0_IRQ,
	MCT_L1_IRQ,
	MCT_L2_IRQ,
	MCT_L3_IRQ,
	MCT_NR_IRQS,
};

static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
static int mct_irqs[MCT_NR_IRQS];

struct mct_clock_event_device {
	struct clock_event_device evt;
	unsigned long base;
	char name[10];
};

static void exynos4_mct_write(unsigned int value, unsigned long offset)
{
	unsigned long stat_addr;
	u32 mask;
	u32 i;

	__raw_writel(value, reg_base + offset);

	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
		stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
		switch (offset & EXYNOS4_MCT_L_MASK) {
		case MCT_L_TCON_OFFSET:
			mask = 1 << 3;		/* L_TCON write status */
			break;
		case MCT_L_ICNTB_OFFSET:
			mask = 1 << 1;		/* L_ICNTB write status */
			break;
		case MCT_L_TCNTB_OFFSET:
			mask = 1 << 0;		/* L_TCNTB write status */
			break;
		default:
			return;
		}
	} else {
		switch (offset) {
		case EXYNOS4_MCT_G_TCON:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 16;		/* G_TCON write status */
			break;
		case EXYNOS4_MCT_G_COMP0_L:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 0;		/* G_COMP0_L write status */
			break;
		case EXYNOS4_MCT_G_COMP0_U:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 1;		/* G_COMP0_U write status */
			break;
		case EXYNOS4_MCT_G_COMP0_ADD_INCR:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 2;		/* G_COMP0_ADD_INCR w status */
			break;
		case EXYNOS4_MCT_G_CNT_L:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 0;		/* G_CNT_L write status */
			break;
		case EXYNOS4_MCT_G_CNT_U:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 1;		/* G_CNT_U write status */
			break;
		default:
			return;
		}
	}

	/* Wait maximum 1 ms until written values are applied */
	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
		if (__raw_readl(reg_base + stat_addr) & mask) {
			__raw_writel(mask, reg_base + stat_addr);
			return;
		}

	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
}

/* Clocksource handling */
static void exynos4_mct_frc_start(u32 hi, u32 lo)
{
	u32 reg;

	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);

	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	reg |= MCT_G_TCON_START;
	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}

static cycle_t exynos4_frc_read(struct clocksource *cs)
{
	unsigned int lo, hi;
	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);

	do {
		hi = hi2;
		lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
		hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
	} while (hi != hi2);

	return ((cycle_t)hi << 32) | lo;
}

static void exynos4_frc_resume(struct clocksource *cs)
{
	exynos4_mct_frc_start(0, 0);
}

struct clocksource mct_frc = {
	.name		= "mct-frc",
	.rating		= 400,
	.read		= exynos4_frc_read,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= exynos4_frc_resume,
};

static void __init exynos4_clocksource_init(void)
{
	exynos4_mct_frc_start(0, 0);

	if (clocksource_register_hz(&mct_frc, clk_rate))
		panic("%s: can't register clocksource\n", mct_frc.name);
}

static void exynos4_mct_comp0_stop(void)
{
	unsigned int tcon;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);

	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
}

static void exynos4_mct_comp0_start(enum clock_event_mode mode,
				    unsigned long cycles)
{
	unsigned int tcon;
	cycle_t comp_cycle;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);

	if (mode == CLOCK_EVT_MODE_PERIODIC) {
		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	}

	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);

	tcon |= MCT_G_TCON_COMP0_ENABLE;
	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
}

static int exynos4_comp_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	exynos4_mct_comp0_start(evt->mode, cycles);

	return 0;
}

static void exynos4_comp_set_mode(enum clock_event_mode mode,
				  struct clock_event_device *evt)
{
	unsigned long cycles_per_jiffy;
	exynos4_mct_comp0_stop();

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_comp0_start(mode, cycles_per_jiffy);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device mct_comp_device = {
	.name		= "mct-comp",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 250,
	.set_next_event	= exynos4_comp_set_next_event,
	.set_mode	= exynos4_comp_set_mode,
};

static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mct_comp_event_irq = {
	.name		= "mct_comp_irq",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= exynos4_mct_comp_isr,
	.dev_id		= &mct_comp_device,
};

static void exynos4_clockevent_init(void)
{
	mct_comp_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mct_comp_device, clk_rate,
					0xf, 0xffffffff);
	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
}

static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);

/* Clock event handling */
static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
	unsigned long tmp;
	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;

	tmp = __raw_readl(reg_base + offset);
	if (tmp & mask) {
		tmp &= ~mask;
		exynos4_mct_write(tmp, offset);
	}
}

static void exynos4_mct_tick_start(unsigned long cycles,
				   struct mct_clock_event_device *mevt)
{
	unsigned long tmp;

	exynos4_mct_tick_stop(mevt);

	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */

	/* update interrupt count buffer */
	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);

	/* enable MCT tick interrupt */
	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);

	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
	       MCT_L_TCON_INTERVAL_MODE;
	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
}

static int exynos4_tick_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);

	exynos4_mct_tick_start(cycles, mevt);

	return 0;
}

static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
					 struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	unsigned long cycles_per_jiffy;

	exynos4_mct_tick_stop(mevt);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_tick_start(cycles_per_jiffy, mevt);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
	struct clock_event_device *evt = &mevt->evt;

	/*
	 * This is for supporting oneshot mode.
	 * Mct would generate interrupt periodically
	 * without explicit stopping.
	 */
	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
		exynos4_mct_tick_stop(mevt);

	/* Clear the MCT tick interrupt */
	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
		return 1;
	} else {
		return 0;
	}
}

static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
{
	struct mct_clock_event_device *mevt = dev_id;
	struct clock_event_device *evt = &mevt->evt;

	exynos4_mct_tick_clear(mevt);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static int exynos4_local_timer_setup(struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt;
	unsigned int cpu = smp_processor_id();

	mevt = container_of(evt, struct mct_clock_event_device, evt);

	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
	sprintf(mevt->name, "mct_tick%d", cpu);

	evt->name = mevt->name;
	evt->cpumask = cpumask_of(cpu);
	evt->set_next_event = exynos4_tick_set_next_event;
	evt->set_mode = exynos4_tick_set_mode;
	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 450;
	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
					0xf, 0x7fffffff);

	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);

	if (mct_int_type == MCT_INT_SPI) {
		evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
		if (request_irq(evt->irq, exynos4_mct_tick_isr,
				IRQF_TIMER | IRQF_NOBALANCING,
				evt->name, mevt)) {
			pr_err("exynos-mct: cannot register IRQ %d\n",
				evt->irq);
			return -EIO;
		}
		irq_set_affinity(evt->irq, cpumask_of(cpu));
	} else {
		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
	}

	return 0;
}

static void exynos4_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	if (mct_int_type == MCT_INT_SPI)
		free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
	else
		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}

static int exynos4_mct_cpu_notify(struct notifier_block *self,
					   unsigned long action, void *hcpu)
{
	struct mct_clock_event_device *mevt;

	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		mevt = this_cpu_ptr(&percpu_mct_tick);
		exynos4_local_timer_setup(&mevt->evt);
		break;
	case CPU_DYING:
		mevt = this_cpu_ptr(&percpu_mct_tick);
		exynos4_local_timer_stop(&mevt->evt);
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block exynos4_mct_cpu_nb = {
	.notifier_call = exynos4_mct_cpu_notify,
};

static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
{
	int err;
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	struct clk *mct_clk, *tick_clk;

	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
				clk_get(NULL, "fin_pll");
	if (IS_ERR(tick_clk))
		panic("%s: unable to determine tick clock rate\n", __func__);
	clk_rate = clk_get_rate(tick_clk);

	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	if (IS_ERR(mct_clk))
		panic("%s: unable to retrieve mct clock instance\n", __func__);
	clk_prepare_enable(mct_clk);

	reg_base = base;
	if (!reg_base)
		panic("%s: unable to ioremap mct address space\n", __func__);

	if (mct_int_type == MCT_INT_PPI) {

		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
					 exynos4_mct_tick_isr, "MCT",
					 &percpu_mct_tick);
		WARN(err, "MCT: can't request IRQ %d (%d)\n",
		     mct_irqs[MCT_L0_IRQ], err);
	}

	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
	if (err)
		goto out_irq;

	/* Immediately configure the timer on the boot CPU */
	exynos4_local_timer_setup(&mevt->evt);
	return;

out_irq:
	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
}

void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
{
	mct_irqs[MCT_G0_IRQ] = irq_g0;
	mct_irqs[MCT_L0_IRQ] = irq_l0;
	mct_irqs[MCT_L1_IRQ] = irq_l1;
	mct_int_type = MCT_INT_SPI;

	exynos4_timer_resources(NULL, base);
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}

static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
{
	u32 nr_irqs, i;

	mct_int_type = int_type;

	/* This driver uses only one global timer interrupt */
	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);

	/*
	 * Find out the number of local irqs specified. The local
	 * timer irqs are specified after the four global timer
	 * irqs are specified.
	 */
#ifdef CONFIG_OF
	nr_irqs = of_irq_count(np);
#else
	nr_irqs = 0;
#endif
	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
		mct_irqs[i] = irq_of_parse_and_map(np, i);

	exynos4_timer_resources(np, of_iomap(np, 0));
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}


static void __init mct_init_spi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_SPI);
}

static void __init mct_init_ppi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_PPI);
}
CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
Commit	Line	Data
30d8bead CY	1	/* linux/arch/arm/mach-exynos4/mct.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* EXYNOS4 MCT(Multi-Core Timer) support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
ee98d27d	19	#include <linux/cpu.h>
30d8bead CY	20	#include <linux/platform_device.h>
	21	#include <linux/delay.h>
	22	#include <linux/percpu.h>
2edb36c4	23	#include <linux/of.h>
36ba5d52 TA	24	#include <linux/of_irq.h>
36ba5d52 TA	25	#include <linux/of_address.h>
9fbf0c85	26	#include <linux/clocksource.h>
30d8bead	27
30d8bead CY	28	#include <asm/mach/time.h>
30d8bead CY	29
a1ba7a7a TA	30	#define EXYNOS4_MCTREG(x) (x)
	31	#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
	32	#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
	33	#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
	34	#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
	35	#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
	36	#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
	37	#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
	38	#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
	39	#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
	40	#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
	41	#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
	42	#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
	43	#define EXYNOS4_MCT_L_MASK (0xffffff00)
	44
	45	#define MCT_L_TCNTB_OFFSET (0x00)
	46	#define MCT_L_ICNTB_OFFSET (0x08)
	47	#define MCT_L_TCON_OFFSET (0x20)
	48	#define MCT_L_INT_CSTAT_OFFSET (0x30)
	49	#define MCT_L_INT_ENB_OFFSET (0x34)
	50	#define MCT_L_WSTAT_OFFSET (0x40)
	51	#define MCT_G_TCON_START (1 << 8)
	52	#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
	53	#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
	54	#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
	55	#define MCT_L_TCON_INT_START (1 << 1)
	56	#define MCT_L_TCON_TIMER_START (1 << 0)
	57
4d2e4d7f CY	58	#define TICK_BASE_CNT 1
4d2e4d7f CY	59
3a062281 CY	60	enum {
	61	MCT_INT_SPI,
	62	MCT_INT_PPI
	63	};
	64
c371dc60 TA	65	enum {
	66	MCT_G0_IRQ,
	67	MCT_G1_IRQ,
	68	MCT_G2_IRQ,
	69	MCT_G3_IRQ,
	70	MCT_L0_IRQ,
	71	MCT_L1_IRQ,
	72	MCT_L2_IRQ,
	73	MCT_L3_IRQ,
	74	MCT_NR_IRQS,
	75	};
	76
a1ba7a7a	77	static void __iomem *reg_base;
30d8bead	78	static unsigned long clk_rate;
3a062281	79	static unsigned int mct_int_type;
c371dc60	80	static int mct_irqs[MCT_NR_IRQS];
30d8bead CY	81
30d8bead CY	82	struct mct_clock_event_device {
ee98d27d	83	struct clock_event_device evt;
a1ba7a7a	84	unsigned long base;
c8987470	85	char name[10];
30d8bead CY	86	};
30d8bead CY	87
a1ba7a7a	88	static void exynos4_mct_write(unsigned int value, unsigned long offset)
30d8bead	89	{
a1ba7a7a	90	unsigned long stat_addr;
30d8bead CY	91	u32 mask;
	92	u32 i;
	93
a1ba7a7a	94	__raw_writel(value, reg_base + offset);
30d8bead	95
a1ba7a7a TA	96	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
	97	stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
	98	switch (offset & EXYNOS4_MCT_L_MASK) {
	99	case MCT_L_TCON_OFFSET:
c8987470 CY	100	mask = 1 << 3; /* L_TCON write status */
c8987470 CY	101	break;
a1ba7a7a	102	case MCT_L_ICNTB_OFFSET:
c8987470 CY	103	mask = 1 << 1; /* L_ICNTB write status */
c8987470 CY	104	break;
a1ba7a7a	105	case MCT_L_TCNTB_OFFSET:
c8987470 CY	106	mask = 1 << 0; /* L_TCNTB write status */
	107	break;
	108	default:
	109	return;
	110	}
	111	} else {
a1ba7a7a TA	112	switch (offset) {
a1ba7a7a TA	113	case EXYNOS4_MCT_G_TCON:
c8987470 CY	114	stat_addr = EXYNOS4_MCT_G_WSTAT;
	115	mask = 1 << 16; /* G_TCON write status */
	116	break;
a1ba7a7a	117	case EXYNOS4_MCT_G_COMP0_L:
c8987470 CY	118	stat_addr = EXYNOS4_MCT_G_WSTAT;
	119	mask = 1 << 0; /* G_COMP0_L write status */
	120	break;
a1ba7a7a	121	case EXYNOS4_MCT_G_COMP0_U:
c8987470 CY	122	stat_addr = EXYNOS4_MCT_G_WSTAT;
	123	mask = 1 << 1; /* G_COMP0_U write status */
	124	break;
a1ba7a7a	125	case EXYNOS4_MCT_G_COMP0_ADD_INCR:
c8987470 CY	126	stat_addr = EXYNOS4_MCT_G_WSTAT;
	127	mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
	128	break;
a1ba7a7a	129	case EXYNOS4_MCT_G_CNT_L:
c8987470 CY	130	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	131	mask = 1 << 0; /* G_CNT_L write status */
	132	break;
a1ba7a7a	133	case EXYNOS4_MCT_G_CNT_U:
c8987470 CY	134	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	135	mask = 1 << 1; /* G_CNT_U write status */
	136	break;
	137	default:
	138	return;
	139	}
30d8bead CY	140	}
	141
	142	/* Wait maximum 1 ms until written values are applied */
	143	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
a1ba7a7a TA	144	if (__raw_readl(reg_base + stat_addr) & mask) {
a1ba7a7a TA	145	__raw_writel(mask, reg_base + stat_addr);
30d8bead CY	146	return;
	147	}
	148
a1ba7a7a	149	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
30d8bead CY	150	}
	151
	152	/* Clocksource handling */
	153	static void exynos4_mct_frc_start(u32 hi, u32 lo)
	154	{
	155	u32 reg;
	156
	157	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	158	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
	159
a1ba7a7a	160	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	161	reg \|= MCT_G_TCON_START;
	162	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
	163	}
	164
	165	static cycle_t exynos4_frc_read(struct clocksource *cs)
	166	{
	167	unsigned int lo, hi;
a1ba7a7a	168	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	169
	170	do {
	171	hi = hi2;
a1ba7a7a TA	172	lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
a1ba7a7a TA	173	hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	174	} while (hi != hi2);
	175
	176	return ((cycle_t)hi << 32) \| lo;
	177	}
	178
aa421c13 CY	179	static void exynos4_frc_resume(struct clocksource *cs)
	180	{
	181	exynos4_mct_frc_start(0, 0);
	182	}
	183
30d8bead CY	184	struct clocksource mct_frc = {
	185	.name = "mct-frc",
	186	.rating = 400,
	187	.read = exynos4_frc_read,
	188	.mask = CLOCKSOURCE_MASK(64),
	189	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
aa421c13	190	.resume = exynos4_frc_resume,
30d8bead CY	191	};
	192
	193	static void __init exynos4_clocksource_init(void)
	194	{
	195	exynos4_mct_frc_start(0, 0);
	196
	197	if (clocksource_register_hz(&mct_frc, clk_rate))
	198	panic("%s: can't register clocksource\n", mct_frc.name);
	199	}
	200
	201	static void exynos4_mct_comp0_stop(void)
	202	{
	203	unsigned int tcon;
	204
a1ba7a7a	205	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	206	tcon &= ~(MCT_G_TCON_COMP0_ENABLE \| MCT_G_TCON_COMP0_AUTO_INC);
	207
	208	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	209	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
	210	}
	211
	212	static void exynos4_mct_comp0_start(enum clock_event_mode mode,
	213	unsigned long cycles)
	214	{
	215	unsigned int tcon;
	216	cycle_t comp_cycle;
	217
a1ba7a7a	218	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	219
	220	if (mode == CLOCK_EVT_MODE_PERIODIC) {
	221	tcon \|= MCT_G_TCON_COMP0_AUTO_INC;
	222	exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	223	}
	224
	225	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	226	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	227	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
	228
	229	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
	230
	231	tcon \|= MCT_G_TCON_COMP0_ENABLE;
	232	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
	233	}
	234
	235	static int exynos4_comp_set_next_event(unsigned long cycles,
	236	struct clock_event_device *evt)
	237	{
	238	exynos4_mct_comp0_start(evt->mode, cycles);
	239
	240	return 0;
	241	}
	242
	243	static void exynos4_comp_set_mode(enum clock_event_mode mode,
	244	struct clock_event_device *evt)
	245	{
4d2e4d7f	246	unsigned long cycles_per_jiffy;
30d8bead CY	247	exynos4_mct_comp0_stop();
	248
	249	switch (mode) {
	250	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	251	cycles_per_jiffy =
	252	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	253	exynos4_mct_comp0_start(mode, cycles_per_jiffy);
30d8bead CY	254	break;
	255
	256	case CLOCK_EVT_MODE_ONESHOT:
	257	case CLOCK_EVT_MODE_UNUSED:
	258	case CLOCK_EVT_MODE_SHUTDOWN:
	259	case CLOCK_EVT_MODE_RESUME:
	260	break;
	261	}
	262	}
	263
	264	static struct clock_event_device mct_comp_device = {
	265	.name = "mct-comp",
	266	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	267	.rating = 250,
	268	.set_next_event = exynos4_comp_set_next_event,
	269	.set_mode = exynos4_comp_set_mode,
	270	};
	271
	272	static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
	273	{
	274	struct clock_event_device *evt = dev_id;
	275
	276	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
	277
	278	evt->event_handler(evt);
	279
	280	return IRQ_HANDLED;
	281	}
	282
	283	static struct irqaction mct_comp_event_irq = {
	284	.name = "mct_comp_irq",
	285	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	286	.handler = exynos4_mct_comp_isr,
	287	.dev_id = &mct_comp_device,
	288	};
	289
	290	static void exynos4_clockevent_init(void)
	291	{
30d8bead	292	mct_comp_device.cpumask = cpumask_of(0);
838a2ae8 SG	293	clockevents_config_and_register(&mct_comp_device, clk_rate,
838a2ae8 SG	294	0xf, 0xffffffff);
c371dc60	295	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
30d8bead CY	296	}
30d8bead CY	297
991a6c7d KK	298	static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
991a6c7d KK	299
30d8bead CY	300	/* Clock event handling */
	301	static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
	302	{
	303	unsigned long tmp;
	304	unsigned long mask = MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START;
a1ba7a7a	305	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
30d8bead	306
a1ba7a7a	307	tmp = __raw_readl(reg_base + offset);
30d8bead CY	308	if (tmp & mask) {
30d8bead CY	309	tmp &= ~mask;
a1ba7a7a	310	exynos4_mct_write(tmp, offset);
30d8bead CY	311	}
	312	}
	313
	314	static void exynos4_mct_tick_start(unsigned long cycles,
	315	struct mct_clock_event_device *mevt)
	316	{
	317	unsigned long tmp;
	318
	319	exynos4_mct_tick_stop(mevt);
	320
	321	tmp = (1 << 31) \| cycles; /* MCT_L_UPDATE_ICNTB */
	322
	323	/* update interrupt count buffer */
	324	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
	325
25985edc	326	/* enable MCT tick interrupt */
30d8bead CY	327	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
30d8bead CY	328
a1ba7a7a	329	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
30d8bead CY	330	tmp \|= MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START \|
	331	MCT_L_TCON_INTERVAL_MODE;
	332	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
	333	}
	334
	335	static int exynos4_tick_set_next_event(unsigned long cycles,
	336	struct clock_event_device *evt)
	337	{
e700e41d	338	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
30d8bead CY	339
	340	exynos4_mct_tick_start(cycles, mevt);
	341
	342	return 0;
	343	}
	344
	345	static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
	346	struct clock_event_device *evt)
	347	{
e700e41d	348	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
4d2e4d7f	349	unsigned long cycles_per_jiffy;
30d8bead CY	350
	351	exynos4_mct_tick_stop(mevt);
	352
	353	switch (mode) {
	354	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	355	cycles_per_jiffy =
	356	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	357	exynos4_mct_tick_start(cycles_per_jiffy, mevt);
30d8bead CY	358	break;
	359
	360	case CLOCK_EVT_MODE_ONESHOT:
	361	case CLOCK_EVT_MODE_UNUSED:
	362	case CLOCK_EVT_MODE_SHUTDOWN:
	363	case CLOCK_EVT_MODE_RESUME:
	364	break;
	365	}
	366	}
	367
c8987470	368	static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
30d8bead	369	{
ee98d27d	370	struct clock_event_device *evt = &mevt->evt;
30d8bead CY	371
	372	/*
	373	* This is for supporting oneshot mode.
	374	* Mct would generate interrupt periodically
	375	* without explicit stopping.
	376	*/
	377	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
	378	exynos4_mct_tick_stop(mevt);
	379
	380	/* Clear the MCT tick interrupt */
a1ba7a7a	381	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
3a062281 CY	382	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
	383	return 1;
	384	} else {
	385	return 0;
	386	}
	387	}
	388
	389	static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
	390	{
	391	struct mct_clock_event_device *mevt = dev_id;
ee98d27d	392	struct clock_event_device *evt = &mevt->evt;
3a062281 CY	393
3a062281 CY	394	exynos4_mct_tick_clear(mevt);
30d8bead CY	395
	396	evt->event_handler(evt);
	397
	398	return IRQ_HANDLED;
	399	}
	400
8c37bb3a	401	static int exynos4_local_timer_setup(struct clock_event_device *evt)
30d8bead	402	{
e700e41d	403	struct mct_clock_event_device *mevt;
30d8bead CY	404	unsigned int cpu = smp_processor_id();
30d8bead CY	405
ee98d27d	406	mevt = container_of(evt, struct mct_clock_event_device, evt);
30d8bead	407
e700e41d MZ	408	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
e700e41d MZ	409	sprintf(mevt->name, "mct_tick%d", cpu);
30d8bead	410
e700e41d	411	evt->name = mevt->name;
30d8bead CY	412	evt->cpumask = cpumask_of(cpu);
	413	evt->set_next_event = exynos4_tick_set_next_event;
	414	evt->set_mode = exynos4_tick_set_mode;
	415	evt->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	416	evt->rating = 450;
838a2ae8 SG	417	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
838a2ae8 SG	418	0xf, 0x7fffffff);
30d8bead	419
4d2e4d7f	420	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
30d8bead	421
3a062281	422	if (mct_int_type == MCT_INT_SPI) {
7114cd74 CK	423	evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
	424	if (request_irq(evt->irq, exynos4_mct_tick_isr,
	425	IRQF_TIMER \| IRQF_NOBALANCING,
	426	evt->name, mevt)) {
	427	pr_err("exynos-mct: cannot register IRQ %d\n",
	428	evt->irq);
	429	return -EIO;
3a062281	430	}
7114cd74	431	irq_set_affinity(evt->irq, cpumask_of(cpu));
30d8bead	432	} else {
c371dc60	433	enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
30d8bead	434	}
4d487d7e KK	435
4d487d7e KK	436	return 0;
30d8bead CY	437	}
30d8bead CY	438
a8cb6041	439	static void exynos4_local_timer_stop(struct clock_event_device *evt)
30d8bead	440	{
28af690a	441	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
e700e41d	442	if (mct_int_type == MCT_INT_SPI)
7114cd74	443	free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
e700e41d	444	else
c371dc60	445	disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
30d8bead	446	}
a8cb6041	447
47dcd356	448	static int exynos4_mct_cpu_notify(struct notifier_block *self,
ee98d27d SB	449	unsigned long action, void *hcpu)
	450	{
	451	struct mct_clock_event_device *mevt;
	452
	453	/*
	454	* Grab cpu pointer in each case to avoid spurious
	455	* preemptible warnings
	456	*/
	457	switch (action & ~CPU_TASKS_FROZEN) {
	458	case CPU_STARTING:
	459	mevt = this_cpu_ptr(&percpu_mct_tick);
	460	exynos4_local_timer_setup(&mevt->evt);
	461	break;
	462	case CPU_DYING:
	463	mevt = this_cpu_ptr(&percpu_mct_tick);
	464	exynos4_local_timer_stop(&mevt->evt);
	465	break;
	466	}
	467
	468	return NOTIFY_OK;
	469	}
	470
47dcd356	471	static struct notifier_block exynos4_mct_cpu_nb = {
ee98d27d	472	.notifier_call = exynos4_mct_cpu_notify,
a8cb6041	473	};
30d8bead	474
19ce4f4a	475	static void __init exynos4_timer_resources(struct device_node np, void __iomem base)
30d8bead	476	{
ee98d27d SB	477	int err;
ee98d27d SB	478	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
ca9048ec	479	struct clk mct_clk, tick_clk;
30d8bead	480
415ac2e2 TA	481	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
	482	clk_get(NULL, "fin_pll");
	483	if (IS_ERR(tick_clk))
	484	panic("%s: unable to determine tick clock rate\n", __func__);
	485	clk_rate = clk_get_rate(tick_clk);
e700e41d	486
ca9048ec TA	487	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	488	if (IS_ERR(mct_clk))
	489	panic("%s: unable to retrieve mct clock instance\n", __func__);
	490	clk_prepare_enable(mct_clk);
e700e41d	491
228e3023	492	reg_base = base;
36ba5d52 TA	493	if (!reg_base)
36ba5d52 TA	494	panic("%s: unable to ioremap mct address space\n", __func__);
a1ba7a7a	495
e700e41d	496	if (mct_int_type == MCT_INT_PPI) {
e700e41d	497
c371dc60	498	err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
e700e41d MZ	499	exynos4_mct_tick_isr, "MCT",
	500	&percpu_mct_tick);
	501	WARN(err, "MCT: can't request IRQ %d (%d)\n",
c371dc60	502	mct_irqs[MCT_L0_IRQ], err);
e700e41d	503	}
a8cb6041	504
ee98d27d SB	505	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
	506	if (err)
	507	goto out_irq;
	508
	509	/* Immediately configure the timer on the boot CPU */
	510	exynos4_local_timer_setup(&mevt->evt);
	511	return;
	512
	513	out_irq:
	514	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
30d8bead CY	515	}
30d8bead CY	516
034c097c	517	void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
30d8bead	518	{
034c097c AB	519	mct_irqs[MCT_G0_IRQ] = irq_g0;
	520	mct_irqs[MCT_L0_IRQ] = irq_l0;
	521	mct_irqs[MCT_L1_IRQ] = irq_l1;
	522	mct_int_type = MCT_INT_SPI;
2edb36c4	523
034c097c	524	exynos4_timer_resources(NULL, base);
30d8bead CY	525	exynos4_clocksource_init();
	526	exynos4_clockevent_init();
	527	}
3a062281	528
228e3023 AB	529	static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
	530	{
	531	u32 nr_irqs, i;
	532
	533	mct_int_type = int_type;
	534
	535	/* This driver uses only one global timer interrupt */
	536	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
	537
	538	/*
	539	* Find out the number of local irqs specified. The local
	540	* timer irqs are specified after the four global timer
	541	* irqs are specified.
	542	*/
f4636d0a	543	#ifdef CONFIG_OF
228e3023	544	nr_irqs = of_irq_count(np);
f4636d0a AB	545	#else
	546	nr_irqs = 0;
	547	#endif
228e3023 AB	548	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
	549	mct_irqs[i] = irq_of_parse_and_map(np, i);
	550
19ce4f4a	551	exynos4_timer_resources(np, of_iomap(np, 0));
30d8bead CY	552	exynos4_clocksource_init();
	553	exynos4_clockevent_init();
	554	}
228e3023 AB	555
	556
	557	static void __init mct_init_spi(struct device_node *np)
	558	{
	559	return mct_init_dt(np, MCT_INT_SPI);
	560	}
	561
	562	static void __init mct_init_ppi(struct device_node *np)
	563	{
	564	return mct_init_dt(np, MCT_INT_PPI);
	565	}
	566	CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
	567	CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);