[deliverable/linux.git] / drivers / clocksource / exynos_mct.c

/* linux/arch/arm/mach-exynos4/mct.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4 MCT(Multi-Core Timer) support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/clocksource.h>
#include <linux/sched_clock.h>

#define EXYNOS4_MCTREG(x)		(x)
#define EXYNOS4_MCT_G_CNT_L		EXYNOS4_MCTREG(0x100)
#define EXYNOS4_MCT_G_CNT_U		EXYNOS4_MCTREG(0x104)
#define EXYNOS4_MCT_G_CNT_WSTAT		EXYNOS4_MCTREG(0x110)
#define EXYNOS4_MCT_G_COMP0_L		EXYNOS4_MCTREG(0x200)
#define EXYNOS4_MCT_G_COMP0_U		EXYNOS4_MCTREG(0x204)
#define EXYNOS4_MCT_G_COMP0_ADD_INCR	EXYNOS4_MCTREG(0x208)
#define EXYNOS4_MCT_G_TCON		EXYNOS4_MCTREG(0x240)
#define EXYNOS4_MCT_G_INT_CSTAT		EXYNOS4_MCTREG(0x244)
#define EXYNOS4_MCT_G_INT_ENB		EXYNOS4_MCTREG(0x248)
#define EXYNOS4_MCT_G_WSTAT		EXYNOS4_MCTREG(0x24C)
#define _EXYNOS4_MCT_L_BASE		EXYNOS4_MCTREG(0x300)
#define EXYNOS4_MCT_L_BASE(x)		(_EXYNOS4_MCT_L_BASE + (0x100 * x))
#define EXYNOS4_MCT_L_MASK		(0xffffff00)

#define MCT_L_TCNTB_OFFSET		(0x00)
#define MCT_L_ICNTB_OFFSET		(0x08)
#define MCT_L_TCON_OFFSET		(0x20)
#define MCT_L_INT_CSTAT_OFFSET		(0x30)
#define MCT_L_INT_ENB_OFFSET		(0x34)
#define MCT_L_WSTAT_OFFSET		(0x40)
#define MCT_G_TCON_START		(1 << 8)
#define MCT_G_TCON_COMP0_AUTO_INC	(1 << 1)
#define MCT_G_TCON_COMP0_ENABLE		(1 << 0)
#define MCT_L_TCON_INTERVAL_MODE	(1 << 2)
#define MCT_L_TCON_INT_START		(1 << 1)
#define MCT_L_TCON_TIMER_START		(1 << 0)

#define TICK_BASE_CNT	1

enum {
	MCT_INT_SPI,
	MCT_INT_PPI
};

enum {
	MCT_G0_IRQ,
	MCT_G1_IRQ,
	MCT_G2_IRQ,
	MCT_G3_IRQ,
	MCT_L0_IRQ,
	MCT_L1_IRQ,
	MCT_L2_IRQ,
	MCT_L3_IRQ,
	MCT_L4_IRQ,
	MCT_L5_IRQ,
	MCT_L6_IRQ,
	MCT_L7_IRQ,
	MCT_NR_IRQS,
};

static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
static int mct_irqs[MCT_NR_IRQS];

struct mct_clock_event_device {
	struct clock_event_device evt;
	unsigned long base;
	char name[10];
};

static void exynos4_mct_write(unsigned int value, unsigned long offset)
{
	unsigned long stat_addr;
	u32 mask;
	u32 i;

	__raw_writel(value, reg_base + offset);

	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
		stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
		switch (offset & EXYNOS4_MCT_L_MASK) {
		case MCT_L_TCON_OFFSET:
			mask = 1 << 3;		/* L_TCON write status */
			break;
		case MCT_L_ICNTB_OFFSET:
			mask = 1 << 1;		/* L_ICNTB write status */
			break;
		case MCT_L_TCNTB_OFFSET:
			mask = 1 << 0;		/* L_TCNTB write status */
			break;
		default:
			return;
		}
	} else {
		switch (offset) {
		case EXYNOS4_MCT_G_TCON:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 16;		/* G_TCON write status */
			break;
		case EXYNOS4_MCT_G_COMP0_L:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 0;		/* G_COMP0_L write status */
			break;
		case EXYNOS4_MCT_G_COMP0_U:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 1;		/* G_COMP0_U write status */
			break;
		case EXYNOS4_MCT_G_COMP0_ADD_INCR:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 2;		/* G_COMP0_ADD_INCR w status */
			break;
		case EXYNOS4_MCT_G_CNT_L:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 0;		/* G_CNT_L write status */
			break;
		case EXYNOS4_MCT_G_CNT_U:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 1;		/* G_CNT_U write status */
			break;
		default:
			return;
		}
	}

	/* Wait maximum 1 ms until written values are applied */
	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
		if (__raw_readl(reg_base + stat_addr) & mask) {
			__raw_writel(mask, reg_base + stat_addr);
			return;
		}

	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
}

/* Clocksource handling */
static void exynos4_mct_frc_start(void)
{
	u32 reg;

	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	reg |= MCT_G_TCON_START;
	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}

static cycle_t exynos4_frc_read(struct clocksource *cs)
{
	unsigned int lo, hi;
	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);

	do {
		hi = hi2;
		lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
		hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
	} while (hi != hi2);

	return ((cycle_t)hi << 32) | lo;
}

static void exynos4_frc_resume(struct clocksource *cs)
{
	exynos4_mct_frc_start();
}

struct clocksource mct_frc = {
	.name		= "mct-frc",
	.rating		= 400,
	.read		= exynos4_frc_read,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= exynos4_frc_resume,
};

static u64 notrace exynos4_read_sched_clock(void)
{
	return exynos4_frc_read(&mct_frc);
}

static void __init exynos4_clocksource_init(void)
{
	exynos4_mct_frc_start();

	if (clocksource_register_hz(&mct_frc, clk_rate))
		panic("%s: can't register clocksource\n", mct_frc.name);

	sched_clock_register(exynos4_read_sched_clock, 64, clk_rate);
}

static void exynos4_mct_comp0_stop(void)
{
	unsigned int tcon;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);

	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
}

static void exynos4_mct_comp0_start(enum clock_event_mode mode,
				    unsigned long cycles)
{
	unsigned int tcon;
	cycle_t comp_cycle;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);

	if (mode == CLOCK_EVT_MODE_PERIODIC) {
		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	}

	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);

	tcon |= MCT_G_TCON_COMP0_ENABLE;
	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
}

static int exynos4_comp_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	exynos4_mct_comp0_start(evt->mode, cycles);

	return 0;
}

static void exynos4_comp_set_mode(enum clock_event_mode mode,
				  struct clock_event_device *evt)
{
	unsigned long cycles_per_jiffy;
	exynos4_mct_comp0_stop();

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_comp0_start(mode, cycles_per_jiffy);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device mct_comp_device = {
	.name		= "mct-comp",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 250,
	.set_next_event	= exynos4_comp_set_next_event,
	.set_mode	= exynos4_comp_set_mode,
};

static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mct_comp_event_irq = {
	.name		= "mct_comp_irq",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= exynos4_mct_comp_isr,
	.dev_id		= &mct_comp_device,
};

static void exynos4_clockevent_init(void)
{
	mct_comp_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mct_comp_device, clk_rate,
					0xf, 0xffffffff);
	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
}

static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);

/* Clock event handling */
static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
	unsigned long tmp;
	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;

	tmp = __raw_readl(reg_base + offset);
	if (tmp & mask) {
		tmp &= ~mask;
		exynos4_mct_write(tmp, offset);
	}
}

static void exynos4_mct_tick_start(unsigned long cycles,
				   struct mct_clock_event_device *mevt)
{
	unsigned long tmp;

	exynos4_mct_tick_stop(mevt);

	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */

	/* update interrupt count buffer */
	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);

	/* enable MCT tick interrupt */
	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);

	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
	       MCT_L_TCON_INTERVAL_MODE;
	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
}

static int exynos4_tick_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);

	exynos4_mct_tick_start(cycles, mevt);

	return 0;
}

static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
					 struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	unsigned long cycles_per_jiffy;

	exynos4_mct_tick_stop(mevt);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_tick_start(cycles_per_jiffy, mevt);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
	struct clock_event_device *evt = &mevt->evt;

	/*
	 * This is for supporting oneshot mode.
	 * Mct would generate interrupt periodically
	 * without explicit stopping.
	 */
	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
		exynos4_mct_tick_stop(mevt);

	/* Clear the MCT tick interrupt */
	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
		return 1;
	} else {
		return 0;
	}
}

static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
{
	struct mct_clock_event_device *mevt = dev_id;
	struct clock_event_device *evt = &mevt->evt;

	exynos4_mct_tick_clear(mevt);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static int exynos4_local_timer_setup(struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt;
	unsigned int cpu = smp_processor_id();

	mevt = container_of(evt, struct mct_clock_event_device, evt);

	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);

	evt->name = mevt->name;
	evt->cpumask = cpumask_of(cpu);
	evt->set_next_event = exynos4_tick_set_next_event;
	evt->set_mode = exynos4_tick_set_mode;
	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 450;

	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);

	if (mct_int_type == MCT_INT_SPI) {
		evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
		if (request_irq(evt->irq, exynos4_mct_tick_isr,
				IRQF_TIMER | IRQF_NOBALANCING,
				evt->name, mevt)) {
			pr_err("exynos-mct: cannot register IRQ %d\n",
				evt->irq);
			return -EIO;
		}
		irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], cpumask_of(cpu));
	} else {
		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
	}
	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
					0xf, 0x7fffffff);

	return 0;
}

static void exynos4_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	if (mct_int_type == MCT_INT_SPI)
		free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
	else
		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}

static int exynos4_mct_cpu_notify(struct notifier_block *self,
					   unsigned long action, void *hcpu)
{
	struct mct_clock_event_device *mevt;

	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		mevt = this_cpu_ptr(&percpu_mct_tick);
		exynos4_local_timer_setup(&mevt->evt);
		break;
	case CPU_DYING:
		mevt = this_cpu_ptr(&percpu_mct_tick);
		exynos4_local_timer_stop(&mevt->evt);
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block exynos4_mct_cpu_nb = {
	.notifier_call = exynos4_mct_cpu_notify,
};

static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
{
	int err;
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	struct clk *mct_clk, *tick_clk;

	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
				clk_get(NULL, "fin_pll");
	if (IS_ERR(tick_clk))
		panic("%s: unable to determine tick clock rate\n", __func__);
	clk_rate = clk_get_rate(tick_clk);

	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	if (IS_ERR(mct_clk))
		panic("%s: unable to retrieve mct clock instance\n", __func__);
	clk_prepare_enable(mct_clk);

	reg_base = base;
	if (!reg_base)
		panic("%s: unable to ioremap mct address space\n", __func__);

	if (mct_int_type == MCT_INT_PPI) {

		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
					 exynos4_mct_tick_isr, "MCT",
					 &percpu_mct_tick);
		WARN(err, "MCT: can't request IRQ %d (%d)\n",
		     mct_irqs[MCT_L0_IRQ], err);
	} else {
		irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
	}

	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
	if (err)
		goto out_irq;

	/* Immediately configure the timer on the boot CPU */
	exynos4_local_timer_setup(&mevt->evt);
	return;

out_irq:
	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
}

void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
{
	mct_irqs[MCT_G0_IRQ] = irq_g0;
	mct_irqs[MCT_L0_IRQ] = irq_l0;
	mct_irqs[MCT_L1_IRQ] = irq_l1;
	mct_int_type = MCT_INT_SPI;

	exynos4_timer_resources(NULL, base);
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}

static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
{
	u32 nr_irqs, i;

	mct_int_type = int_type;

	/* This driver uses only one global timer interrupt */
	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);

	/*
	 * Find out the number of local irqs specified. The local
	 * timer irqs are specified after the four global timer
	 * irqs are specified.
	 */
#ifdef CONFIG_OF
	nr_irqs = of_irq_count(np);
#else
	nr_irqs = 0;
#endif
	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
		mct_irqs[i] = irq_of_parse_and_map(np, i);

	exynos4_timer_resources(np, of_iomap(np, 0));
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}


static void __init mct_init_spi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_SPI);
}

static void __init mct_init_ppi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_PPI);
}
CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
Commit	Line	Data
30d8bead CY	1	/* linux/arch/arm/mach-exynos4/mct.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* EXYNOS4 MCT(Multi-Core Timer) support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
ee98d27d	19	#include <linux/cpu.h>
30d8bead CY	20	#include <linux/platform_device.h>
	21	#include <linux/delay.h>
	22	#include <linux/percpu.h>
2edb36c4	23	#include <linux/of.h>
36ba5d52 TA	24	#include <linux/of_irq.h>
36ba5d52 TA	25	#include <linux/of_address.h>
9fbf0c85	26	#include <linux/clocksource.h>
93bfb769	27	#include <linux/sched_clock.h>
30d8bead	28
a1ba7a7a TA	29	#define EXYNOS4_MCTREG(x) (x)
	30	#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
	31	#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
	32	#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
	33	#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
	34	#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
	35	#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
	36	#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
	37	#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
	38	#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
	39	#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
	40	#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
	41	#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
	42	#define EXYNOS4_MCT_L_MASK (0xffffff00)
	43
	44	#define MCT_L_TCNTB_OFFSET (0x00)
	45	#define MCT_L_ICNTB_OFFSET (0x08)
	46	#define MCT_L_TCON_OFFSET (0x20)
	47	#define MCT_L_INT_CSTAT_OFFSET (0x30)
	48	#define MCT_L_INT_ENB_OFFSET (0x34)
	49	#define MCT_L_WSTAT_OFFSET (0x40)
	50	#define MCT_G_TCON_START (1 << 8)
	51	#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
	52	#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
	53	#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
	54	#define MCT_L_TCON_INT_START (1 << 1)
	55	#define MCT_L_TCON_TIMER_START (1 << 0)
	56
4d2e4d7f CY	57	#define TICK_BASE_CNT 1
4d2e4d7f CY	58
3a062281 CY	59	enum {
	60	MCT_INT_SPI,
	61	MCT_INT_PPI
	62	};
	63
c371dc60 TA	64	enum {
	65	MCT_G0_IRQ,
	66	MCT_G1_IRQ,
	67	MCT_G2_IRQ,
	68	MCT_G3_IRQ,
	69	MCT_L0_IRQ,
	70	MCT_L1_IRQ,
	71	MCT_L2_IRQ,
	72	MCT_L3_IRQ,
6c16dedf CK	73	MCT_L4_IRQ,
	74	MCT_L5_IRQ,
	75	MCT_L6_IRQ,
	76	MCT_L7_IRQ,
c371dc60 TA	77	MCT_NR_IRQS,
	78	};
	79
a1ba7a7a	80	static void __iomem *reg_base;
30d8bead	81	static unsigned long clk_rate;
3a062281	82	static unsigned int mct_int_type;
c371dc60	83	static int mct_irqs[MCT_NR_IRQS];
30d8bead CY	84
30d8bead CY	85	struct mct_clock_event_device {
ee98d27d	86	struct clock_event_device evt;
a1ba7a7a	87	unsigned long base;
c8987470	88	char name[10];
30d8bead CY	89	};
30d8bead CY	90
a1ba7a7a	91	static void exynos4_mct_write(unsigned int value, unsigned long offset)
30d8bead	92	{
a1ba7a7a	93	unsigned long stat_addr;
30d8bead CY	94	u32 mask;
	95	u32 i;
	96
a1ba7a7a	97	__raw_writel(value, reg_base + offset);
30d8bead	98
a1ba7a7a TA	99	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
	100	stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
	101	switch (offset & EXYNOS4_MCT_L_MASK) {
	102	case MCT_L_TCON_OFFSET:
c8987470 CY	103	mask = 1 << 3; /* L_TCON write status */
c8987470 CY	104	break;
a1ba7a7a	105	case MCT_L_ICNTB_OFFSET:
c8987470 CY	106	mask = 1 << 1; /* L_ICNTB write status */
c8987470 CY	107	break;
a1ba7a7a	108	case MCT_L_TCNTB_OFFSET:
c8987470 CY	109	mask = 1 << 0; /* L_TCNTB write status */
	110	break;
	111	default:
	112	return;
	113	}
	114	} else {
a1ba7a7a TA	115	switch (offset) {
a1ba7a7a TA	116	case EXYNOS4_MCT_G_TCON:
c8987470 CY	117	stat_addr = EXYNOS4_MCT_G_WSTAT;
	118	mask = 1 << 16; /* G_TCON write status */
	119	break;
a1ba7a7a	120	case EXYNOS4_MCT_G_COMP0_L:
c8987470 CY	121	stat_addr = EXYNOS4_MCT_G_WSTAT;
	122	mask = 1 << 0; /* G_COMP0_L write status */
	123	break;
a1ba7a7a	124	case EXYNOS4_MCT_G_COMP0_U:
c8987470 CY	125	stat_addr = EXYNOS4_MCT_G_WSTAT;
	126	mask = 1 << 1; /* G_COMP0_U write status */
	127	break;
a1ba7a7a	128	case EXYNOS4_MCT_G_COMP0_ADD_INCR:
c8987470 CY	129	stat_addr = EXYNOS4_MCT_G_WSTAT;
	130	mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
	131	break;
a1ba7a7a	132	case EXYNOS4_MCT_G_CNT_L:
c8987470 CY	133	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	134	mask = 1 << 0; /* G_CNT_L write status */
	135	break;
a1ba7a7a	136	case EXYNOS4_MCT_G_CNT_U:
c8987470 CY	137	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	138	mask = 1 << 1; /* G_CNT_U write status */
	139	break;
	140	default:
	141	return;
	142	}
30d8bead CY	143	}
	144
	145	/* Wait maximum 1 ms until written values are applied */
	146	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
a1ba7a7a TA	147	if (__raw_readl(reg_base + stat_addr) & mask) {
a1ba7a7a TA	148	__raw_writel(mask, reg_base + stat_addr);
30d8bead CY	149	return;
	150	}
	151
a1ba7a7a	152	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
30d8bead CY	153	}
	154
	155	/* Clocksource handling */
1d80415d	156	static void exynos4_mct_frc_start(void)
30d8bead CY	157	{
	158	u32 reg;
	159
a1ba7a7a	160	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	161	reg \|= MCT_G_TCON_START;
	162	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
	163	}
	164
	165	static cycle_t exynos4_frc_read(struct clocksource *cs)
	166	{
	167	unsigned int lo, hi;
a1ba7a7a	168	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	169
	170	do {
	171	hi = hi2;
a1ba7a7a TA	172	lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
a1ba7a7a TA	173	hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	174	} while (hi != hi2);
	175
	176	return ((cycle_t)hi << 32) \| lo;
	177	}
	178
aa421c13 CY	179	static void exynos4_frc_resume(struct clocksource *cs)
aa421c13 CY	180	{
1d80415d	181	exynos4_mct_frc_start();
aa421c13 CY	182	}
aa421c13 CY	183
30d8bead CY	184	struct clocksource mct_frc = {
	185	.name = "mct-frc",
	186	.rating = 400,
	187	.read = exynos4_frc_read,
	188	.mask = CLOCKSOURCE_MASK(64),
	189	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
aa421c13	190	.resume = exynos4_frc_resume,
30d8bead CY	191	};
30d8bead CY	192
93bfb769 VG	193	static u64 notrace exynos4_read_sched_clock(void)
	194	{
	195	return exynos4_frc_read(&mct_frc);
	196	}
	197
30d8bead CY	198	static void __init exynos4_clocksource_init(void)
30d8bead CY	199	{
1d80415d	200	exynos4_mct_frc_start();
30d8bead CY	201
	202	if (clocksource_register_hz(&mct_frc, clk_rate))
	203	panic("%s: can't register clocksource\n", mct_frc.name);
93bfb769 VG	204
93bfb769 VG	205	sched_clock_register(exynos4_read_sched_clock, 64, clk_rate);
30d8bead CY	206	}
	207
	208	static void exynos4_mct_comp0_stop(void)
	209	{
	210	unsigned int tcon;
	211
a1ba7a7a	212	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	213	tcon &= ~(MCT_G_TCON_COMP0_ENABLE \| MCT_G_TCON_COMP0_AUTO_INC);
	214
	215	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	216	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
	217	}
	218
	219	static void exynos4_mct_comp0_start(enum clock_event_mode mode,
	220	unsigned long cycles)
	221	{
	222	unsigned int tcon;
	223	cycle_t comp_cycle;
	224
a1ba7a7a	225	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	226
	227	if (mode == CLOCK_EVT_MODE_PERIODIC) {
	228	tcon \|= MCT_G_TCON_COMP0_AUTO_INC;
	229	exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	230	}
	231
	232	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	233	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	234	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
	235
	236	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
	237
	238	tcon \|= MCT_G_TCON_COMP0_ENABLE;
	239	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
	240	}
	241
	242	static int exynos4_comp_set_next_event(unsigned long cycles,
	243	struct clock_event_device *evt)
	244	{
	245	exynos4_mct_comp0_start(evt->mode, cycles);
	246
	247	return 0;
	248	}
	249
	250	static void exynos4_comp_set_mode(enum clock_event_mode mode,
	251	struct clock_event_device *evt)
	252	{
4d2e4d7f	253	unsigned long cycles_per_jiffy;
30d8bead CY	254	exynos4_mct_comp0_stop();
	255
	256	switch (mode) {
	257	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	258	cycles_per_jiffy =
	259	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	260	exynos4_mct_comp0_start(mode, cycles_per_jiffy);
30d8bead CY	261	break;
	262
	263	case CLOCK_EVT_MODE_ONESHOT:
	264	case CLOCK_EVT_MODE_UNUSED:
	265	case CLOCK_EVT_MODE_SHUTDOWN:
	266	case CLOCK_EVT_MODE_RESUME:
	267	break;
	268	}
	269	}
	270
	271	static struct clock_event_device mct_comp_device = {
	272	.name = "mct-comp",
	273	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	274	.rating = 250,
	275	.set_next_event = exynos4_comp_set_next_event,
	276	.set_mode = exynos4_comp_set_mode,
	277	};
	278
	279	static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
	280	{
	281	struct clock_event_device *evt = dev_id;
	282
	283	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
	284
	285	evt->event_handler(evt);
	286
	287	return IRQ_HANDLED;
	288	}
	289
	290	static struct irqaction mct_comp_event_irq = {
	291	.name = "mct_comp_irq",
	292	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	293	.handler = exynos4_mct_comp_isr,
	294	.dev_id = &mct_comp_device,
	295	};
	296
	297	static void exynos4_clockevent_init(void)
	298	{
30d8bead	299	mct_comp_device.cpumask = cpumask_of(0);
838a2ae8 SG	300	clockevents_config_and_register(&mct_comp_device, clk_rate,
838a2ae8 SG	301	0xf, 0xffffffff);
c371dc60	302	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
30d8bead CY	303	}
30d8bead CY	304
991a6c7d KK	305	static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
991a6c7d KK	306
30d8bead CY	307	/* Clock event handling */
	308	static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
	309	{
	310	unsigned long tmp;
	311	unsigned long mask = MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START;
a1ba7a7a	312	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
30d8bead	313
a1ba7a7a	314	tmp = __raw_readl(reg_base + offset);
30d8bead CY	315	if (tmp & mask) {
30d8bead CY	316	tmp &= ~mask;
a1ba7a7a	317	exynos4_mct_write(tmp, offset);
30d8bead CY	318	}
	319	}
	320
	321	static void exynos4_mct_tick_start(unsigned long cycles,
	322	struct mct_clock_event_device *mevt)
	323	{
	324	unsigned long tmp;
	325
	326	exynos4_mct_tick_stop(mevt);
	327
	328	tmp = (1 << 31) \| cycles; /* MCT_L_UPDATE_ICNTB */
	329
	330	/* update interrupt count buffer */
	331	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
	332
25985edc	333	/* enable MCT tick interrupt */
30d8bead CY	334	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
30d8bead CY	335
a1ba7a7a	336	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
30d8bead CY	337	tmp \|= MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START \|
	338	MCT_L_TCON_INTERVAL_MODE;
	339	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
	340	}
	341
	342	static int exynos4_tick_set_next_event(unsigned long cycles,
	343	struct clock_event_device *evt)
	344	{
e700e41d	345	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
30d8bead CY	346
	347	exynos4_mct_tick_start(cycles, mevt);
	348
	349	return 0;
	350	}
	351
	352	static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
	353	struct clock_event_device *evt)
	354	{
e700e41d	355	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
4d2e4d7f	356	unsigned long cycles_per_jiffy;
30d8bead CY	357
	358	exynos4_mct_tick_stop(mevt);
	359
	360	switch (mode) {
	361	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	362	cycles_per_jiffy =
	363	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	364	exynos4_mct_tick_start(cycles_per_jiffy, mevt);
30d8bead CY	365	break;
	366
	367	case CLOCK_EVT_MODE_ONESHOT:
	368	case CLOCK_EVT_MODE_UNUSED:
	369	case CLOCK_EVT_MODE_SHUTDOWN:
	370	case CLOCK_EVT_MODE_RESUME:
	371	break;
	372	}
	373	}
	374
c8987470	375	static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
30d8bead	376	{
ee98d27d	377	struct clock_event_device *evt = &mevt->evt;
30d8bead CY	378
	379	/*
	380	* This is for supporting oneshot mode.
	381	* Mct would generate interrupt periodically
	382	* without explicit stopping.
	383	*/
	384	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
	385	exynos4_mct_tick_stop(mevt);
	386
	387	/* Clear the MCT tick interrupt */
a1ba7a7a	388	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
3a062281 CY	389	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
	390	return 1;
	391	} else {
	392	return 0;
	393	}
	394	}
	395
	396	static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
	397	{
	398	struct mct_clock_event_device *mevt = dev_id;
ee98d27d	399	struct clock_event_device *evt = &mevt->evt;
3a062281 CY	400
3a062281 CY	401	exynos4_mct_tick_clear(mevt);
30d8bead CY	402
	403	evt->event_handler(evt);
	404
	405	return IRQ_HANDLED;
	406	}
	407
8c37bb3a	408	static int exynos4_local_timer_setup(struct clock_event_device *evt)
30d8bead	409	{
e700e41d	410	struct mct_clock_event_device *mevt;
30d8bead CY	411	unsigned int cpu = smp_processor_id();
30d8bead CY	412
ee98d27d	413	mevt = container_of(evt, struct mct_clock_event_device, evt);
30d8bead	414
e700e41d	415	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
09e15176	416	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
30d8bead	417
e700e41d	418	evt->name = mevt->name;
30d8bead CY	419	evt->cpumask = cpumask_of(cpu);
	420	evt->set_next_event = exynos4_tick_set_next_event;
	421	evt->set_mode = exynos4_tick_set_mode;
	422	evt->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	423	evt->rating = 450;
30d8bead	424
4d2e4d7f	425	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
30d8bead	426
3a062281	427	if (mct_int_type == MCT_INT_SPI) {
7114cd74 CK	428	evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
	429	if (request_irq(evt->irq, exynos4_mct_tick_isr,
	430	IRQF_TIMER \| IRQF_NOBALANCING,
	431	evt->name, mevt)) {
	432	pr_err("exynos-mct: cannot register IRQ %d\n",
	433	evt->irq);
	434	return -EIO;
3a062281	435	}
30ccf03b	436	irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], cpumask_of(cpu));
30d8bead	437	} else {
c371dc60	438	enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
30d8bead	439	}
8db6e510 KK	440	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
8db6e510 KK	441	0xf, 0x7fffffff);
4d487d7e KK	442
4d487d7e KK	443	return 0;
30d8bead CY	444	}
30d8bead CY	445
a8cb6041	446	static void exynos4_local_timer_stop(struct clock_event_device *evt)
30d8bead	447	{
28af690a	448	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
e700e41d	449	if (mct_int_type == MCT_INT_SPI)
7114cd74	450	free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
e700e41d	451	else
c371dc60	452	disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
30d8bead	453	}
a8cb6041	454
47dcd356	455	static int exynos4_mct_cpu_notify(struct notifier_block *self,
ee98d27d SB	456	unsigned long action, void *hcpu)
	457	{
	458	struct mct_clock_event_device *mevt;
	459
	460	/*
	461	* Grab cpu pointer in each case to avoid spurious
	462	* preemptible warnings
	463	*/
	464	switch (action & ~CPU_TASKS_FROZEN) {
	465	case CPU_STARTING:
	466	mevt = this_cpu_ptr(&percpu_mct_tick);
	467	exynos4_local_timer_setup(&mevt->evt);
	468	break;
	469	case CPU_DYING:
	470	mevt = this_cpu_ptr(&percpu_mct_tick);
	471	exynos4_local_timer_stop(&mevt->evt);
	472	break;
	473	}
	474
	475	return NOTIFY_OK;
	476	}
	477
47dcd356	478	static struct notifier_block exynos4_mct_cpu_nb = {
ee98d27d	479	.notifier_call = exynos4_mct_cpu_notify,
a8cb6041	480	};
30d8bead	481
19ce4f4a	482	static void __init exynos4_timer_resources(struct device_node np, void __iomem base)
30d8bead	483	{
ee98d27d SB	484	int err;
ee98d27d SB	485	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
ca9048ec	486	struct clk mct_clk, tick_clk;
30d8bead	487
415ac2e2 TA	488	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
	489	clk_get(NULL, "fin_pll");
	490	if (IS_ERR(tick_clk))
	491	panic("%s: unable to determine tick clock rate\n", __func__);
	492	clk_rate = clk_get_rate(tick_clk);
e700e41d	493
ca9048ec TA	494	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	495	if (IS_ERR(mct_clk))
	496	panic("%s: unable to retrieve mct clock instance\n", __func__);
	497	clk_prepare_enable(mct_clk);
e700e41d	498
228e3023	499	reg_base = base;
36ba5d52 TA	500	if (!reg_base)
36ba5d52 TA	501	panic("%s: unable to ioremap mct address space\n", __func__);
a1ba7a7a	502
e700e41d	503	if (mct_int_type == MCT_INT_PPI) {
e700e41d	504
c371dc60	505	err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
e700e41d MZ	506	exynos4_mct_tick_isr, "MCT",
	507	&percpu_mct_tick);
	508	WARN(err, "MCT: can't request IRQ %d (%d)\n",
c371dc60	509	mct_irqs[MCT_L0_IRQ], err);
5df718d8 TF	510	} else {
5df718d8 TF	511	irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
e700e41d	512	}
a8cb6041	513
ee98d27d SB	514	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
	515	if (err)
	516	goto out_irq;
	517
	518	/* Immediately configure the timer on the boot CPU */
	519	exynos4_local_timer_setup(&mevt->evt);
	520	return;
	521
	522	out_irq:
	523	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
30d8bead CY	524	}
30d8bead CY	525
034c097c	526	void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
30d8bead	527	{
034c097c AB	528	mct_irqs[MCT_G0_IRQ] = irq_g0;
	529	mct_irqs[MCT_L0_IRQ] = irq_l0;
	530	mct_irqs[MCT_L1_IRQ] = irq_l1;
	531	mct_int_type = MCT_INT_SPI;
2edb36c4	532
034c097c	533	exynos4_timer_resources(NULL, base);
30d8bead CY	534	exynos4_clocksource_init();
	535	exynos4_clockevent_init();
	536	}
3a062281	537
228e3023 AB	538	static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
	539	{
	540	u32 nr_irqs, i;
	541
	542	mct_int_type = int_type;
	543
	544	/* This driver uses only one global timer interrupt */
	545	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
	546
	547	/*
	548	* Find out the number of local irqs specified. The local
	549	* timer irqs are specified after the four global timer
	550	* irqs are specified.
	551	*/
f4636d0a	552	#ifdef CONFIG_OF
228e3023	553	nr_irqs = of_irq_count(np);
f4636d0a AB	554	#else
	555	nr_irqs = 0;
	556	#endif
228e3023 AB	557	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
	558	mct_irqs[i] = irq_of_parse_and_map(np, i);
	559
19ce4f4a	560	exynos4_timer_resources(np, of_iomap(np, 0));
30d8bead CY	561	exynos4_clocksource_init();
	562	exynos4_clockevent_init();
	563	}
228e3023 AB	564
	565
	566	static void __init mct_init_spi(struct device_node *np)
	567	{
	568	return mct_init_dt(np, MCT_INT_SPI);
	569	}
	570
	571	static void __init mct_init_ppi(struct device_node *np)
	572	{
	573	return mct_init_dt(np, MCT_INT_PPI);
	574	}
	575	CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
	576	CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);