[deliverable/linux.git] / drivers / clocksource / exynos_mct.c

/* linux/arch/arm/mach-exynos4/mct.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4 MCT(Multi-Core Timer) support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/clocksource.h>

#define EXYNOS4_MCTREG(x)		(x)
#define EXYNOS4_MCT_G_CNT_L		EXYNOS4_MCTREG(0x100)
#define EXYNOS4_MCT_G_CNT_U		EXYNOS4_MCTREG(0x104)
#define EXYNOS4_MCT_G_CNT_WSTAT		EXYNOS4_MCTREG(0x110)
#define EXYNOS4_MCT_G_COMP0_L		EXYNOS4_MCTREG(0x200)
#define EXYNOS4_MCT_G_COMP0_U		EXYNOS4_MCTREG(0x204)
#define EXYNOS4_MCT_G_COMP0_ADD_INCR	EXYNOS4_MCTREG(0x208)
#define EXYNOS4_MCT_G_TCON		EXYNOS4_MCTREG(0x240)
#define EXYNOS4_MCT_G_INT_CSTAT		EXYNOS4_MCTREG(0x244)
#define EXYNOS4_MCT_G_INT_ENB		EXYNOS4_MCTREG(0x248)
#define EXYNOS4_MCT_G_WSTAT		EXYNOS4_MCTREG(0x24C)
#define _EXYNOS4_MCT_L_BASE		EXYNOS4_MCTREG(0x300)
#define EXYNOS4_MCT_L_BASE(x)		(_EXYNOS4_MCT_L_BASE + (0x100 * x))
#define EXYNOS4_MCT_L_MASK		(0xffffff00)

#define MCT_L_TCNTB_OFFSET		(0x00)
#define MCT_L_ICNTB_OFFSET		(0x08)
#define MCT_L_TCON_OFFSET		(0x20)
#define MCT_L_INT_CSTAT_OFFSET		(0x30)
#define MCT_L_INT_ENB_OFFSET		(0x34)
#define MCT_L_WSTAT_OFFSET		(0x40)
#define MCT_G_TCON_START		(1 << 8)
#define MCT_G_TCON_COMP0_AUTO_INC	(1 << 1)
#define MCT_G_TCON_COMP0_ENABLE		(1 << 0)
#define MCT_L_TCON_INTERVAL_MODE	(1 << 2)
#define MCT_L_TCON_INT_START		(1 << 1)
#define MCT_L_TCON_TIMER_START		(1 << 0)

#define TICK_BASE_CNT	1

enum {
	MCT_INT_SPI,
	MCT_INT_PPI
};

enum {
	MCT_G0_IRQ,
	MCT_G1_IRQ,
	MCT_G2_IRQ,
	MCT_G3_IRQ,
	MCT_L0_IRQ,
	MCT_L1_IRQ,
	MCT_L2_IRQ,
	MCT_L3_IRQ,
	MCT_L4_IRQ,
	MCT_L5_IRQ,
	MCT_L6_IRQ,
	MCT_L7_IRQ,
	MCT_NR_IRQS,
};

static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
static int mct_irqs[MCT_NR_IRQS];

struct mct_clock_event_device {
	struct clock_event_device evt;
	unsigned long base;
	char name[10];
};

static void exynos4_mct_write(unsigned int value, unsigned long offset)
{
	unsigned long stat_addr;
	u32 mask;
	u32 i;

	__raw_writel(value, reg_base + offset);

	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
		stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
		switch (offset & EXYNOS4_MCT_L_MASK) {
		case MCT_L_TCON_OFFSET:
			mask = 1 << 3;		/* L_TCON write status */
			break;
		case MCT_L_ICNTB_OFFSET:
			mask = 1 << 1;		/* L_ICNTB write status */
			break;
		case MCT_L_TCNTB_OFFSET:
			mask = 1 << 0;		/* L_TCNTB write status */
			break;
		default:
			return;
		}
	} else {
		switch (offset) {
		case EXYNOS4_MCT_G_TCON:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 16;		/* G_TCON write status */
			break;
		case EXYNOS4_MCT_G_COMP0_L:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 0;		/* G_COMP0_L write status */
			break;
		case EXYNOS4_MCT_G_COMP0_U:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 1;		/* G_COMP0_U write status */
			break;
		case EXYNOS4_MCT_G_COMP0_ADD_INCR:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 2;		/* G_COMP0_ADD_INCR w status */
			break;
		case EXYNOS4_MCT_G_CNT_L:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 0;		/* G_CNT_L write status */
			break;
		case EXYNOS4_MCT_G_CNT_U:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 1;		/* G_CNT_U write status */
			break;
		default:
			return;
		}
	}

	/* Wait maximum 1 ms until written values are applied */
	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
		if (__raw_readl(reg_base + stat_addr) & mask) {
			__raw_writel(mask, reg_base + stat_addr);
			return;
		}

	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
}

/* Clocksource handling */
static void exynos4_mct_frc_start(u32 hi, u32 lo)
{
	u32 reg;

	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);

	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	reg |= MCT_G_TCON_START;
	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}

static cycle_t exynos4_frc_read(struct clocksource *cs)
{
	unsigned int lo, hi;
	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);

	do {
		hi = hi2;
		lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
		hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
	} while (hi != hi2);

	return ((cycle_t)hi << 32) | lo;
}

static void exynos4_frc_resume(struct clocksource *cs)
{
	exynos4_mct_frc_start(0, 0);
}

struct clocksource mct_frc = {
	.name		= "mct-frc",
	.rating		= 400,
	.read		= exynos4_frc_read,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= exynos4_frc_resume,
};

static void __init exynos4_clocksource_init(void)
{
	exynos4_mct_frc_start(0, 0);

	if (clocksource_register_hz(&mct_frc, clk_rate))
		panic("%s: can't register clocksource\n", mct_frc.name);
}

static void exynos4_mct_comp0_stop(void)
{
	unsigned int tcon;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);

	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
}

static void exynos4_mct_comp0_start(enum clock_event_mode mode,
				    unsigned long cycles)
{
	unsigned int tcon;
	cycle_t comp_cycle;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);

	if (mode == CLOCK_EVT_MODE_PERIODIC) {
		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	}

	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);

	tcon |= MCT_G_TCON_COMP0_ENABLE;
	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
}

static int exynos4_comp_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	exynos4_mct_comp0_start(evt->mode, cycles);

	return 0;
}

static void exynos4_comp_set_mode(enum clock_event_mode mode,
				  struct clock_event_device *evt)
{
	unsigned long cycles_per_jiffy;
	exynos4_mct_comp0_stop();

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_comp0_start(mode, cycles_per_jiffy);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device mct_comp_device = {
	.name		= "mct-comp",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 250,
	.set_next_event	= exynos4_comp_set_next_event,
	.set_mode	= exynos4_comp_set_mode,
};

static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mct_comp_event_irq = {
	.name		= "mct_comp_irq",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= exynos4_mct_comp_isr,
	.dev_id		= &mct_comp_device,
};

static void exynos4_clockevent_init(void)
{
	mct_comp_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mct_comp_device, clk_rate,
					0xf, 0xffffffff);
	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
}

static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);

/* Clock event handling */
static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
	unsigned long tmp;
	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;

	tmp = __raw_readl(reg_base + offset);
	if (tmp & mask) {
		tmp &= ~mask;
		exynos4_mct_write(tmp, offset);
	}
}

static void exynos4_mct_tick_start(unsigned long cycles,
				   struct mct_clock_event_device *mevt)
{
	unsigned long tmp;

	exynos4_mct_tick_stop(mevt);

	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */

	/* update interrupt count buffer */
	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);

	/* enable MCT tick interrupt */
	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);

	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
	       MCT_L_TCON_INTERVAL_MODE;
	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
}

static int exynos4_tick_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);

	exynos4_mct_tick_start(cycles, mevt);

	return 0;
}

static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
					 struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	unsigned long cycles_per_jiffy;

	exynos4_mct_tick_stop(mevt);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_tick_start(cycles_per_jiffy, mevt);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
	struct clock_event_device *evt = &mevt->evt;

	/*
	 * This is for supporting oneshot mode.
	 * Mct would generate interrupt periodically
	 * without explicit stopping.
	 */
	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
		exynos4_mct_tick_stop(mevt);

	/* Clear the MCT tick interrupt */
	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
		return 1;
	} else {
		return 0;
	}
}

static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
{
	struct mct_clock_event_device *mevt = dev_id;
	struct clock_event_device *evt = &mevt->evt;

	exynos4_mct_tick_clear(mevt);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static int exynos4_local_timer_setup(struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt;
	unsigned int cpu = smp_processor_id();

	mevt = container_of(evt, struct mct_clock_event_device, evt);

	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);

	evt->name = mevt->name;
	evt->cpumask = cpumask_of(cpu);
	evt->set_next_event = exynos4_tick_set_next_event;
	evt->set_mode = exynos4_tick_set_mode;
	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 450;
	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
					0xf, 0x7fffffff);

	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);

	if (mct_int_type == MCT_INT_SPI) {
		evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
		if (request_irq(evt->irq, exynos4_mct_tick_isr,
				IRQF_TIMER | IRQF_NOBALANCING,
				evt->name, mevt)) {
			pr_err("exynos-mct: cannot register IRQ %d\n",
				evt->irq);
			return -EIO;
		}
	} else {
		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
	}

	return 0;
}

static void exynos4_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	if (mct_int_type == MCT_INT_SPI)
		free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
	else
		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}

static int exynos4_mct_cpu_notify(struct notifier_block *self,
					   unsigned long action, void *hcpu)
{
	struct mct_clock_event_device *mevt;
	unsigned int cpu;

	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		mevt = this_cpu_ptr(&percpu_mct_tick);
		exynos4_local_timer_setup(&mevt->evt);
		break;
	case CPU_ONLINE:
		cpu = (unsigned long)hcpu;
		if (mct_int_type == MCT_INT_SPI)
			irq_set_affinity(mct_irqs[MCT_L0_IRQ + cpu],
						cpumask_of(cpu));
		break;
	case CPU_DYING:
		mevt = this_cpu_ptr(&percpu_mct_tick);
		exynos4_local_timer_stop(&mevt->evt);
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block exynos4_mct_cpu_nb = {
	.notifier_call = exynos4_mct_cpu_notify,
};

static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
{
	int err;
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	struct clk *mct_clk, *tick_clk;

	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
				clk_get(NULL, "fin_pll");
	if (IS_ERR(tick_clk))
		panic("%s: unable to determine tick clock rate\n", __func__);
	clk_rate = clk_get_rate(tick_clk);

	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	if (IS_ERR(mct_clk))
		panic("%s: unable to retrieve mct clock instance\n", __func__);
	clk_prepare_enable(mct_clk);

	reg_base = base;
	if (!reg_base)
		panic("%s: unable to ioremap mct address space\n", __func__);

	if (mct_int_type == MCT_INT_PPI) {

		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
					 exynos4_mct_tick_isr, "MCT",
					 &percpu_mct_tick);
		WARN(err, "MCT: can't request IRQ %d (%d)\n",
		     mct_irqs[MCT_L0_IRQ], err);
	} else {
		irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
	}

	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
	if (err)
		goto out_irq;

	/* Immediately configure the timer on the boot CPU */
	exynos4_local_timer_setup(&mevt->evt);
	return;

out_irq:
	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
}

void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
{
	mct_irqs[MCT_G0_IRQ] = irq_g0;
	mct_irqs[MCT_L0_IRQ] = irq_l0;
	mct_irqs[MCT_L1_IRQ] = irq_l1;
	mct_int_type = MCT_INT_SPI;

	exynos4_timer_resources(NULL, base);
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}

static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
{
	u32 nr_irqs, i;

	mct_int_type = int_type;

	/* This driver uses only one global timer interrupt */
	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);

	/*
	 * Find out the number of local irqs specified. The local
	 * timer irqs are specified after the four global timer
	 * irqs are specified.
	 */
#ifdef CONFIG_OF
	nr_irqs = of_irq_count(np);
#else
	nr_irqs = 0;
#endif
	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
		mct_irqs[i] = irq_of_parse_and_map(np, i);

	exynos4_timer_resources(np, of_iomap(np, 0));
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}


static void __init mct_init_spi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_SPI);
}

static void __init mct_init_ppi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_PPI);
}
CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
Commit	Line	Data
30d8bead CY	1	/* linux/arch/arm/mach-exynos4/mct.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* EXYNOS4 MCT(Multi-Core Timer) support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
ee98d27d	19	#include <linux/cpu.h>
30d8bead CY	20	#include <linux/platform_device.h>
	21	#include <linux/delay.h>
	22	#include <linux/percpu.h>
2edb36c4	23	#include <linux/of.h>
36ba5d52 TA	24	#include <linux/of_irq.h>
36ba5d52 TA	25	#include <linux/of_address.h>
9fbf0c85	26	#include <linux/clocksource.h>
30d8bead	27
a1ba7a7a TA	28	#define EXYNOS4_MCTREG(x) (x)
	29	#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
	30	#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
	31	#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
	32	#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
	33	#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
	34	#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
	35	#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
	36	#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
	37	#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
	38	#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
	39	#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
	40	#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
	41	#define EXYNOS4_MCT_L_MASK (0xffffff00)
	42
	43	#define MCT_L_TCNTB_OFFSET (0x00)
	44	#define MCT_L_ICNTB_OFFSET (0x08)
	45	#define MCT_L_TCON_OFFSET (0x20)
	46	#define MCT_L_INT_CSTAT_OFFSET (0x30)
	47	#define MCT_L_INT_ENB_OFFSET (0x34)
	48	#define MCT_L_WSTAT_OFFSET (0x40)
	49	#define MCT_G_TCON_START (1 << 8)
	50	#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
	51	#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
	52	#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
	53	#define MCT_L_TCON_INT_START (1 << 1)
	54	#define MCT_L_TCON_TIMER_START (1 << 0)
	55
4d2e4d7f CY	56	#define TICK_BASE_CNT 1
4d2e4d7f CY	57
3a062281 CY	58	enum {
	59	MCT_INT_SPI,
	60	MCT_INT_PPI
	61	};
	62
c371dc60 TA	63	enum {
	64	MCT_G0_IRQ,
	65	MCT_G1_IRQ,
	66	MCT_G2_IRQ,
	67	MCT_G3_IRQ,
	68	MCT_L0_IRQ,
	69	MCT_L1_IRQ,
	70	MCT_L2_IRQ,
	71	MCT_L3_IRQ,
6c16dedf CK	72	MCT_L4_IRQ,
	73	MCT_L5_IRQ,
	74	MCT_L6_IRQ,
	75	MCT_L7_IRQ,
c371dc60 TA	76	MCT_NR_IRQS,
	77	};
	78
a1ba7a7a	79	static void __iomem *reg_base;
30d8bead	80	static unsigned long clk_rate;
3a062281	81	static unsigned int mct_int_type;
c371dc60	82	static int mct_irqs[MCT_NR_IRQS];
30d8bead CY	83
30d8bead CY	84	struct mct_clock_event_device {
ee98d27d	85	struct clock_event_device evt;
a1ba7a7a	86	unsigned long base;
c8987470	87	char name[10];
30d8bead CY	88	};
30d8bead CY	89
a1ba7a7a	90	static void exynos4_mct_write(unsigned int value, unsigned long offset)
30d8bead	91	{
a1ba7a7a	92	unsigned long stat_addr;
30d8bead CY	93	u32 mask;
	94	u32 i;
	95
a1ba7a7a	96	__raw_writel(value, reg_base + offset);
30d8bead	97
a1ba7a7a TA	98	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
	99	stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
	100	switch (offset & EXYNOS4_MCT_L_MASK) {
	101	case MCT_L_TCON_OFFSET:
c8987470 CY	102	mask = 1 << 3; /* L_TCON write status */
c8987470 CY	103	break;
a1ba7a7a	104	case MCT_L_ICNTB_OFFSET:
c8987470 CY	105	mask = 1 << 1; /* L_ICNTB write status */
c8987470 CY	106	break;
a1ba7a7a	107	case MCT_L_TCNTB_OFFSET:
c8987470 CY	108	mask = 1 << 0; /* L_TCNTB write status */
	109	break;
	110	default:
	111	return;
	112	}
	113	} else {
a1ba7a7a TA	114	switch (offset) {
a1ba7a7a TA	115	case EXYNOS4_MCT_G_TCON:
c8987470 CY	116	stat_addr = EXYNOS4_MCT_G_WSTAT;
	117	mask = 1 << 16; /* G_TCON write status */
	118	break;
a1ba7a7a	119	case EXYNOS4_MCT_G_COMP0_L:
c8987470 CY	120	stat_addr = EXYNOS4_MCT_G_WSTAT;
	121	mask = 1 << 0; /* G_COMP0_L write status */
	122	break;
a1ba7a7a	123	case EXYNOS4_MCT_G_COMP0_U:
c8987470 CY	124	stat_addr = EXYNOS4_MCT_G_WSTAT;
	125	mask = 1 << 1; /* G_COMP0_U write status */
	126	break;
a1ba7a7a	127	case EXYNOS4_MCT_G_COMP0_ADD_INCR:
c8987470 CY	128	stat_addr = EXYNOS4_MCT_G_WSTAT;
	129	mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
	130	break;
a1ba7a7a	131	case EXYNOS4_MCT_G_CNT_L:
c8987470 CY	132	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	133	mask = 1 << 0; /* G_CNT_L write status */
	134	break;
a1ba7a7a	135	case EXYNOS4_MCT_G_CNT_U:
c8987470 CY	136	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	137	mask = 1 << 1; /* G_CNT_U write status */
	138	break;
	139	default:
	140	return;
	141	}
30d8bead CY	142	}
	143
	144	/* Wait maximum 1 ms until written values are applied */
	145	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
a1ba7a7a TA	146	if (__raw_readl(reg_base + stat_addr) & mask) {
a1ba7a7a TA	147	__raw_writel(mask, reg_base + stat_addr);
30d8bead CY	148	return;
	149	}
	150
a1ba7a7a	151	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
30d8bead CY	152	}
	153
	154	/* Clocksource handling */
	155	static void exynos4_mct_frc_start(u32 hi, u32 lo)
	156	{
	157	u32 reg;
	158
	159	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	160	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
	161
a1ba7a7a	162	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	163	reg \|= MCT_G_TCON_START;
	164	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
	165	}
	166
	167	static cycle_t exynos4_frc_read(struct clocksource *cs)
	168	{
	169	unsigned int lo, hi;
a1ba7a7a	170	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	171
	172	do {
	173	hi = hi2;
a1ba7a7a TA	174	lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
a1ba7a7a TA	175	hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	176	} while (hi != hi2);
	177
	178	return ((cycle_t)hi << 32) \| lo;
	179	}
	180
aa421c13 CY	181	static void exynos4_frc_resume(struct clocksource *cs)
	182	{
	183	exynos4_mct_frc_start(0, 0);
	184	}
	185
30d8bead CY	186	struct clocksource mct_frc = {
	187	.name = "mct-frc",
	188	.rating = 400,
	189	.read = exynos4_frc_read,
	190	.mask = CLOCKSOURCE_MASK(64),
	191	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
aa421c13	192	.resume = exynos4_frc_resume,
30d8bead CY	193	};
	194
	195	static void __init exynos4_clocksource_init(void)
	196	{
	197	exynos4_mct_frc_start(0, 0);
	198
	199	if (clocksource_register_hz(&mct_frc, clk_rate))
	200	panic("%s: can't register clocksource\n", mct_frc.name);
	201	}
	202
	203	static void exynos4_mct_comp0_stop(void)
	204	{
	205	unsigned int tcon;
	206
a1ba7a7a	207	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	208	tcon &= ~(MCT_G_TCON_COMP0_ENABLE \| MCT_G_TCON_COMP0_AUTO_INC);
	209
	210	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	211	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
	212	}
	213
	214	static void exynos4_mct_comp0_start(enum clock_event_mode mode,
	215	unsigned long cycles)
	216	{
	217	unsigned int tcon;
	218	cycle_t comp_cycle;
	219
a1ba7a7a	220	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	221
	222	if (mode == CLOCK_EVT_MODE_PERIODIC) {
	223	tcon \|= MCT_G_TCON_COMP0_AUTO_INC;
	224	exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	225	}
	226
	227	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	228	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	229	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
	230
	231	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
	232
	233	tcon \|= MCT_G_TCON_COMP0_ENABLE;
	234	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
	235	}
	236
	237	static int exynos4_comp_set_next_event(unsigned long cycles,
	238	struct clock_event_device *evt)
	239	{
	240	exynos4_mct_comp0_start(evt->mode, cycles);
	241
	242	return 0;
	243	}
	244
	245	static void exynos4_comp_set_mode(enum clock_event_mode mode,
	246	struct clock_event_device *evt)
	247	{
4d2e4d7f	248	unsigned long cycles_per_jiffy;
30d8bead CY	249	exynos4_mct_comp0_stop();
	250
	251	switch (mode) {
	252	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	253	cycles_per_jiffy =
	254	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	255	exynos4_mct_comp0_start(mode, cycles_per_jiffy);
30d8bead CY	256	break;
	257
	258	case CLOCK_EVT_MODE_ONESHOT:
	259	case CLOCK_EVT_MODE_UNUSED:
	260	case CLOCK_EVT_MODE_SHUTDOWN:
	261	case CLOCK_EVT_MODE_RESUME:
	262	break;
	263	}
	264	}
	265
	266	static struct clock_event_device mct_comp_device = {
	267	.name = "mct-comp",
	268	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	269	.rating = 250,
	270	.set_next_event = exynos4_comp_set_next_event,
	271	.set_mode = exynos4_comp_set_mode,
	272	};
	273
	274	static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
	275	{
	276	struct clock_event_device *evt = dev_id;
	277
	278	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
	279
	280	evt->event_handler(evt);
	281
	282	return IRQ_HANDLED;
	283	}
	284
	285	static struct irqaction mct_comp_event_irq = {
	286	.name = "mct_comp_irq",
	287	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	288	.handler = exynos4_mct_comp_isr,
	289	.dev_id = &mct_comp_device,
	290	};
	291
	292	static void exynos4_clockevent_init(void)
	293	{
30d8bead	294	mct_comp_device.cpumask = cpumask_of(0);
838a2ae8 SG	295	clockevents_config_and_register(&mct_comp_device, clk_rate,
838a2ae8 SG	296	0xf, 0xffffffff);
c371dc60	297	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
30d8bead CY	298	}
30d8bead CY	299
991a6c7d KK	300	static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
991a6c7d KK	301
30d8bead CY	302	/* Clock event handling */
	303	static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
	304	{
	305	unsigned long tmp;
	306	unsigned long mask = MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START;
a1ba7a7a	307	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
30d8bead	308
a1ba7a7a	309	tmp = __raw_readl(reg_base + offset);
30d8bead CY	310	if (tmp & mask) {
30d8bead CY	311	tmp &= ~mask;
a1ba7a7a	312	exynos4_mct_write(tmp, offset);
30d8bead CY	313	}
	314	}
	315
	316	static void exynos4_mct_tick_start(unsigned long cycles,
	317	struct mct_clock_event_device *mevt)
	318	{
	319	unsigned long tmp;
	320
	321	exynos4_mct_tick_stop(mevt);
	322
	323	tmp = (1 << 31) \| cycles; /* MCT_L_UPDATE_ICNTB */
	324
	325	/* update interrupt count buffer */
	326	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
	327
25985edc	328	/* enable MCT tick interrupt */
30d8bead CY	329	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
30d8bead CY	330
a1ba7a7a	331	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
30d8bead CY	332	tmp \|= MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START \|
	333	MCT_L_TCON_INTERVAL_MODE;
	334	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
	335	}
	336
	337	static int exynos4_tick_set_next_event(unsigned long cycles,
	338	struct clock_event_device *evt)
	339	{
e700e41d	340	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
30d8bead CY	341
	342	exynos4_mct_tick_start(cycles, mevt);
	343
	344	return 0;
	345	}
	346
	347	static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
	348	struct clock_event_device *evt)
	349	{
e700e41d	350	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
4d2e4d7f	351	unsigned long cycles_per_jiffy;
30d8bead CY	352
	353	exynos4_mct_tick_stop(mevt);
	354
	355	switch (mode) {
	356	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	357	cycles_per_jiffy =
	358	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	359	exynos4_mct_tick_start(cycles_per_jiffy, mevt);
30d8bead CY	360	break;
	361
	362	case CLOCK_EVT_MODE_ONESHOT:
	363	case CLOCK_EVT_MODE_UNUSED:
	364	case CLOCK_EVT_MODE_SHUTDOWN:
	365	case CLOCK_EVT_MODE_RESUME:
	366	break;
	367	}
	368	}
	369
c8987470	370	static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
30d8bead	371	{
ee98d27d	372	struct clock_event_device *evt = &mevt->evt;
30d8bead CY	373
	374	/*
	375	* This is for supporting oneshot mode.
	376	* Mct would generate interrupt periodically
	377	* without explicit stopping.
	378	*/
	379	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
	380	exynos4_mct_tick_stop(mevt);
	381
	382	/* Clear the MCT tick interrupt */
a1ba7a7a	383	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
3a062281 CY	384	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
	385	return 1;
	386	} else {
	387	return 0;
	388	}
	389	}
	390
	391	static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
	392	{
	393	struct mct_clock_event_device *mevt = dev_id;
ee98d27d	394	struct clock_event_device *evt = &mevt->evt;
3a062281 CY	395
3a062281 CY	396	exynos4_mct_tick_clear(mevt);
30d8bead CY	397
	398	evt->event_handler(evt);
	399
	400	return IRQ_HANDLED;
	401	}
	402
8c37bb3a	403	static int exynos4_local_timer_setup(struct clock_event_device *evt)
30d8bead	404	{
e700e41d	405	struct mct_clock_event_device *mevt;
30d8bead CY	406	unsigned int cpu = smp_processor_id();
30d8bead CY	407
ee98d27d	408	mevt = container_of(evt, struct mct_clock_event_device, evt);
30d8bead	409
e700e41d	410	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
09e15176	411	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
30d8bead	412
e700e41d	413	evt->name = mevt->name;
30d8bead CY	414	evt->cpumask = cpumask_of(cpu);
	415	evt->set_next_event = exynos4_tick_set_next_event;
	416	evt->set_mode = exynos4_tick_set_mode;
	417	evt->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	418	evt->rating = 450;
838a2ae8 SG	419	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
838a2ae8 SG	420	0xf, 0x7fffffff);
30d8bead	421
4d2e4d7f	422	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
30d8bead	423
3a062281	424	if (mct_int_type == MCT_INT_SPI) {
7114cd74 CK	425	evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
	426	if (request_irq(evt->irq, exynos4_mct_tick_isr,
	427	IRQF_TIMER \| IRQF_NOBALANCING,
	428	evt->name, mevt)) {
	429	pr_err("exynos-mct: cannot register IRQ %d\n",
	430	evt->irq);
	431	return -EIO;
3a062281	432	}
30d8bead	433	} else {
c371dc60	434	enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
30d8bead	435	}
4d487d7e KK	436
4d487d7e KK	437	return 0;
30d8bead CY	438	}
30d8bead CY	439
a8cb6041	440	static void exynos4_local_timer_stop(struct clock_event_device *evt)
30d8bead	441	{
28af690a	442	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
e700e41d	443	if (mct_int_type == MCT_INT_SPI)
7114cd74	444	free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
e700e41d	445	else
c371dc60	446	disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
30d8bead	447	}
a8cb6041	448
47dcd356	449	static int exynos4_mct_cpu_notify(struct notifier_block *self,
ee98d27d SB	450	unsigned long action, void *hcpu)
	451	{
	452	struct mct_clock_event_device *mevt;
5df718d8	453	unsigned int cpu;
ee98d27d SB	454
	455	/*
	456	* Grab cpu pointer in each case to avoid spurious
	457	* preemptible warnings
	458	*/
	459	switch (action & ~CPU_TASKS_FROZEN) {
	460	case CPU_STARTING:
	461	mevt = this_cpu_ptr(&percpu_mct_tick);
	462	exynos4_local_timer_setup(&mevt->evt);
	463	break;
5df718d8 TF	464	case CPU_ONLINE:
	465	cpu = (unsigned long)hcpu;
	466	if (mct_int_type == MCT_INT_SPI)
	467	irq_set_affinity(mct_irqs[MCT_L0_IRQ + cpu],
	468	cpumask_of(cpu));
	469	break;
ee98d27d SB	470	case CPU_DYING:
	471	mevt = this_cpu_ptr(&percpu_mct_tick);
	472	exynos4_local_timer_stop(&mevt->evt);
	473	break;
	474	}
	475
	476	return NOTIFY_OK;
	477	}
	478
47dcd356	479	static struct notifier_block exynos4_mct_cpu_nb = {
ee98d27d	480	.notifier_call = exynos4_mct_cpu_notify,
a8cb6041	481	};
30d8bead	482
19ce4f4a	483	static void __init exynos4_timer_resources(struct device_node np, void __iomem base)
30d8bead	484	{
ee98d27d SB	485	int err;
ee98d27d SB	486	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
ca9048ec	487	struct clk mct_clk, tick_clk;
30d8bead	488
415ac2e2 TA	489	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
	490	clk_get(NULL, "fin_pll");
	491	if (IS_ERR(tick_clk))
	492	panic("%s: unable to determine tick clock rate\n", __func__);
	493	clk_rate = clk_get_rate(tick_clk);
e700e41d	494
ca9048ec TA	495	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	496	if (IS_ERR(mct_clk))
	497	panic("%s: unable to retrieve mct clock instance\n", __func__);
	498	clk_prepare_enable(mct_clk);
e700e41d	499
228e3023	500	reg_base = base;
36ba5d52 TA	501	if (!reg_base)
36ba5d52 TA	502	panic("%s: unable to ioremap mct address space\n", __func__);
a1ba7a7a	503
e700e41d	504	if (mct_int_type == MCT_INT_PPI) {
e700e41d	505
c371dc60	506	err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
e700e41d MZ	507	exynos4_mct_tick_isr, "MCT",
	508	&percpu_mct_tick);
	509	WARN(err, "MCT: can't request IRQ %d (%d)\n",
c371dc60	510	mct_irqs[MCT_L0_IRQ], err);
5df718d8 TF	511	} else {
5df718d8 TF	512	irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
e700e41d	513	}
a8cb6041	514
ee98d27d SB	515	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
	516	if (err)
	517	goto out_irq;
	518
	519	/* Immediately configure the timer on the boot CPU */
	520	exynos4_local_timer_setup(&mevt->evt);
	521	return;
	522
	523	out_irq:
	524	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
30d8bead CY	525	}
30d8bead CY	526
034c097c	527	void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
30d8bead	528	{
034c097c AB	529	mct_irqs[MCT_G0_IRQ] = irq_g0;
	530	mct_irqs[MCT_L0_IRQ] = irq_l0;
	531	mct_irqs[MCT_L1_IRQ] = irq_l1;
	532	mct_int_type = MCT_INT_SPI;
2edb36c4	533
034c097c	534	exynos4_timer_resources(NULL, base);
30d8bead CY	535	exynos4_clocksource_init();
	536	exynos4_clockevent_init();
	537	}
3a062281	538
228e3023 AB	539	static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
	540	{
	541	u32 nr_irqs, i;
	542
	543	mct_int_type = int_type;
	544
	545	/* This driver uses only one global timer interrupt */
	546	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
	547
	548	/*
	549	* Find out the number of local irqs specified. The local
	550	* timer irqs are specified after the four global timer
	551	* irqs are specified.
	552	*/
f4636d0a	553	#ifdef CONFIG_OF
228e3023	554	nr_irqs = of_irq_count(np);
f4636d0a AB	555	#else
	556	nr_irqs = 0;
	557	#endif
228e3023 AB	558	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
	559	mct_irqs[i] = irq_of_parse_and_map(np, i);
	560
19ce4f4a	561	exynos4_timer_resources(np, of_iomap(np, 0));
30d8bead CY	562	exynos4_clocksource_init();
	563	exynos4_clockevent_init();
	564	}
228e3023 AB	565
	566
	567	static void __init mct_init_spi(struct device_node *np)
	568	{
	569	return mct_init_dt(np, MCT_INT_SPI);
	570	}
	571
	572	static void __init mct_init_ppi(struct device_node *np)
	573	{
	574	return mct_init_dt(np, MCT_INT_PPI);
	575	}
	576	CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
	577	CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);