[deliverable/linux.git] / drivers / clocksource / mips-gic-timer.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irqchip/mips-gic.h>
#include <linux/notifier.h>
#include <linux/of_irq.h>
#include <linux/percpu.h>
#include <linux/smp.h>
#include <linux/time.h>

static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
static int gic_timer_irq;
static unsigned int gic_frequency;

static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
{
	u64 cnt;
	int res;

	cnt = gic_read_count();
	cnt += (u64)delta;
	gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
	res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
	return res;
}

static void gic_set_clock_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	/* Nothing to do ...  */
}

static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *cd = dev_id;

	gic_write_compare(gic_read_compare());
	cd->event_handler(cd);
	return IRQ_HANDLED;
}

struct irqaction gic_compare_irqaction = {
	.handler = gic_compare_interrupt,
	.percpu_dev_id = &gic_clockevent_device,
	.flags = IRQF_PERCPU | IRQF_TIMER,
	.name = "timer",
};

static void gic_clockevent_cpu_init(struct clock_event_device *cd)
{
	unsigned int cpu = smp_processor_id();

	cd->name		= "MIPS GIC";
	cd->features		= CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_C3STOP;

	cd->rating		= 350;
	cd->irq			= gic_timer_irq;
	cd->cpumask		= cpumask_of(cpu);
	cd->set_next_event	= gic_next_event;
	cd->set_mode		= gic_set_clock_mode;

	clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);

	enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
}

static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
{
	disable_percpu_irq(gic_timer_irq);
}

static int gic_cpu_notifier(struct notifier_block *nb, unsigned long action,
				void *data)
{
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
		break;
	case CPU_DYING:
		gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block gic_cpu_nb = {
	.notifier_call = gic_cpu_notifier,
};

static int gic_clockevent_init(void)
{
	if (!cpu_has_counter || !gic_frequency)
		return -ENXIO;

	setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);

	register_cpu_notifier(&gic_cpu_nb);

	gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));

	return 0;
}

static cycle_t gic_hpt_read(struct clocksource *cs)
{
	return gic_read_count();
}

static struct clocksource gic_clocksource = {
	.name	= "GIC",
	.read	= gic_hpt_read,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void __init __gic_clocksource_init(void)
{
	/* Set clocksource mask. */
	gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());

	/* Calculate a somewhat reasonable rating value. */
	gic_clocksource.rating = 200 + gic_frequency / 10000000;

	clocksource_register_hz(&gic_clocksource, gic_frequency);

	gic_clockevent_init();

	/* And finally start the counter */
	gic_start_count();
}

void __init gic_clocksource_init(unsigned int frequency)
{
	gic_frequency = frequency;
	gic_timer_irq = MIPS_GIC_IRQ_BASE +
		GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);

	__gic_clocksource_init();
}

static void __init gic_clocksource_of_init(struct device_node *node)
{
	struct clk *clk;

	if (WARN_ON(!gic_present || !node->parent ||
		    !of_device_is_compatible(node->parent, "mti,gic")))
		return;

	clk = of_clk_get(node, 0);
	if (!IS_ERR(clk)) {
		gic_frequency = clk_get_rate(clk);
		clk_put(clk);
	} else if (of_property_read_u32(node, "clock-frequency",
					&gic_frequency)) {
		pr_err("GIC frequency not specified.\n");
		return;
	}
	gic_timer_irq = irq_of_parse_and_map(node, 0);
	if (!gic_timer_irq) {
		pr_err("GIC timer IRQ not specified.\n");
		return;
	}

	__gic_clocksource_init();
}
CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
		       gic_clocksource_of_init);
Commit	Line	Data
778eeb1b SH	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
	7	*/
5b4e8453	8	#include <linux/clk.h>
a331ce63	9	#include <linux/clockchips.h>
e4752dbb	10	#include <linux/cpu.h>
778eeb1b	11	#include <linux/init.h>
a331ce63	12	#include <linux/interrupt.h>
4060bbe9	13	#include <linux/irqchip/mips-gic.h>
e4752dbb	14	#include <linux/notifier.h>
e12aa828	15	#include <linux/of_irq.h>
a331ce63 AB	16	#include <linux/percpu.h>
a331ce63 AB	17	#include <linux/smp.h>
dfa762e1	18	#include <linux/time.h>
778eeb1b	19
5fee56e0	20	static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
e4752dbb	21	static int gic_timer_irq;
b0854514	22	static unsigned int gic_frequency;
a331ce63 AB	23
	24	static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
	25	{
	26	u64 cnt;
	27	int res;
	28
	29	cnt = gic_read_count();
	30	cnt += (u64)delta;
	31	gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
	32	res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
	33	return res;
	34	}
	35
5fee56e0	36	static void gic_set_clock_mode(enum clock_event_mode mode,
a331ce63 AB	37	struct clock_event_device *evt)
	38	{
	39	/* Nothing to do ... */
	40	}
	41
5fee56e0	42	static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
a331ce63	43	{
f7ea3060	44	struct clock_event_device *cd = dev_id;
a331ce63 AB	45
a331ce63 AB	46	gic_write_compare(gic_read_compare());
a331ce63 AB	47	cd->event_handler(cd);
	48	return IRQ_HANDLED;
	49	}
	50
	51	struct irqaction gic_compare_irqaction = {
	52	.handler = gic_compare_interrupt,
f7ea3060	53	.percpu_dev_id = &gic_clockevent_device,
a331ce63 AB	54	.flags = IRQF_PERCPU \| IRQF_TIMER,
	55	.name = "timer",
	56	};
	57
e4752dbb	58	static void gic_clockevent_cpu_init(struct clock_event_device *cd)
a331ce63 AB	59	{
a331ce63 AB	60	unsigned int cpu = smp_processor_id();
a331ce63 AB	61
	62	cd->name = "MIPS GIC";
	63	cd->features = CLOCK_EVT_FEAT_ONESHOT \|
	64	CLOCK_EVT_FEAT_C3STOP;
	65
a45da565	66	cd->rating = 350;
e4752dbb	67	cd->irq = gic_timer_irq;
a331ce63 AB	68	cd->cpumask = cpumask_of(cpu);
	69	cd->set_next_event = gic_next_event;
	70	cd->set_mode = gic_set_clock_mode;
a331ce63	71
b695d8e6	72	clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
a331ce63	73
e4752dbb AB	74	enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
	75	}
	76
	77	static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
	78	{
	79	disable_percpu_irq(gic_timer_irq);
	80	}
	81
	82	static int gic_cpu_notifier(struct notifier_block *nb, unsigned long action,
	83	void *data)
	84	{
	85	switch (action & ~CPU_TASKS_FROZEN) {
	86	case CPU_STARTING:
	87	gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
	88	break;
	89	case CPU_DYING:
	90	gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
	91	break;
a331ce63 AB	92	}
a331ce63 AB	93
e4752dbb AB	94	return NOTIFY_OK;
	95	}
	96
	97	static struct notifier_block gic_cpu_nb = {
	98	.notifier_call = gic_cpu_notifier,
	99	};
	100
	101	static int gic_clockevent_init(void)
	102	{
	103	if (!cpu_has_counter \|\| !gic_frequency)
	104	return -ENXIO;
	105
e4752dbb AB	106	setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
	107
	108	register_cpu_notifier(&gic_cpu_nb);
	109
	110	gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
a331ce63 AB	111
	112	return 0;
	113	}
	114
778eeb1b SH	115	static cycle_t gic_hpt_read(struct clocksource *cs)
778eeb1b SH	116	{
dfa762e1	117	return gic_read_count();
778eeb1b SH	118	}
	119
	120	static struct clocksource gic_clocksource = {
	121	.name = "GIC",
	122	.read = gic_hpt_read,
	123	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	124	};
	125
e12aa828	126	static void __init __gic_clocksource_init(void)
778eeb1b	127	{
778eeb1b	128	/* Set clocksource mask. */
387904ff	129	gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
778eeb1b SH	130
778eeb1b SH	131	/* Calculate a somewhat reasonable rating value. */
e12aa828	132	gic_clocksource.rating = 200 + gic_frequency / 10000000;
778eeb1b	133
e12aa828	134	clocksource_register_hz(&gic_clocksource, gic_frequency);
e4752dbb AB	135
e4752dbb AB	136	gic_clockevent_init();
7d9cd1f5 MC	137
	138	/* And finally start the counter */
	139	gic_start_count();
778eeb1b	140	}
e12aa828 AB	141
	142	void __init gic_clocksource_init(unsigned int frequency)
	143	{
	144	gic_frequency = frequency;
	145	gic_timer_irq = MIPS_GIC_IRQ_BASE +
	146	GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
	147
	148	__gic_clocksource_init();
	149	}
	150
	151	static void __init gic_clocksource_of_init(struct device_node *node)
	152	{
5b4e8453 AB	153	struct clk *clk;
5b4e8453 AB	154
e12aa828 AB	155	if (WARN_ON(!gic_present \|\| !node->parent \|\|
	156	!of_device_is_compatible(node->parent, "mti,gic")))
	157	return;
	158
5b4e8453 AB	159	clk = of_clk_get(node, 0);
	160	if (!IS_ERR(clk)) {
	161	gic_frequency = clk_get_rate(clk);
	162	clk_put(clk);
	163	} else if (of_property_read_u32(node, "clock-frequency",
	164	&gic_frequency)) {
e12aa828 AB	165	pr_err("GIC frequency not specified.\n");
	166	return;
	167	}
	168	gic_timer_irq = irq_of_parse_and_map(node, 0);
	169	if (!gic_timer_irq) {
	170	pr_err("GIC timer IRQ not specified.\n");
	171	return;
	172	}
	173
	174	__gic_clocksource_init();
	175	}
	176	CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
	177	gic_clocksource_of_init);