Commit | Line | Data |
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07862c1c JJ |
1 | /* |
2 | * MOXA ART SoCs timer handling. | |
3 | * | |
4 | * Copyright (C) 2013 Jonas Jensen | |
5 | * | |
6 | * Jonas Jensen <jonas.jensen@gmail.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/clockchips.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/irq.h> | |
17 | #include <linux/irqreturn.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <linux/of_irq.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/clocksource.h> | |
adf157eb | 23 | #include <linux/bitops.h> |
07862c1c JJ |
24 | |
25 | #define TIMER1_BASE 0x00 | |
26 | #define TIMER2_BASE 0x10 | |
27 | #define TIMER3_BASE 0x20 | |
28 | ||
29 | #define REG_COUNT 0x0 /* writable */ | |
30 | #define REG_LOAD 0x4 | |
31 | #define REG_MATCH1 0x8 | |
32 | #define REG_MATCH2 0xC | |
33 | ||
34 | #define TIMER_CR 0x30 | |
35 | #define TIMER_INTR_STATE 0x34 | |
36 | #define TIMER_INTR_MASK 0x38 | |
37 | ||
38 | /* | |
39 | * TIMER_CR flags: | |
40 | * | |
41 | * TIMEREG_CR_*_CLOCK 0: PCLK, 1: EXT1CLK | |
42 | * TIMEREG_CR_*_INT overflow interrupt enable bit | |
43 | */ | |
44 | #define TIMEREG_CR_1_ENABLE BIT(0) | |
45 | #define TIMEREG_CR_1_CLOCK BIT(1) | |
46 | #define TIMEREG_CR_1_INT BIT(2) | |
47 | #define TIMEREG_CR_2_ENABLE BIT(3) | |
48 | #define TIMEREG_CR_2_CLOCK BIT(4) | |
49 | #define TIMEREG_CR_2_INT BIT(5) | |
50 | #define TIMEREG_CR_3_ENABLE BIT(6) | |
51 | #define TIMEREG_CR_3_CLOCK BIT(7) | |
52 | #define TIMEREG_CR_3_INT BIT(8) | |
53 | #define TIMEREG_CR_COUNT_UP BIT(9) | |
54 | ||
55 | #define TIMER1_ENABLE (TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE) | |
56 | #define TIMER1_DISABLE (TIMEREG_CR_2_ENABLE) | |
57 | ||
58 | static void __iomem *base; | |
59 | static unsigned int clock_count_per_tick; | |
60 | ||
37ae2471 | 61 | static int moxart_shutdown(struct clock_event_device *evt) |
07862c1c | 62 | { |
37ae2471 VK |
63 | writel(TIMER1_DISABLE, base + TIMER_CR); |
64 | return 0; | |
65 | } | |
66 | ||
67 | static int moxart_set_oneshot(struct clock_event_device *evt) | |
68 | { | |
69 | writel(TIMER1_DISABLE, base + TIMER_CR); | |
70 | writel(~0, base + TIMER1_BASE + REG_LOAD); | |
71 | return 0; | |
72 | } | |
73 | ||
74 | static int moxart_set_periodic(struct clock_event_device *evt) | |
75 | { | |
76 | writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); | |
77 | writel(TIMER1_ENABLE, base + TIMER_CR); | |
78 | return 0; | |
07862c1c JJ |
79 | } |
80 | ||
81 | static int moxart_clkevt_next_event(unsigned long cycles, | |
82 | struct clock_event_device *unused) | |
83 | { | |
84 | u32 u; | |
85 | ||
86 | writel(TIMER1_DISABLE, base + TIMER_CR); | |
87 | ||
88 | u = readl(base + TIMER1_BASE + REG_COUNT) - cycles; | |
89 | writel(u, base + TIMER1_BASE + REG_MATCH1); | |
90 | ||
91 | writel(TIMER1_ENABLE, base + TIMER_CR); | |
92 | ||
93 | return 0; | |
94 | } | |
95 | ||
96 | static struct clock_event_device moxart_clockevent = { | |
37ae2471 VK |
97 | .name = "moxart_timer", |
98 | .rating = 200, | |
99 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
100 | CLOCK_EVT_FEAT_ONESHOT, | |
101 | .set_state_shutdown = moxart_shutdown, | |
102 | .set_state_periodic = moxart_set_periodic, | |
103 | .set_state_oneshot = moxart_set_oneshot, | |
104 | .tick_resume = moxart_set_oneshot, | |
105 | .set_next_event = moxart_clkevt_next_event, | |
07862c1c JJ |
106 | }; |
107 | ||
108 | static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id) | |
109 | { | |
110 | struct clock_event_device *evt = dev_id; | |
111 | evt->event_handler(evt); | |
112 | return IRQ_HANDLED; | |
113 | } | |
114 | ||
115 | static struct irqaction moxart_timer_irq = { | |
116 | .name = "moxart-timer", | |
117 | .flags = IRQF_TIMER, | |
118 | .handler = moxart_timer_interrupt, | |
119 | .dev_id = &moxart_clockevent, | |
120 | }; | |
121 | ||
122 | static void __init moxart_timer_init(struct device_node *node) | |
123 | { | |
124 | int ret, irq; | |
125 | unsigned long pclk; | |
126 | struct clk *clk; | |
127 | ||
128 | base = of_iomap(node, 0); | |
129 | if (!base) | |
130 | panic("%s: of_iomap failed\n", node->full_name); | |
131 | ||
132 | irq = irq_of_parse_and_map(node, 0); | |
133 | if (irq <= 0) | |
134 | panic("%s: irq_of_parse_and_map failed\n", node->full_name); | |
135 | ||
136 | ret = setup_irq(irq, &moxart_timer_irq); | |
137 | if (ret) | |
138 | panic("%s: setup_irq failed\n", node->full_name); | |
139 | ||
140 | clk = of_clk_get(node, 0); | |
141 | if (IS_ERR(clk)) | |
142 | panic("%s: of_clk_get failed\n", node->full_name); | |
143 | ||
144 | pclk = clk_get_rate(clk); | |
145 | ||
146 | if (clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT, | |
147 | "moxart_timer", pclk, 200, 32, | |
148 | clocksource_mmio_readl_down)) | |
149 | panic("%s: clocksource_mmio_init failed\n", node->full_name); | |
150 | ||
151 | clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ); | |
152 | ||
153 | writel(~0, base + TIMER2_BASE + REG_LOAD); | |
154 | writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); | |
155 | ||
156 | moxart_clockevent.cpumask = cpumask_of(0); | |
157 | moxart_clockevent.irq = irq; | |
158 | ||
159 | /* | |
160 | * documentation is not publicly available: | |
161 | * min_delta / max_delta obtained by trial-and-error, | |
162 | * max_delta 0xfffffffe should be ok because count | |
163 | * register size is u32 | |
164 | */ | |
165 | clockevents_config_and_register(&moxart_clockevent, pclk, | |
166 | 0x4, 0xfffffffe); | |
167 | } | |
168 | CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init); |