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f1189989 TF |
1 | /* |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com/ | |
4 | * | |
5 | * samsung - Common hr-timer support (s3c and s5p) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/interrupt.h> | |
13 | #include <linux/irq.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/clockchips.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_irq.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/slab.h> | |
38ff87f7 | 24 | #include <linux/sched_clock.h> |
f1189989 TF |
25 | |
26 | #include <clocksource/samsung_pwm.h> | |
27 | ||
f1189989 TF |
28 | |
29 | /* | |
30 | * Clocksource driver | |
31 | */ | |
32 | ||
33 | #define REG_TCFG0 0x00 | |
34 | #define REG_TCFG1 0x04 | |
35 | #define REG_TCON 0x08 | |
36 | #define REG_TINT_CSTAT 0x44 | |
37 | ||
38 | #define REG_TCNTB(chan) (0x0c + 12 * (chan)) | |
39 | #define REG_TCMPB(chan) (0x10 + 12 * (chan)) | |
40 | ||
41 | #define TCFG0_PRESCALER_MASK 0xff | |
42 | #define TCFG0_PRESCALER1_SHIFT 8 | |
43 | ||
44 | #define TCFG1_SHIFT(x) ((x) * 4) | |
45 | #define TCFG1_MUX_MASK 0xf | |
46 | ||
ceea1241 TF |
47 | /* |
48 | * Each channel occupies 4 bits in TCON register, but there is a gap of 4 | |
49 | * bits (one channel) after channel 0, so channels have different numbering | |
50 | * when accessing TCON register. | |
51 | * | |
52 | * In addition, the location of autoreload bit for channel 4 (TCON channel 5) | |
53 | * in its set of bits is 2 as opposed to 3 for other channels. | |
54 | */ | |
f1189989 TF |
55 | #define TCON_START(chan) (1 << (4 * (chan) + 0)) |
56 | #define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1)) | |
57 | #define TCON_INVERT(chan) (1 << (4 * (chan) + 2)) | |
ceea1241 TF |
58 | #define _TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3)) |
59 | #define _TCON_AUTORELOAD4(chan) (1 << (4 * (chan) + 2)) | |
60 | #define TCON_AUTORELOAD(chan) \ | |
61 | ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan)) | |
f1189989 | 62 | |
7aac482e TF |
63 | DEFINE_SPINLOCK(samsung_pwm_lock); |
64 | EXPORT_SYMBOL(samsung_pwm_lock); | |
65 | ||
030c2a1e TF |
66 | struct samsung_pwm_clocksource { |
67 | void __iomem *base; | |
61d7e205 | 68 | void __iomem *source_reg; |
030c2a1e TF |
69 | unsigned int irq[SAMSUNG_PWM_NUM]; |
70 | struct samsung_pwm_variant variant; | |
71 | ||
72 | struct clk *timerclk; | |
73 | ||
f1189989 TF |
74 | unsigned int event_id; |
75 | unsigned int source_id; | |
76 | unsigned int tcnt_max; | |
77 | unsigned int tscaler_div; | |
78 | unsigned int tdiv; | |
030c2a1e TF |
79 | |
80 | unsigned long clock_count_per_tick; | |
f1189989 TF |
81 | }; |
82 | ||
030c2a1e | 83 | static struct samsung_pwm_clocksource pwm; |
f1189989 | 84 | |
030c2a1e | 85 | static void samsung_timer_set_prescale(unsigned int channel, u16 prescale) |
f1189989 TF |
86 | { |
87 | unsigned long flags; | |
88 | u8 shift = 0; | |
89 | u32 reg; | |
90 | ||
91 | if (channel >= 2) | |
92 | shift = TCFG0_PRESCALER1_SHIFT; | |
93 | ||
7aac482e | 94 | spin_lock_irqsave(&samsung_pwm_lock, flags); |
f1189989 | 95 | |
030c2a1e | 96 | reg = readl(pwm.base + REG_TCFG0); |
f1189989 TF |
97 | reg &= ~(TCFG0_PRESCALER_MASK << shift); |
98 | reg |= (prescale - 1) << shift; | |
030c2a1e | 99 | writel(reg, pwm.base + REG_TCFG0); |
f1189989 | 100 | |
7aac482e | 101 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
f1189989 TF |
102 | } |
103 | ||
030c2a1e | 104 | static void samsung_timer_set_divisor(unsigned int channel, u8 divisor) |
f1189989 TF |
105 | { |
106 | u8 shift = TCFG1_SHIFT(channel); | |
107 | unsigned long flags; | |
108 | u32 reg; | |
109 | u8 bits; | |
110 | ||
030c2a1e | 111 | bits = (fls(divisor) - 1) - pwm.variant.div_base; |
f1189989 | 112 | |
7aac482e | 113 | spin_lock_irqsave(&samsung_pwm_lock, flags); |
f1189989 | 114 | |
030c2a1e | 115 | reg = readl(pwm.base + REG_TCFG1); |
f1189989 TF |
116 | reg &= ~(TCFG1_MUX_MASK << shift); |
117 | reg |= bits << shift; | |
030c2a1e | 118 | writel(reg, pwm.base + REG_TCFG1); |
f1189989 | 119 | |
7aac482e | 120 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
f1189989 TF |
121 | } |
122 | ||
123 | static void samsung_time_stop(unsigned int channel) | |
124 | { | |
125 | unsigned long tcon; | |
126 | unsigned long flags; | |
127 | ||
128 | if (channel > 0) | |
129 | ++channel; | |
130 | ||
7aac482e | 131 | spin_lock_irqsave(&samsung_pwm_lock, flags); |
f1189989 | 132 | |
030c2a1e | 133 | tcon = __raw_readl(pwm.base + REG_TCON); |
f1189989 | 134 | tcon &= ~TCON_START(channel); |
030c2a1e | 135 | __raw_writel(tcon, pwm.base + REG_TCON); |
f1189989 | 136 | |
7aac482e | 137 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
f1189989 TF |
138 | } |
139 | ||
140 | static void samsung_time_setup(unsigned int channel, unsigned long tcnt) | |
141 | { | |
142 | unsigned long tcon; | |
143 | unsigned long flags; | |
144 | unsigned int tcon_chan = channel; | |
145 | ||
146 | if (tcon_chan > 0) | |
147 | ++tcon_chan; | |
148 | ||
7aac482e | 149 | spin_lock_irqsave(&samsung_pwm_lock, flags); |
f1189989 | 150 | |
030c2a1e | 151 | tcon = __raw_readl(pwm.base + REG_TCON); |
f1189989 | 152 | |
f1189989 TF |
153 | tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan)); |
154 | tcon |= TCON_MANUALUPDATE(tcon_chan); | |
155 | ||
030c2a1e TF |
156 | __raw_writel(tcnt, pwm.base + REG_TCNTB(channel)); |
157 | __raw_writel(tcnt, pwm.base + REG_TCMPB(channel)); | |
158 | __raw_writel(tcon, pwm.base + REG_TCON); | |
f1189989 | 159 | |
7aac482e | 160 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
f1189989 TF |
161 | } |
162 | ||
163 | static void samsung_time_start(unsigned int channel, bool periodic) | |
164 | { | |
165 | unsigned long tcon; | |
166 | unsigned long flags; | |
167 | ||
168 | if (channel > 0) | |
169 | ++channel; | |
170 | ||
7aac482e | 171 | spin_lock_irqsave(&samsung_pwm_lock, flags); |
f1189989 | 172 | |
030c2a1e | 173 | tcon = __raw_readl(pwm.base + REG_TCON); |
f1189989 TF |
174 | |
175 | tcon &= ~TCON_MANUALUPDATE(channel); | |
176 | tcon |= TCON_START(channel); | |
177 | ||
178 | if (periodic) | |
179 | tcon |= TCON_AUTORELOAD(channel); | |
180 | else | |
181 | tcon &= ~TCON_AUTORELOAD(channel); | |
182 | ||
030c2a1e | 183 | __raw_writel(tcon, pwm.base + REG_TCON); |
f1189989 | 184 | |
7aac482e | 185 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
f1189989 TF |
186 | } |
187 | ||
188 | static int samsung_set_next_event(unsigned long cycles, | |
189 | struct clock_event_device *evt) | |
190 | { | |
81d4f7bf TF |
191 | /* |
192 | * This check is needed to account for internal rounding | |
193 | * errors inside clockevents core, which might result in | |
194 | * passing cycles = 0, which in turn would not generate any | |
195 | * timer interrupt and hang the system. | |
196 | * | |
197 | * Another solution would be to set up the clockevent device | |
198 | * with min_delta = 2, but this would unnecessarily increase | |
199 | * the minimum sleep period. | |
200 | */ | |
201 | if (!cycles) | |
202 | cycles = 1; | |
203 | ||
030c2a1e TF |
204 | samsung_time_setup(pwm.event_id, cycles); |
205 | samsung_time_start(pwm.event_id, false); | |
f1189989 TF |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static void samsung_timer_resume(void) | |
211 | { | |
212 | /* event timer restart */ | |
6fe4dfd0 | 213 | samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1); |
030c2a1e | 214 | samsung_time_start(pwm.event_id, true); |
f1189989 TF |
215 | |
216 | /* source timer restart */ | |
030c2a1e TF |
217 | samsung_time_setup(pwm.source_id, pwm.tcnt_max); |
218 | samsung_time_start(pwm.source_id, true); | |
f1189989 TF |
219 | } |
220 | ||
221 | static void samsung_set_mode(enum clock_event_mode mode, | |
222 | struct clock_event_device *evt) | |
223 | { | |
030c2a1e | 224 | samsung_time_stop(pwm.event_id); |
f1189989 TF |
225 | |
226 | switch (mode) { | |
227 | case CLOCK_EVT_MODE_PERIODIC: | |
6fe4dfd0 | 228 | samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1); |
030c2a1e | 229 | samsung_time_start(pwm.event_id, true); |
f1189989 TF |
230 | break; |
231 | ||
232 | case CLOCK_EVT_MODE_ONESHOT: | |
233 | break; | |
234 | ||
235 | case CLOCK_EVT_MODE_UNUSED: | |
236 | case CLOCK_EVT_MODE_SHUTDOWN: | |
237 | break; | |
238 | ||
239 | case CLOCK_EVT_MODE_RESUME: | |
240 | samsung_timer_resume(); | |
241 | break; | |
242 | } | |
243 | } | |
244 | ||
245 | static struct clock_event_device time_event_device = { | |
246 | .name = "samsung_event_timer", | |
247 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
248 | .rating = 200, | |
249 | .set_next_event = samsung_set_next_event, | |
250 | .set_mode = samsung_set_mode, | |
251 | }; | |
252 | ||
253 | static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id) | |
254 | { | |
255 | struct clock_event_device *evt = dev_id; | |
256 | ||
030c2a1e TF |
257 | if (pwm.variant.has_tint_cstat) { |
258 | u32 mask = (1 << pwm.event_id); | |
259 | writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); | |
f1189989 TF |
260 | } |
261 | ||
262 | evt->event_handler(evt); | |
263 | ||
264 | return IRQ_HANDLED; | |
265 | } | |
266 | ||
267 | static struct irqaction samsung_clock_event_irq = { | |
268 | .name = "samsung_time_irq", | |
269 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | |
270 | .handler = samsung_clock_event_isr, | |
271 | .dev_id = &time_event_device, | |
272 | }; | |
273 | ||
274 | static void __init samsung_clockevent_init(void) | |
275 | { | |
276 | unsigned long pclk; | |
277 | unsigned long clock_rate; | |
278 | unsigned int irq_number; | |
279 | ||
030c2a1e | 280 | pclk = clk_get_rate(pwm.timerclk); |
f1189989 | 281 | |
030c2a1e TF |
282 | samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div); |
283 | samsung_timer_set_divisor(pwm.event_id, pwm.tdiv); | |
f1189989 | 284 | |
030c2a1e TF |
285 | clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv); |
286 | pwm.clock_count_per_tick = clock_rate / HZ; | |
f1189989 TF |
287 | |
288 | time_event_device.cpumask = cpumask_of(0); | |
e9b852b8 TF |
289 | clockevents_config_and_register(&time_event_device, |
290 | clock_rate, 1, pwm.tcnt_max); | |
f1189989 | 291 | |
030c2a1e | 292 | irq_number = pwm.irq[pwm.event_id]; |
f1189989 TF |
293 | setup_irq(irq_number, &samsung_clock_event_irq); |
294 | ||
030c2a1e TF |
295 | if (pwm.variant.has_tint_cstat) { |
296 | u32 mask = (1 << pwm.event_id); | |
297 | writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); | |
f1189989 TF |
298 | } |
299 | } | |
300 | ||
f1189989 TF |
301 | /* |
302 | * Override the global weak sched_clock symbol with this | |
303 | * local implementation which uses the clocksource to get some | |
304 | * better resolution when scheduling the kernel. We accept that | |
305 | * this wraps around for now, since it is just a relative time | |
306 | * stamp. (Inspired by U300 implementation.) | |
307 | */ | |
308 | static u32 notrace samsung_read_sched_clock(void) | |
309 | { | |
61d7e205 | 310 | return ~__raw_readl(pwm.source_reg); |
f1189989 TF |
311 | } |
312 | ||
313 | static void __init samsung_clocksource_init(void) | |
314 | { | |
f1189989 TF |
315 | unsigned long pclk; |
316 | unsigned long clock_rate; | |
317 | int ret; | |
318 | ||
030c2a1e | 319 | pclk = clk_get_rate(pwm.timerclk); |
f1189989 | 320 | |
030c2a1e TF |
321 | samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div); |
322 | samsung_timer_set_divisor(pwm.source_id, pwm.tdiv); | |
f1189989 | 323 | |
030c2a1e | 324 | clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv); |
f1189989 | 325 | |
030c2a1e TF |
326 | samsung_time_setup(pwm.source_id, pwm.tcnt_max); |
327 | samsung_time_start(pwm.source_id, true); | |
f1189989 | 328 | |
61d7e205 TF |
329 | if (pwm.source_id == 4) |
330 | pwm.source_reg = pwm.base + 0x40; | |
331 | else | |
332 | pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14; | |
333 | ||
f1189989 | 334 | setup_sched_clock(samsung_read_sched_clock, |
030c2a1e | 335 | pwm.variant.bits, clock_rate); |
f1189989 | 336 | |
61d7e205 | 337 | ret = clocksource_mmio_init(pwm.source_reg, "samsung_clocksource_timer", |
030c2a1e | 338 | clock_rate, 250, pwm.variant.bits, |
f1189989 TF |
339 | clocksource_mmio_readl_down); |
340 | if (ret) | |
341 | panic("samsung_clocksource_timer: can't register clocksource\n"); | |
342 | } | |
343 | ||
344 | static void __init samsung_timer_resources(void) | |
345 | { | |
030c2a1e TF |
346 | pwm.timerclk = clk_get(NULL, "timers"); |
347 | if (IS_ERR(pwm.timerclk)) | |
f1189989 TF |
348 | panic("failed to get timers clock for timer"); |
349 | ||
030c2a1e | 350 | clk_prepare_enable(pwm.timerclk); |
f1189989 | 351 | |
030c2a1e TF |
352 | pwm.tcnt_max = (1UL << pwm.variant.bits) - 1; |
353 | if (pwm.variant.bits == 16) { | |
354 | pwm.tscaler_div = 25; | |
355 | pwm.tdiv = 2; | |
f1189989 | 356 | } else { |
030c2a1e TF |
357 | pwm.tscaler_div = 2; |
358 | pwm.tdiv = 1; | |
f1189989 TF |
359 | } |
360 | } | |
361 | ||
362 | /* | |
363 | * PWM master driver | |
364 | */ | |
f9bb48a2 | 365 | static void __init _samsung_pwm_clocksource_init(void) |
f1189989 TF |
366 | { |
367 | u8 mask; | |
368 | int channel; | |
369 | ||
030c2a1e | 370 | mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1); |
f1189989 TF |
371 | channel = fls(mask) - 1; |
372 | if (channel < 0) | |
373 | panic("failed to find PWM channel for clocksource"); | |
030c2a1e | 374 | pwm.source_id = channel; |
f1189989 TF |
375 | |
376 | mask &= ~(1 << channel); | |
377 | channel = fls(mask) - 1; | |
378 | if (channel < 0) | |
379 | panic("failed to find PWM channel for clock event"); | |
030c2a1e | 380 | pwm.event_id = channel; |
f1189989 TF |
381 | |
382 | samsung_timer_resources(); | |
383 | samsung_clockevent_init(); | |
384 | samsung_clocksource_init(); | |
385 | } | |
386 | ||
f9bb48a2 TF |
387 | void __init samsung_pwm_clocksource_init(void __iomem *base, |
388 | unsigned int *irqs, struct samsung_pwm_variant *variant) | |
389 | { | |
390 | pwm.base = base; | |
391 | memcpy(&pwm.variant, variant, sizeof(pwm.variant)); | |
392 | memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs)); | |
393 | ||
394 | _samsung_pwm_clocksource_init(); | |
395 | } | |
396 | ||
397 | #ifdef CONFIG_CLKSRC_OF | |
f1189989 TF |
398 | static void __init samsung_pwm_alloc(struct device_node *np, |
399 | const struct samsung_pwm_variant *variant) | |
400 | { | |
f1189989 TF |
401 | struct property *prop; |
402 | const __be32 *cur; | |
403 | u32 val; | |
404 | int i; | |
405 | ||
030c2a1e | 406 | memcpy(&pwm.variant, variant, sizeof(pwm.variant)); |
f1189989 | 407 | for (i = 0; i < SAMSUNG_PWM_NUM; ++i) |
030c2a1e | 408 | pwm.irq[i] = irq_of_parse_and_map(np, i); |
f1189989 TF |
409 | |
410 | of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { | |
411 | if (val >= SAMSUNG_PWM_NUM) { | |
412 | pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n", | |
413 | __func__); | |
414 | continue; | |
415 | } | |
030c2a1e | 416 | pwm.variant.output_mask |= 1 << val; |
f1189989 TF |
417 | } |
418 | ||
e2415489 | 419 | pwm.base = of_iomap(np, 0); |
030c2a1e | 420 | if (!pwm.base) { |
f1189989 | 421 | pr_err("%s: failed to map PWM registers\n", __func__); |
f1189989 TF |
422 | return; |
423 | } | |
424 | ||
f9bb48a2 | 425 | _samsung_pwm_clocksource_init(); |
f1189989 TF |
426 | } |
427 | ||
428 | static const struct samsung_pwm_variant s3c24xx_variant = { | |
429 | .bits = 16, | |
430 | .div_base = 1, | |
431 | .has_tint_cstat = false, | |
432 | .tclk_mask = (1 << 4), | |
433 | }; | |
434 | ||
435 | static void __init s3c2410_pwm_clocksource_init(struct device_node *np) | |
436 | { | |
437 | samsung_pwm_alloc(np, &s3c24xx_variant); | |
438 | } | |
439 | CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init); | |
440 | ||
441 | static const struct samsung_pwm_variant s3c64xx_variant = { | |
442 | .bits = 32, | |
443 | .div_base = 0, | |
444 | .has_tint_cstat = true, | |
445 | .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5), | |
446 | }; | |
447 | ||
448 | static void __init s3c64xx_pwm_clocksource_init(struct device_node *np) | |
449 | { | |
450 | samsung_pwm_alloc(np, &s3c64xx_variant); | |
451 | } | |
452 | CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init); | |
453 | ||
454 | static const struct samsung_pwm_variant s5p64x0_variant = { | |
455 | .bits = 32, | |
456 | .div_base = 0, | |
457 | .has_tint_cstat = true, | |
458 | .tclk_mask = 0, | |
459 | }; | |
460 | ||
461 | static void __init s5p64x0_pwm_clocksource_init(struct device_node *np) | |
462 | { | |
463 | samsung_pwm_alloc(np, &s5p64x0_variant); | |
464 | } | |
465 | CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init); | |
466 | ||
467 | static const struct samsung_pwm_variant s5p_variant = { | |
468 | .bits = 32, | |
469 | .div_base = 0, | |
470 | .has_tint_cstat = true, | |
471 | .tclk_mask = (1 << 5), | |
472 | }; | |
473 | ||
474 | static void __init s5p_pwm_clocksource_init(struct device_node *np) | |
475 | { | |
476 | samsung_pwm_alloc(np, &s5p_variant); | |
477 | } | |
478 | CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init); | |
f9bb48a2 | 479 | #endif |