Commit | Line | Data |
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3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
3fb1b6ad MD |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/irq.h> | |
28 | #include <linux/err.h> | |
3f7e5e24 | 29 | #include <linux/delay.h> |
3fb1b6ad MD |
30 | #include <linux/clocksource.h> |
31 | #include <linux/clockchips.h> | |
46a12f74 | 32 | #include <linux/sh_timer.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
3fb1b6ad MD |
34 | |
35 | struct sh_cmt_priv { | |
36 | void __iomem *mapbase; | |
37 | struct clk *clk; | |
38 | unsigned long width; /* 16 or 32 bit version of hardware block */ | |
39 | unsigned long overflow_bit; | |
40 | unsigned long clear_bits; | |
41 | struct irqaction irqaction; | |
42 | struct platform_device *pdev; | |
43 | ||
44 | unsigned long flags; | |
45 | unsigned long match_value; | |
46 | unsigned long next_match_value; | |
47 | unsigned long max_match_value; | |
48 | unsigned long rate; | |
49 | spinlock_t lock; | |
50 | struct clock_event_device ced; | |
19bdc9d0 | 51 | struct clocksource cs; |
3fb1b6ad MD |
52 | unsigned long total_cycles; |
53 | }; | |
54 | ||
55 | static DEFINE_SPINLOCK(sh_cmt_lock); | |
56 | ||
57 | #define CMSTR -1 /* shared register */ | |
58 | #define CMCSR 0 /* channel register */ | |
59 | #define CMCNT 1 /* channel register */ | |
60 | #define CMCOR 2 /* channel register */ | |
61 | ||
62 | static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr) | |
63 | { | |
46a12f74 | 64 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
3fb1b6ad MD |
65 | void __iomem *base = p->mapbase; |
66 | unsigned long offs; | |
67 | ||
68 | if (reg_nr == CMSTR) { | |
69 | offs = 0; | |
70 | base -= cfg->channel_offset; | |
71 | } else | |
72 | offs = reg_nr; | |
73 | ||
74 | if (p->width == 16) | |
75 | offs <<= 1; | |
76 | else { | |
77 | offs <<= 2; | |
78 | if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) | |
79 | return ioread32(base + offs); | |
80 | } | |
81 | ||
82 | return ioread16(base + offs); | |
83 | } | |
84 | ||
85 | static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr, | |
86 | unsigned long value) | |
87 | { | |
46a12f74 | 88 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
3fb1b6ad MD |
89 | void __iomem *base = p->mapbase; |
90 | unsigned long offs; | |
91 | ||
92 | if (reg_nr == CMSTR) { | |
93 | offs = 0; | |
94 | base -= cfg->channel_offset; | |
95 | } else | |
96 | offs = reg_nr; | |
97 | ||
98 | if (p->width == 16) | |
99 | offs <<= 1; | |
100 | else { | |
101 | offs <<= 2; | |
102 | if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) { | |
103 | iowrite32(value, base + offs); | |
104 | return; | |
105 | } | |
106 | } | |
107 | ||
108 | iowrite16(value, base + offs); | |
109 | } | |
110 | ||
111 | static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p, | |
112 | int *has_wrapped) | |
113 | { | |
114 | unsigned long v1, v2, v3; | |
5b644c7a MD |
115 | int o1, o2; |
116 | ||
117 | o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit; | |
3fb1b6ad MD |
118 | |
119 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
120 | do { | |
5b644c7a | 121 | o2 = o1; |
3fb1b6ad MD |
122 | v1 = sh_cmt_read(p, CMCNT); |
123 | v2 = sh_cmt_read(p, CMCNT); | |
124 | v3 = sh_cmt_read(p, CMCNT); | |
5b644c7a MD |
125 | o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit; |
126 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) | |
127 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 128 | |
5b644c7a | 129 | *has_wrapped = o1; |
3fb1b6ad MD |
130 | return v2; |
131 | } | |
132 | ||
133 | ||
134 | static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start) | |
135 | { | |
46a12f74 | 136 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
3fb1b6ad MD |
137 | unsigned long flags, value; |
138 | ||
139 | /* start stop register shared by multiple timer channels */ | |
140 | spin_lock_irqsave(&sh_cmt_lock, flags); | |
141 | value = sh_cmt_read(p, CMSTR); | |
142 | ||
143 | if (start) | |
144 | value |= 1 << cfg->timer_bit; | |
145 | else | |
146 | value &= ~(1 << cfg->timer_bit); | |
147 | ||
148 | sh_cmt_write(p, CMSTR, value); | |
149 | spin_unlock_irqrestore(&sh_cmt_lock, flags); | |
150 | } | |
151 | ||
152 | static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate) | |
153 | { | |
3f7e5e24 | 154 | int k, ret; |
3fb1b6ad | 155 | |
9436b4ab | 156 | /* enable clock */ |
3fb1b6ad MD |
157 | ret = clk_enable(p->clk); |
158 | if (ret) { | |
214a607a | 159 | dev_err(&p->pdev->dev, "cannot enable clock\n"); |
3f7e5e24 | 160 | goto err0; |
3fb1b6ad | 161 | } |
3fb1b6ad MD |
162 | |
163 | /* make sure channel is disabled */ | |
164 | sh_cmt_start_stop_ch(p, 0); | |
165 | ||
166 | /* configure channel, periodic mode and maximum timeout */ | |
3014f474 MD |
167 | if (p->width == 16) { |
168 | *rate = clk_get_rate(p->clk) / 512; | |
169 | sh_cmt_write(p, CMCSR, 0x43); | |
170 | } else { | |
171 | *rate = clk_get_rate(p->clk) / 8; | |
3fb1b6ad | 172 | sh_cmt_write(p, CMCSR, 0x01a4); |
3014f474 | 173 | } |
3fb1b6ad MD |
174 | |
175 | sh_cmt_write(p, CMCOR, 0xffffffff); | |
176 | sh_cmt_write(p, CMCNT, 0); | |
177 | ||
3f7e5e24 MD |
178 | /* |
179 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
180 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
181 | * modifying CMCNT register; two RCLK cycles are necessary before | |
182 | * this register is either read or any modification of the value | |
183 | * it holds is reflected in the LSI's actual operation. | |
184 | * | |
185 | * While at it, we're supposed to clear out the CMCNT as of this | |
186 | * moment, so make sure it's processed properly here. This will | |
187 | * take RCLKx2 at maximum. | |
188 | */ | |
189 | for (k = 0; k < 100; k++) { | |
190 | if (!sh_cmt_read(p, CMCNT)) | |
191 | break; | |
192 | udelay(1); | |
193 | } | |
194 | ||
195 | if (sh_cmt_read(p, CMCNT)) { | |
196 | dev_err(&p->pdev->dev, "cannot clear CMCNT\n"); | |
197 | ret = -ETIMEDOUT; | |
198 | goto err1; | |
199 | } | |
200 | ||
3fb1b6ad MD |
201 | /* enable channel */ |
202 | sh_cmt_start_stop_ch(p, 1); | |
203 | return 0; | |
3f7e5e24 MD |
204 | err1: |
205 | /* stop clock */ | |
206 | clk_disable(p->clk); | |
207 | ||
208 | err0: | |
209 | return ret; | |
3fb1b6ad MD |
210 | } |
211 | ||
212 | static void sh_cmt_disable(struct sh_cmt_priv *p) | |
213 | { | |
214 | /* disable channel */ | |
215 | sh_cmt_start_stop_ch(p, 0); | |
216 | ||
be890a1a MD |
217 | /* disable interrupts in CMT block */ |
218 | sh_cmt_write(p, CMCSR, 0); | |
219 | ||
9436b4ab | 220 | /* stop clock */ |
3fb1b6ad MD |
221 | clk_disable(p->clk); |
222 | } | |
223 | ||
224 | /* private flags */ | |
225 | #define FLAG_CLOCKEVENT (1 << 0) | |
226 | #define FLAG_CLOCKSOURCE (1 << 1) | |
227 | #define FLAG_REPROGRAM (1 << 2) | |
228 | #define FLAG_SKIPEVENT (1 << 3) | |
229 | #define FLAG_IRQCONTEXT (1 << 4) | |
230 | ||
231 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p, | |
232 | int absolute) | |
233 | { | |
234 | unsigned long new_match; | |
235 | unsigned long value = p->next_match_value; | |
236 | unsigned long delay = 0; | |
237 | unsigned long now = 0; | |
238 | int has_wrapped; | |
239 | ||
240 | now = sh_cmt_get_counter(p, &has_wrapped); | |
241 | p->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
242 | ||
243 | if (has_wrapped) { | |
244 | /* we're competing with the interrupt handler. | |
245 | * -> let the interrupt handler reprogram the timer. | |
246 | * -> interrupt number two handles the event. | |
247 | */ | |
248 | p->flags |= FLAG_SKIPEVENT; | |
249 | return; | |
250 | } | |
251 | ||
252 | if (absolute) | |
253 | now = 0; | |
254 | ||
255 | do { | |
256 | /* reprogram the timer hardware, | |
257 | * but don't save the new match value yet. | |
258 | */ | |
259 | new_match = now + value + delay; | |
260 | if (new_match > p->max_match_value) | |
261 | new_match = p->max_match_value; | |
262 | ||
263 | sh_cmt_write(p, CMCOR, new_match); | |
264 | ||
265 | now = sh_cmt_get_counter(p, &has_wrapped); | |
266 | if (has_wrapped && (new_match > p->match_value)) { | |
267 | /* we are changing to a greater match value, | |
268 | * so this wrap must be caused by the counter | |
269 | * matching the old value. | |
270 | * -> first interrupt reprograms the timer. | |
271 | * -> interrupt number two handles the event. | |
272 | */ | |
273 | p->flags |= FLAG_SKIPEVENT; | |
274 | break; | |
275 | } | |
276 | ||
277 | if (has_wrapped) { | |
278 | /* we are changing to a smaller match value, | |
279 | * so the wrap must be caused by the counter | |
280 | * matching the new value. | |
281 | * -> save programmed match value. | |
282 | * -> let isr handle the event. | |
283 | */ | |
284 | p->match_value = new_match; | |
285 | break; | |
286 | } | |
287 | ||
288 | /* be safe: verify hardware settings */ | |
289 | if (now < new_match) { | |
290 | /* timer value is below match value, all good. | |
291 | * this makes sure we won't miss any match events. | |
292 | * -> save programmed match value. | |
293 | * -> let isr handle the event. | |
294 | */ | |
295 | p->match_value = new_match; | |
296 | break; | |
297 | } | |
298 | ||
299 | /* the counter has reached a value greater | |
300 | * than our new match value. and since the | |
301 | * has_wrapped flag isn't set we must have | |
302 | * programmed a too close event. | |
303 | * -> increase delay and retry. | |
304 | */ | |
305 | if (delay) | |
306 | delay <<= 1; | |
307 | else | |
308 | delay = 1; | |
309 | ||
310 | if (!delay) | |
214a607a | 311 | dev_warn(&p->pdev->dev, "too long delay\n"); |
3fb1b6ad MD |
312 | |
313 | } while (delay); | |
314 | } | |
315 | ||
65ada547 | 316 | static void __sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta) |
3fb1b6ad | 317 | { |
3fb1b6ad | 318 | if (delta > p->max_match_value) |
214a607a | 319 | dev_warn(&p->pdev->dev, "delta out of range\n"); |
3fb1b6ad | 320 | |
3fb1b6ad MD |
321 | p->next_match_value = delta; |
322 | sh_cmt_clock_event_program_verify(p, 0); | |
65ada547 TY |
323 | } |
324 | ||
325 | static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta) | |
326 | { | |
327 | unsigned long flags; | |
328 | ||
329 | spin_lock_irqsave(&p->lock, flags); | |
330 | __sh_cmt_set_next(p, delta); | |
3fb1b6ad MD |
331 | spin_unlock_irqrestore(&p->lock, flags); |
332 | } | |
333 | ||
334 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
335 | { | |
336 | struct sh_cmt_priv *p = dev_id; | |
337 | ||
338 | /* clear flags */ | |
339 | sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits); | |
340 | ||
341 | /* update clock source counter to begin with if enabled | |
342 | * the wrap flag should be cleared by the timer specific | |
343 | * isr before we end up here. | |
344 | */ | |
345 | if (p->flags & FLAG_CLOCKSOURCE) | |
43809473 | 346 | p->total_cycles += p->match_value + 1; |
3fb1b6ad MD |
347 | |
348 | if (!(p->flags & FLAG_REPROGRAM)) | |
349 | p->next_match_value = p->max_match_value; | |
350 | ||
351 | p->flags |= FLAG_IRQCONTEXT; | |
352 | ||
353 | if (p->flags & FLAG_CLOCKEVENT) { | |
354 | if (!(p->flags & FLAG_SKIPEVENT)) { | |
355 | if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) { | |
356 | p->next_match_value = p->max_match_value; | |
357 | p->flags |= FLAG_REPROGRAM; | |
358 | } | |
359 | ||
360 | p->ced.event_handler(&p->ced); | |
361 | } | |
362 | } | |
363 | ||
364 | p->flags &= ~FLAG_SKIPEVENT; | |
365 | ||
366 | if (p->flags & FLAG_REPROGRAM) { | |
367 | p->flags &= ~FLAG_REPROGRAM; | |
368 | sh_cmt_clock_event_program_verify(p, 1); | |
369 | ||
370 | if (p->flags & FLAG_CLOCKEVENT) | |
371 | if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) | |
372 | || (p->match_value == p->next_match_value)) | |
373 | p->flags &= ~FLAG_REPROGRAM; | |
374 | } | |
375 | ||
376 | p->flags &= ~FLAG_IRQCONTEXT; | |
377 | ||
378 | return IRQ_HANDLED; | |
379 | } | |
380 | ||
381 | static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag) | |
382 | { | |
383 | int ret = 0; | |
384 | unsigned long flags; | |
385 | ||
386 | spin_lock_irqsave(&p->lock, flags); | |
387 | ||
388 | if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) | |
389 | ret = sh_cmt_enable(p, &p->rate); | |
390 | ||
391 | if (ret) | |
392 | goto out; | |
393 | p->flags |= flag; | |
394 | ||
395 | /* setup timeout if no clockevent */ | |
396 | if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT))) | |
65ada547 | 397 | __sh_cmt_set_next(p, p->max_match_value); |
3fb1b6ad MD |
398 | out: |
399 | spin_unlock_irqrestore(&p->lock, flags); | |
400 | ||
401 | return ret; | |
402 | } | |
403 | ||
404 | static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag) | |
405 | { | |
406 | unsigned long flags; | |
407 | unsigned long f; | |
408 | ||
409 | spin_lock_irqsave(&p->lock, flags); | |
410 | ||
411 | f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); | |
412 | p->flags &= ~flag; | |
413 | ||
414 | if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) | |
415 | sh_cmt_disable(p); | |
416 | ||
417 | /* adjust the timeout to maximum if only clocksource left */ | |
418 | if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE)) | |
65ada547 | 419 | __sh_cmt_set_next(p, p->max_match_value); |
3fb1b6ad MD |
420 | |
421 | spin_unlock_irqrestore(&p->lock, flags); | |
422 | } | |
423 | ||
19bdc9d0 MD |
424 | static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs) |
425 | { | |
426 | return container_of(cs, struct sh_cmt_priv, cs); | |
427 | } | |
428 | ||
429 | static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) | |
430 | { | |
431 | struct sh_cmt_priv *p = cs_to_sh_cmt(cs); | |
432 | unsigned long flags, raw; | |
433 | unsigned long value; | |
434 | int has_wrapped; | |
435 | ||
436 | spin_lock_irqsave(&p->lock, flags); | |
437 | value = p->total_cycles; | |
438 | raw = sh_cmt_get_counter(p, &has_wrapped); | |
439 | ||
440 | if (unlikely(has_wrapped)) | |
43809473 | 441 | raw += p->match_value + 1; |
19bdc9d0 MD |
442 | spin_unlock_irqrestore(&p->lock, flags); |
443 | ||
444 | return value + raw; | |
445 | } | |
446 | ||
447 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
448 | { | |
3593f5fe | 449 | int ret; |
19bdc9d0 | 450 | struct sh_cmt_priv *p = cs_to_sh_cmt(cs); |
19bdc9d0 MD |
451 | |
452 | p->total_cycles = 0; | |
453 | ||
3593f5fe MD |
454 | ret = sh_cmt_start(p, FLAG_CLOCKSOURCE); |
455 | if (!ret) | |
456 | __clocksource_updatefreq_hz(cs, p->rate); | |
457 | return ret; | |
19bdc9d0 MD |
458 | } |
459 | ||
460 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
461 | { | |
462 | sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE); | |
463 | } | |
464 | ||
c8162884 MD |
465 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
466 | { | |
467 | sh_cmt_start(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE); | |
468 | } | |
469 | ||
19bdc9d0 MD |
470 | static int sh_cmt_register_clocksource(struct sh_cmt_priv *p, |
471 | char *name, unsigned long rating) | |
472 | { | |
473 | struct clocksource *cs = &p->cs; | |
474 | ||
475 | cs->name = name; | |
476 | cs->rating = rating; | |
477 | cs->read = sh_cmt_clocksource_read; | |
478 | cs->enable = sh_cmt_clocksource_enable; | |
479 | cs->disable = sh_cmt_clocksource_disable; | |
c8162884 MD |
480 | cs->suspend = sh_cmt_clocksource_disable; |
481 | cs->resume = sh_cmt_clocksource_resume; | |
19bdc9d0 MD |
482 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
483 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 484 | |
214a607a | 485 | dev_info(&p->pdev->dev, "used as clock source\n"); |
f4d7c356 | 486 | |
3593f5fe MD |
487 | /* Register with dummy 1 Hz value, gets updated in ->enable() */ |
488 | clocksource_register_hz(cs, 1); | |
19bdc9d0 MD |
489 | return 0; |
490 | } | |
491 | ||
3fb1b6ad MD |
492 | static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced) |
493 | { | |
494 | return container_of(ced, struct sh_cmt_priv, ced); | |
495 | } | |
496 | ||
497 | static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic) | |
498 | { | |
499 | struct clock_event_device *ced = &p->ced; | |
500 | ||
501 | sh_cmt_start(p, FLAG_CLOCKEVENT); | |
502 | ||
503 | /* TODO: calculate good shift from rate and counter bit width */ | |
504 | ||
505 | ced->shift = 32; | |
506 | ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift); | |
507 | ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced); | |
508 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); | |
509 | ||
510 | if (periodic) | |
43809473 | 511 | sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1); |
3fb1b6ad MD |
512 | else |
513 | sh_cmt_set_next(p, p->max_match_value); | |
514 | } | |
515 | ||
516 | static void sh_cmt_clock_event_mode(enum clock_event_mode mode, | |
517 | struct clock_event_device *ced) | |
518 | { | |
519 | struct sh_cmt_priv *p = ced_to_sh_cmt(ced); | |
520 | ||
521 | /* deal with old setting first */ | |
522 | switch (ced->mode) { | |
523 | case CLOCK_EVT_MODE_PERIODIC: | |
524 | case CLOCK_EVT_MODE_ONESHOT: | |
525 | sh_cmt_stop(p, FLAG_CLOCKEVENT); | |
526 | break; | |
527 | default: | |
528 | break; | |
529 | } | |
530 | ||
531 | switch (mode) { | |
532 | case CLOCK_EVT_MODE_PERIODIC: | |
214a607a | 533 | dev_info(&p->pdev->dev, "used for periodic clock events\n"); |
3fb1b6ad MD |
534 | sh_cmt_clock_event_start(p, 1); |
535 | break; | |
536 | case CLOCK_EVT_MODE_ONESHOT: | |
214a607a | 537 | dev_info(&p->pdev->dev, "used for oneshot clock events\n"); |
3fb1b6ad MD |
538 | sh_cmt_clock_event_start(p, 0); |
539 | break; | |
540 | case CLOCK_EVT_MODE_SHUTDOWN: | |
541 | case CLOCK_EVT_MODE_UNUSED: | |
542 | sh_cmt_stop(p, FLAG_CLOCKEVENT); | |
543 | break; | |
544 | default: | |
545 | break; | |
546 | } | |
547 | } | |
548 | ||
549 | static int sh_cmt_clock_event_next(unsigned long delta, | |
550 | struct clock_event_device *ced) | |
551 | { | |
552 | struct sh_cmt_priv *p = ced_to_sh_cmt(ced); | |
553 | ||
554 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
555 | if (likely(p->flags & FLAG_IRQCONTEXT)) | |
43809473 | 556 | p->next_match_value = delta - 1; |
3fb1b6ad | 557 | else |
43809473 | 558 | sh_cmt_set_next(p, delta - 1); |
3fb1b6ad MD |
559 | |
560 | return 0; | |
561 | } | |
562 | ||
563 | static void sh_cmt_register_clockevent(struct sh_cmt_priv *p, | |
564 | char *name, unsigned long rating) | |
565 | { | |
566 | struct clock_event_device *ced = &p->ced; | |
567 | ||
568 | memset(ced, 0, sizeof(*ced)); | |
569 | ||
570 | ced->name = name; | |
571 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
572 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
573 | ced->rating = rating; | |
574 | ced->cpumask = cpumask_of(0); | |
575 | ced->set_next_event = sh_cmt_clock_event_next; | |
576 | ced->set_mode = sh_cmt_clock_event_mode; | |
577 | ||
214a607a | 578 | dev_info(&p->pdev->dev, "used for clock events\n"); |
3fb1b6ad MD |
579 | clockevents_register_device(ced); |
580 | } | |
581 | ||
d1fcc0a8 PM |
582 | static int sh_cmt_register(struct sh_cmt_priv *p, char *name, |
583 | unsigned long clockevent_rating, | |
584 | unsigned long clocksource_rating) | |
3fb1b6ad MD |
585 | { |
586 | if (p->width == (sizeof(p->max_match_value) * 8)) | |
587 | p->max_match_value = ~0; | |
588 | else | |
589 | p->max_match_value = (1 << p->width) - 1; | |
590 | ||
591 | p->match_value = p->max_match_value; | |
592 | spin_lock_init(&p->lock); | |
593 | ||
594 | if (clockevent_rating) | |
595 | sh_cmt_register_clockevent(p, name, clockevent_rating); | |
596 | ||
19bdc9d0 MD |
597 | if (clocksource_rating) |
598 | sh_cmt_register_clocksource(p, name, clocksource_rating); | |
599 | ||
3fb1b6ad MD |
600 | return 0; |
601 | } | |
602 | ||
603 | static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev) | |
604 | { | |
46a12f74 | 605 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
3fb1b6ad MD |
606 | struct resource *res; |
607 | int irq, ret; | |
608 | ret = -ENXIO; | |
609 | ||
610 | memset(p, 0, sizeof(*p)); | |
611 | p->pdev = pdev; | |
612 | ||
613 | if (!cfg) { | |
614 | dev_err(&p->pdev->dev, "missing platform data\n"); | |
615 | goto err0; | |
616 | } | |
617 | ||
618 | platform_set_drvdata(pdev, p); | |
619 | ||
620 | res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0); | |
621 | if (!res) { | |
622 | dev_err(&p->pdev->dev, "failed to get I/O memory\n"); | |
623 | goto err0; | |
624 | } | |
625 | ||
626 | irq = platform_get_irq(p->pdev, 0); | |
627 | if (irq < 0) { | |
628 | dev_err(&p->pdev->dev, "failed to get irq\n"); | |
629 | goto err0; | |
630 | } | |
631 | ||
632 | /* map memory, let mapbase point to our channel */ | |
633 | p->mapbase = ioremap_nocache(res->start, resource_size(res)); | |
634 | if (p->mapbase == NULL) { | |
214a607a | 635 | dev_err(&p->pdev->dev, "failed to remap I/O memory\n"); |
3fb1b6ad MD |
636 | goto err0; |
637 | } | |
638 | ||
639 | /* request irq using setup_irq() (too early for request_irq()) */ | |
214a607a | 640 | p->irqaction.name = dev_name(&p->pdev->dev); |
3fb1b6ad MD |
641 | p->irqaction.handler = sh_cmt_interrupt; |
642 | p->irqaction.dev_id = p; | |
fecf066c PM |
643 | p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \ |
644 | IRQF_IRQPOLL | IRQF_NOBALANCING; | |
3fb1b6ad MD |
645 | |
646 | /* get hold of clock */ | |
c2a25e81 | 647 | p->clk = clk_get(&p->pdev->dev, "cmt_fck"); |
3fb1b6ad | 648 | if (IS_ERR(p->clk)) { |
03ff858c MD |
649 | dev_err(&p->pdev->dev, "cannot get clock\n"); |
650 | ret = PTR_ERR(p->clk); | |
651 | goto err1; | |
3fb1b6ad MD |
652 | } |
653 | ||
654 | if (resource_size(res) == 6) { | |
655 | p->width = 16; | |
656 | p->overflow_bit = 0x80; | |
3014f474 | 657 | p->clear_bits = ~0x80; |
3fb1b6ad MD |
658 | } else { |
659 | p->width = 32; | |
660 | p->overflow_bit = 0x8000; | |
661 | p->clear_bits = ~0xc000; | |
662 | } | |
663 | ||
214a607a | 664 | ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev), |
da64c2a8 PM |
665 | cfg->clockevent_rating, |
666 | cfg->clocksource_rating); | |
667 | if (ret) { | |
214a607a | 668 | dev_err(&p->pdev->dev, "registration failed\n"); |
da64c2a8 PM |
669 | goto err1; |
670 | } | |
671 | ||
672 | ret = setup_irq(irq, &p->irqaction); | |
673 | if (ret) { | |
214a607a | 674 | dev_err(&p->pdev->dev, "failed to request irq %d\n", irq); |
da64c2a8 PM |
675 | goto err1; |
676 | } | |
677 | ||
678 | return 0; | |
679 | ||
680 | err1: | |
3fb1b6ad | 681 | iounmap(p->mapbase); |
da64c2a8 | 682 | err0: |
3fb1b6ad MD |
683 | return ret; |
684 | } | |
685 | ||
686 | static int __devinit sh_cmt_probe(struct platform_device *pdev) | |
687 | { | |
688 | struct sh_cmt_priv *p = platform_get_drvdata(pdev); | |
689 | int ret; | |
690 | ||
e475eedb | 691 | if (p) { |
214a607a | 692 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
e475eedb MD |
693 | return 0; |
694 | } | |
695 | ||
8e0b8429 | 696 | p = kmalloc(sizeof(*p), GFP_KERNEL); |
3fb1b6ad MD |
697 | if (p == NULL) { |
698 | dev_err(&pdev->dev, "failed to allocate driver data\n"); | |
699 | return -ENOMEM; | |
700 | } | |
701 | ||
702 | ret = sh_cmt_setup(p, pdev); | |
703 | if (ret) { | |
8e0b8429 | 704 | kfree(p); |
3fb1b6ad MD |
705 | platform_set_drvdata(pdev, NULL); |
706 | } | |
707 | return ret; | |
708 | } | |
709 | ||
710 | static int __devexit sh_cmt_remove(struct platform_device *pdev) | |
711 | { | |
712 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
713 | } | |
714 | ||
715 | static struct platform_driver sh_cmt_device_driver = { | |
716 | .probe = sh_cmt_probe, | |
717 | .remove = __devexit_p(sh_cmt_remove), | |
718 | .driver = { | |
719 | .name = "sh_cmt", | |
720 | } | |
721 | }; | |
722 | ||
723 | static int __init sh_cmt_init(void) | |
724 | { | |
725 | return platform_driver_register(&sh_cmt_device_driver); | |
726 | } | |
727 | ||
728 | static void __exit sh_cmt_exit(void) | |
729 | { | |
730 | platform_driver_unregister(&sh_cmt_device_driver); | |
731 | } | |
732 | ||
e475eedb | 733 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
3fb1b6ad MD |
734 | module_init(sh_cmt_init); |
735 | module_exit(sh_cmt_exit); | |
736 | ||
737 | MODULE_AUTHOR("Magnus Damm"); | |
738 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
739 | MODULE_LICENSE("GPL v2"); |