Commit | Line | Data |
---|---|---|
3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
3fb1b6ad MD |
14 | */ |
15 | ||
e7a9bcc2 LP |
16 | #include <linux/clk.h> |
17 | #include <linux/clockchips.h> | |
18 | #include <linux/clocksource.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/err.h> | |
3fb1b6ad | 21 | #include <linux/init.h> |
3fb1b6ad | 22 | #include <linux/interrupt.h> |
3fb1b6ad | 23 | #include <linux/io.h> |
e7a9bcc2 | 24 | #include <linux/ioport.h> |
3fb1b6ad | 25 | #include <linux/irq.h> |
7deeab5d | 26 | #include <linux/module.h> |
e7a9bcc2 | 27 | #include <linux/platform_device.h> |
615a445f | 28 | #include <linux/pm_domain.h> |
bad81383 | 29 | #include <linux/pm_runtime.h> |
e7a9bcc2 LP |
30 | #include <linux/sh_timer.h> |
31 | #include <linux/slab.h> | |
32 | #include <linux/spinlock.h> | |
3fb1b6ad | 33 | |
2653caf4 | 34 | struct sh_cmt_device; |
7269f933 | 35 | |
2cda3ac4 LP |
36 | /* |
37 | * The CMT comes in 5 different identified flavours, depending not only on the | |
38 | * SoC but also on the particular instance. The following table lists the main | |
39 | * characteristics of those flavours. | |
40 | * | |
41 | * 16B 32B 32B-F 48B 48B-2 | |
42 | * ----------------------------------------------------------------------------- | |
43 | * Channels 2 1/4 1 6 2/8 | |
44 | * Control Width 16 16 16 16 32 | |
45 | * Counter Width 16 32 32 32/48 32/48 | |
46 | * Shared Start/Stop Y Y Y Y N | |
47 | * | |
48 | * The 48-bit gen2 version has a per-channel start/stop register located in the | |
49 | * channel registers block. All other versions have a shared start/stop register | |
50 | * located in the global space. | |
51 | * | |
81b3b271 LP |
52 | * Channels are indexed from 0 to N-1 in the documentation. The channel index |
53 | * infers the start/stop bit position in the control register and the channel | |
54 | * registers block address. Some CMT instances have a subset of channels | |
55 | * available, in which case the index in the documentation doesn't match the | |
56 | * "real" index as implemented in hardware. This is for instance the case with | |
57 | * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 | |
58 | * in the documentation but using start/stop bit 5 and having its registers | |
59 | * block at 0x60. | |
60 | * | |
61 | * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
2cda3ac4 LP |
62 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. |
63 | */ | |
64 | ||
65 | enum sh_cmt_model { | |
66 | SH_CMT_16BIT, | |
67 | SH_CMT_32BIT, | |
68 | SH_CMT_32BIT_FAST, | |
69 | SH_CMT_48BIT, | |
70 | SH_CMT_48BIT_GEN2, | |
71 | }; | |
72 | ||
73 | struct sh_cmt_info { | |
74 | enum sh_cmt_model model; | |
75 | ||
76 | unsigned long width; /* 16 or 32 bit version of hardware block */ | |
77 | unsigned long overflow_bit; | |
78 | unsigned long clear_bits; | |
79 | ||
80 | /* callbacks for CMSTR and CMCSR access */ | |
81 | unsigned long (*read_control)(void __iomem *base, unsigned long offs); | |
82 | void (*write_control)(void __iomem *base, unsigned long offs, | |
83 | unsigned long value); | |
84 | ||
85 | /* callbacks for CMCNT and CMCOR access */ | |
86 | unsigned long (*read_count)(void __iomem *base, unsigned long offs); | |
87 | void (*write_count)(void __iomem *base, unsigned long offs, | |
88 | unsigned long value); | |
89 | }; | |
90 | ||
7269f933 | 91 | struct sh_cmt_channel { |
2653caf4 | 92 | struct sh_cmt_device *cmt; |
3fb1b6ad | 93 | |
81b3b271 LP |
94 | unsigned int index; /* Index in the documentation */ |
95 | unsigned int hwidx; /* Real hardware index */ | |
96 | ||
97 | void __iomem *iostart; | |
98 | void __iomem *ioctrl; | |
c924d2d2 | 99 | |
81b3b271 | 100 | unsigned int timer_bit; |
3fb1b6ad MD |
101 | unsigned long flags; |
102 | unsigned long match_value; | |
103 | unsigned long next_match_value; | |
104 | unsigned long max_match_value; | |
105 | unsigned long rate; | |
7d0c399f | 106 | raw_spinlock_t lock; |
3fb1b6ad | 107 | struct clock_event_device ced; |
19bdc9d0 | 108 | struct clocksource cs; |
3fb1b6ad | 109 | unsigned long total_cycles; |
bad81383 | 110 | bool cs_enabled; |
7269f933 LP |
111 | }; |
112 | ||
2653caf4 | 113 | struct sh_cmt_device { |
7269f933 LP |
114 | struct platform_device *pdev; |
115 | ||
2cda3ac4 | 116 | const struct sh_cmt_info *info; |
81b3b271 | 117 | bool legacy; |
2cda3ac4 | 118 | |
36f1ac98 | 119 | void __iomem *mapbase_ch; |
7269f933 | 120 | void __iomem *mapbase; |
7269f933 LP |
121 | struct clk *clk; |
122 | ||
f5ec9b19 LP |
123 | struct sh_cmt_channel *channels; |
124 | unsigned int num_channels; | |
81b3b271 LP |
125 | |
126 | bool has_clockevent; | |
127 | bool has_clocksource; | |
3fb1b6ad MD |
128 | }; |
129 | ||
d14be99b LP |
130 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
131 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
132 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
133 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
134 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
135 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
136 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
137 | ||
138 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
139 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
140 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
141 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
142 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
143 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
144 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
145 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
146 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
147 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
148 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
149 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
150 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
151 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
152 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
153 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
154 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
155 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
156 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
157 | ||
a6a912ca | 158 | static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
159 | { |
160 | return ioread16(base + (offs << 1)); | |
161 | } | |
162 | ||
a6a912ca MD |
163 | static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) |
164 | { | |
165 | return ioread32(base + (offs << 2)); | |
166 | } | |
167 | ||
168 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, | |
169 | unsigned long value) | |
587acb3d MD |
170 | { |
171 | iowrite16(value, base + (offs << 1)); | |
172 | } | |
3fb1b6ad | 173 | |
a6a912ca MD |
174 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, |
175 | unsigned long value) | |
176 | { | |
177 | iowrite32(value, base + (offs << 2)); | |
178 | } | |
179 | ||
2cda3ac4 LP |
180 | static const struct sh_cmt_info sh_cmt_info[] = { |
181 | [SH_CMT_16BIT] = { | |
182 | .model = SH_CMT_16BIT, | |
183 | .width = 16, | |
d14be99b LP |
184 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
185 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
186 | .read_control = sh_cmt_read16, |
187 | .write_control = sh_cmt_write16, | |
188 | .read_count = sh_cmt_read16, | |
189 | .write_count = sh_cmt_write16, | |
190 | }, | |
191 | [SH_CMT_32BIT] = { | |
192 | .model = SH_CMT_32BIT, | |
193 | .width = 32, | |
d14be99b LP |
194 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
195 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
196 | .read_control = sh_cmt_read16, |
197 | .write_control = sh_cmt_write16, | |
198 | .read_count = sh_cmt_read32, | |
199 | .write_count = sh_cmt_write32, | |
200 | }, | |
201 | [SH_CMT_32BIT_FAST] = { | |
202 | .model = SH_CMT_32BIT_FAST, | |
203 | .width = 32, | |
d14be99b LP |
204 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
205 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
206 | .read_control = sh_cmt_read16, |
207 | .write_control = sh_cmt_write16, | |
208 | .read_count = sh_cmt_read32, | |
209 | .write_count = sh_cmt_write32, | |
210 | }, | |
211 | [SH_CMT_48BIT] = { | |
212 | .model = SH_CMT_48BIT, | |
213 | .width = 32, | |
d14be99b LP |
214 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
215 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
216 | .read_control = sh_cmt_read32, |
217 | .write_control = sh_cmt_write32, | |
218 | .read_count = sh_cmt_read32, | |
219 | .write_count = sh_cmt_write32, | |
220 | }, | |
221 | [SH_CMT_48BIT_GEN2] = { | |
222 | .model = SH_CMT_48BIT_GEN2, | |
223 | .width = 32, | |
d14be99b LP |
224 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
225 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
226 | .read_control = sh_cmt_read32, |
227 | .write_control = sh_cmt_write32, | |
228 | .read_count = sh_cmt_read32, | |
229 | .write_count = sh_cmt_write32, | |
230 | }, | |
231 | }; | |
232 | ||
3fb1b6ad MD |
233 | #define CMCSR 0 /* channel register */ |
234 | #define CMCNT 1 /* channel register */ | |
235 | #define CMCOR 2 /* channel register */ | |
236 | ||
7269f933 | 237 | static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 238 | { |
81b3b271 LP |
239 | if (ch->iostart) |
240 | return ch->cmt->info->read_control(ch->iostart, 0); | |
241 | else | |
242 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); | |
1b56b96b MD |
243 | } |
244 | ||
81b3b271 LP |
245 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, |
246 | unsigned long value) | |
1b56b96b | 247 | { |
81b3b271 LP |
248 | if (ch->iostart) |
249 | ch->cmt->info->write_control(ch->iostart, 0, value); | |
250 | else | |
251 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); | |
1b56b96b MD |
252 | } |
253 | ||
81b3b271 | 254 | static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 255 | { |
81b3b271 | 256 | return ch->cmt->info->read_control(ch->ioctrl, CMCSR); |
3fb1b6ad MD |
257 | } |
258 | ||
81b3b271 | 259 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, |
1b56b96b MD |
260 | unsigned long value) |
261 | { | |
81b3b271 | 262 | ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); |
1b56b96b MD |
263 | } |
264 | ||
81b3b271 | 265 | static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 266 | { |
81b3b271 | 267 | return ch->cmt->info->read_count(ch->ioctrl, CMCNT); |
1b56b96b MD |
268 | } |
269 | ||
7269f933 | 270 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, |
1b56b96b MD |
271 | unsigned long value) |
272 | { | |
81b3b271 | 273 | ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); |
1b56b96b MD |
274 | } |
275 | ||
7269f933 | 276 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, |
1b56b96b MD |
277 | unsigned long value) |
278 | { | |
81b3b271 | 279 | ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); |
1b56b96b MD |
280 | } |
281 | ||
7269f933 | 282 | static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
283 | int *has_wrapped) |
284 | { | |
285 | unsigned long v1, v2, v3; | |
5b644c7a MD |
286 | int o1, o2; |
287 | ||
2cda3ac4 | 288 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
289 | |
290 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
291 | do { | |
5b644c7a | 292 | o2 = o1; |
7269f933 LP |
293 | v1 = sh_cmt_read_cmcnt(ch); |
294 | v2 = sh_cmt_read_cmcnt(ch); | |
295 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 296 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
297 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
298 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 299 | |
5b644c7a | 300 | *has_wrapped = o1; |
3fb1b6ad MD |
301 | return v2; |
302 | } | |
303 | ||
587acb3d | 304 | static DEFINE_RAW_SPINLOCK(sh_cmt_lock); |
3fb1b6ad | 305 | |
7269f933 | 306 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 307 | { |
3fb1b6ad MD |
308 | unsigned long flags, value; |
309 | ||
310 | /* start stop register shared by multiple timer channels */ | |
7d0c399f | 311 | raw_spin_lock_irqsave(&sh_cmt_lock, flags); |
7269f933 | 312 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
313 | |
314 | if (start) | |
81b3b271 | 315 | value |= 1 << ch->timer_bit; |
3fb1b6ad | 316 | else |
81b3b271 | 317 | value &= ~(1 << ch->timer_bit); |
3fb1b6ad | 318 | |
7269f933 | 319 | sh_cmt_write_cmstr(ch, value); |
7d0c399f | 320 | raw_spin_unlock_irqrestore(&sh_cmt_lock, flags); |
3fb1b6ad MD |
321 | } |
322 | ||
7269f933 | 323 | static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate) |
3fb1b6ad | 324 | { |
3f7e5e24 | 325 | int k, ret; |
3fb1b6ad | 326 | |
7269f933 LP |
327 | pm_runtime_get_sync(&ch->cmt->pdev->dev); |
328 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); | |
bad81383 | 329 | |
9436b4ab | 330 | /* enable clock */ |
7269f933 | 331 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 332 | if (ret) { |
740a9518 LP |
333 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
334 | ch->index); | |
3f7e5e24 | 335 | goto err0; |
3fb1b6ad | 336 | } |
3fb1b6ad MD |
337 | |
338 | /* make sure channel is disabled */ | |
7269f933 | 339 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
340 | |
341 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 342 | if (ch->cmt->info->width == 16) { |
7269f933 | 343 | *rate = clk_get_rate(ch->cmt->clk) / 512; |
d14be99b LP |
344 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
345 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 346 | } else { |
7269f933 | 347 | *rate = clk_get_rate(ch->cmt->clk) / 8; |
d14be99b LP |
348 | sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | |
349 | SH_CMT32_CMCSR_CMTOUT_IE | | |
350 | SH_CMT32_CMCSR_CMR_IRQ | | |
351 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 352 | } |
3fb1b6ad | 353 | |
7269f933 LP |
354 | sh_cmt_write_cmcor(ch, 0xffffffff); |
355 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 356 | |
3f7e5e24 MD |
357 | /* |
358 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
359 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
360 | * modifying CMCNT register; two RCLK cycles are necessary before | |
361 | * this register is either read or any modification of the value | |
362 | * it holds is reflected in the LSI's actual operation. | |
363 | * | |
364 | * While at it, we're supposed to clear out the CMCNT as of this | |
365 | * moment, so make sure it's processed properly here. This will | |
366 | * take RCLKx2 at maximum. | |
367 | */ | |
368 | for (k = 0; k < 100; k++) { | |
7269f933 | 369 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
370 | break; |
371 | udelay(1); | |
372 | } | |
373 | ||
7269f933 | 374 | if (sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
375 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
376 | ch->index); | |
3f7e5e24 MD |
377 | ret = -ETIMEDOUT; |
378 | goto err1; | |
379 | } | |
380 | ||
3fb1b6ad | 381 | /* enable channel */ |
7269f933 | 382 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 383 | return 0; |
3f7e5e24 MD |
384 | err1: |
385 | /* stop clock */ | |
7269f933 | 386 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
387 | |
388 | err0: | |
389 | return ret; | |
3fb1b6ad MD |
390 | } |
391 | ||
7269f933 | 392 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
393 | { |
394 | /* disable channel */ | |
7269f933 | 395 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 396 | |
be890a1a | 397 | /* disable interrupts in CMT block */ |
7269f933 | 398 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 399 | |
9436b4ab | 400 | /* stop clock */ |
7269f933 | 401 | clk_disable(ch->cmt->clk); |
bad81383 | 402 | |
7269f933 LP |
403 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
404 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
405 | } |
406 | ||
407 | /* private flags */ | |
408 | #define FLAG_CLOCKEVENT (1 << 0) | |
409 | #define FLAG_CLOCKSOURCE (1 << 1) | |
410 | #define FLAG_REPROGRAM (1 << 2) | |
411 | #define FLAG_SKIPEVENT (1 << 3) | |
412 | #define FLAG_IRQCONTEXT (1 << 4) | |
413 | ||
7269f933 | 414 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
415 | int absolute) |
416 | { | |
417 | unsigned long new_match; | |
7269f933 | 418 | unsigned long value = ch->next_match_value; |
3fb1b6ad MD |
419 | unsigned long delay = 0; |
420 | unsigned long now = 0; | |
421 | int has_wrapped; | |
422 | ||
7269f933 LP |
423 | now = sh_cmt_get_counter(ch, &has_wrapped); |
424 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
425 | |
426 | if (has_wrapped) { | |
427 | /* we're competing with the interrupt handler. | |
428 | * -> let the interrupt handler reprogram the timer. | |
429 | * -> interrupt number two handles the event. | |
430 | */ | |
7269f933 | 431 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
432 | return; |
433 | } | |
434 | ||
435 | if (absolute) | |
436 | now = 0; | |
437 | ||
438 | do { | |
439 | /* reprogram the timer hardware, | |
440 | * but don't save the new match value yet. | |
441 | */ | |
442 | new_match = now + value + delay; | |
7269f933 LP |
443 | if (new_match > ch->max_match_value) |
444 | new_match = ch->max_match_value; | |
3fb1b6ad | 445 | |
7269f933 | 446 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 447 | |
7269f933 LP |
448 | now = sh_cmt_get_counter(ch, &has_wrapped); |
449 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
450 | /* we are changing to a greater match value, |
451 | * so this wrap must be caused by the counter | |
452 | * matching the old value. | |
453 | * -> first interrupt reprograms the timer. | |
454 | * -> interrupt number two handles the event. | |
455 | */ | |
7269f933 | 456 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
457 | break; |
458 | } | |
459 | ||
460 | if (has_wrapped) { | |
461 | /* we are changing to a smaller match value, | |
462 | * so the wrap must be caused by the counter | |
463 | * matching the new value. | |
464 | * -> save programmed match value. | |
465 | * -> let isr handle the event. | |
466 | */ | |
7269f933 | 467 | ch->match_value = new_match; |
3fb1b6ad MD |
468 | break; |
469 | } | |
470 | ||
471 | /* be safe: verify hardware settings */ | |
472 | if (now < new_match) { | |
473 | /* timer value is below match value, all good. | |
474 | * this makes sure we won't miss any match events. | |
475 | * -> save programmed match value. | |
476 | * -> let isr handle the event. | |
477 | */ | |
7269f933 | 478 | ch->match_value = new_match; |
3fb1b6ad MD |
479 | break; |
480 | } | |
481 | ||
482 | /* the counter has reached a value greater | |
483 | * than our new match value. and since the | |
484 | * has_wrapped flag isn't set we must have | |
485 | * programmed a too close event. | |
486 | * -> increase delay and retry. | |
487 | */ | |
488 | if (delay) | |
489 | delay <<= 1; | |
490 | else | |
491 | delay = 1; | |
492 | ||
493 | if (!delay) | |
740a9518 LP |
494 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
495 | ch->index); | |
3fb1b6ad MD |
496 | |
497 | } while (delay); | |
498 | } | |
499 | ||
7269f933 | 500 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 501 | { |
7269f933 | 502 | if (delta > ch->max_match_value) |
740a9518 LP |
503 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
504 | ch->index); | |
3fb1b6ad | 505 | |
7269f933 LP |
506 | ch->next_match_value = delta; |
507 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
508 | } |
509 | ||
7269f933 | 510 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
511 | { |
512 | unsigned long flags; | |
513 | ||
7269f933 LP |
514 | raw_spin_lock_irqsave(&ch->lock, flags); |
515 | __sh_cmt_set_next(ch, delta); | |
516 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
517 | } |
518 | ||
519 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
520 | { | |
7269f933 | 521 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
522 | |
523 | /* clear flags */ | |
2cda3ac4 LP |
524 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
525 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
526 | |
527 | /* update clock source counter to begin with if enabled | |
528 | * the wrap flag should be cleared by the timer specific | |
529 | * isr before we end up here. | |
530 | */ | |
7269f933 LP |
531 | if (ch->flags & FLAG_CLOCKSOURCE) |
532 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 533 | |
7269f933 LP |
534 | if (!(ch->flags & FLAG_REPROGRAM)) |
535 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 536 | |
7269f933 | 537 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 538 | |
7269f933 LP |
539 | if (ch->flags & FLAG_CLOCKEVENT) { |
540 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
541 | if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) { | |
542 | ch->next_match_value = ch->max_match_value; | |
543 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
544 | } |
545 | ||
7269f933 | 546 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
547 | } |
548 | } | |
549 | ||
7269f933 | 550 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 551 | |
7269f933 LP |
552 | if (ch->flags & FLAG_REPROGRAM) { |
553 | ch->flags &= ~FLAG_REPROGRAM; | |
554 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 555 | |
7269f933 LP |
556 | if (ch->flags & FLAG_CLOCKEVENT) |
557 | if ((ch->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) | |
558 | || (ch->match_value == ch->next_match_value)) | |
559 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
560 | } |
561 | ||
7269f933 | 562 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
563 | |
564 | return IRQ_HANDLED; | |
565 | } | |
566 | ||
7269f933 | 567 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
568 | { |
569 | int ret = 0; | |
570 | unsigned long flags; | |
571 | ||
7269f933 | 572 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 573 | |
7269f933 LP |
574 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
575 | ret = sh_cmt_enable(ch, &ch->rate); | |
3fb1b6ad MD |
576 | |
577 | if (ret) | |
578 | goto out; | |
7269f933 | 579 | ch->flags |= flag; |
3fb1b6ad MD |
580 | |
581 | /* setup timeout if no clockevent */ | |
7269f933 LP |
582 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
583 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 584 | out: |
7269f933 | 585 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
586 | |
587 | return ret; | |
588 | } | |
589 | ||
7269f933 | 590 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
591 | { |
592 | unsigned long flags; | |
593 | unsigned long f; | |
594 | ||
7269f933 | 595 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 596 | |
7269f933 LP |
597 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
598 | ch->flags &= ~flag; | |
3fb1b6ad | 599 | |
7269f933 LP |
600 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
601 | sh_cmt_disable(ch); | |
3fb1b6ad MD |
602 | |
603 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
604 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
605 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 606 | |
7269f933 | 607 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
608 | } |
609 | ||
7269f933 | 610 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 611 | { |
7269f933 | 612 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
613 | } |
614 | ||
615 | static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) | |
616 | { | |
7269f933 | 617 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 MD |
618 | unsigned long flags, raw; |
619 | unsigned long value; | |
620 | int has_wrapped; | |
621 | ||
7269f933 LP |
622 | raw_spin_lock_irqsave(&ch->lock, flags); |
623 | value = ch->total_cycles; | |
624 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
625 | |
626 | if (unlikely(has_wrapped)) | |
7269f933 LP |
627 | raw += ch->match_value + 1; |
628 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
629 | |
630 | return value + raw; | |
631 | } | |
632 | ||
633 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
634 | { | |
3593f5fe | 635 | int ret; |
7269f933 | 636 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 637 | |
7269f933 | 638 | WARN_ON(ch->cs_enabled); |
bad81383 | 639 | |
7269f933 | 640 | ch->total_cycles = 0; |
19bdc9d0 | 641 | |
7269f933 | 642 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
bad81383 | 643 | if (!ret) { |
7269f933 LP |
644 | __clocksource_updatefreq_hz(cs, ch->rate); |
645 | ch->cs_enabled = true; | |
bad81383 | 646 | } |
3593f5fe | 647 | return ret; |
19bdc9d0 MD |
648 | } |
649 | ||
650 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
651 | { | |
7269f933 | 652 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 653 | |
7269f933 | 654 | WARN_ON(!ch->cs_enabled); |
bad81383 | 655 | |
7269f933 LP |
656 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
657 | ch->cs_enabled = false; | |
19bdc9d0 MD |
658 | } |
659 | ||
9bb5ec88 RW |
660 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
661 | { | |
7269f933 | 662 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 663 | |
7269f933 LP |
664 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
665 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
666 | } |
667 | ||
c8162884 MD |
668 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
669 | { | |
7269f933 | 670 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 671 | |
7269f933 LP |
672 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); |
673 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); | |
c8162884 MD |
674 | } |
675 | ||
7269f933 | 676 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
fb28a659 | 677 | const char *name) |
19bdc9d0 | 678 | { |
7269f933 | 679 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
680 | |
681 | cs->name = name; | |
fb28a659 | 682 | cs->rating = 125; |
19bdc9d0 MD |
683 | cs->read = sh_cmt_clocksource_read; |
684 | cs->enable = sh_cmt_clocksource_enable; | |
685 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 686 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 687 | cs->resume = sh_cmt_clocksource_resume; |
19bdc9d0 MD |
688 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
689 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 690 | |
740a9518 LP |
691 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
692 | ch->index); | |
f4d7c356 | 693 | |
3593f5fe MD |
694 | /* Register with dummy 1 Hz value, gets updated in ->enable() */ |
695 | clocksource_register_hz(cs, 1); | |
19bdc9d0 MD |
696 | return 0; |
697 | } | |
698 | ||
7269f933 | 699 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 700 | { |
7269f933 | 701 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
702 | } |
703 | ||
7269f933 | 704 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 705 | { |
7269f933 | 706 | struct clock_event_device *ced = &ch->ced; |
3fb1b6ad | 707 | |
7269f933 | 708 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
709 | |
710 | /* TODO: calculate good shift from rate and counter bit width */ | |
711 | ||
712 | ced->shift = 32; | |
7269f933 LP |
713 | ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift); |
714 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
3fb1b6ad MD |
715 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
716 | ||
717 | if (periodic) | |
7269f933 | 718 | sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 719 | else |
7269f933 | 720 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
721 | } |
722 | ||
723 | static void sh_cmt_clock_event_mode(enum clock_event_mode mode, | |
724 | struct clock_event_device *ced) | |
725 | { | |
7269f933 | 726 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
727 | |
728 | /* deal with old setting first */ | |
729 | switch (ced->mode) { | |
730 | case CLOCK_EVT_MODE_PERIODIC: | |
731 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 732 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
733 | break; |
734 | default: | |
735 | break; | |
736 | } | |
737 | ||
738 | switch (mode) { | |
739 | case CLOCK_EVT_MODE_PERIODIC: | |
7269f933 | 740 | dev_info(&ch->cmt->pdev->dev, |
740a9518 | 741 | "ch%u: used for periodic clock events\n", ch->index); |
7269f933 | 742 | sh_cmt_clock_event_start(ch, 1); |
3fb1b6ad MD |
743 | break; |
744 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 745 | dev_info(&ch->cmt->pdev->dev, |
740a9518 | 746 | "ch%u: used for oneshot clock events\n", ch->index); |
7269f933 | 747 | sh_cmt_clock_event_start(ch, 0); |
3fb1b6ad MD |
748 | break; |
749 | case CLOCK_EVT_MODE_SHUTDOWN: | |
750 | case CLOCK_EVT_MODE_UNUSED: | |
7269f933 | 751 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
752 | break; |
753 | default: | |
754 | break; | |
755 | } | |
756 | } | |
757 | ||
758 | static int sh_cmt_clock_event_next(unsigned long delta, | |
759 | struct clock_event_device *ced) | |
760 | { | |
7269f933 | 761 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
762 | |
763 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
7269f933 LP |
764 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
765 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 766 | else |
7269f933 | 767 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
768 | |
769 | return 0; | |
770 | } | |
771 | ||
9bb5ec88 RW |
772 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
773 | { | |
7269f933 | 774 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 775 | |
7269f933 LP |
776 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); |
777 | clk_unprepare(ch->cmt->clk); | |
9bb5ec88 RW |
778 | } |
779 | ||
780 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
781 | { | |
7269f933 | 782 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 783 | |
7269f933 LP |
784 | clk_prepare(ch->cmt->clk); |
785 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
786 | } |
787 | ||
bfa76bb1 LP |
788 | static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
789 | const char *name) | |
3fb1b6ad | 790 | { |
7269f933 | 791 | struct clock_event_device *ced = &ch->ced; |
bfa76bb1 LP |
792 | int irq; |
793 | int ret; | |
794 | ||
795 | irq = platform_get_irq(ch->cmt->pdev, ch->cmt->legacy ? 0 : ch->index); | |
796 | if (irq < 0) { | |
797 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n", | |
798 | ch->index); | |
799 | return irq; | |
800 | } | |
801 | ||
802 | ret = request_irq(irq, sh_cmt_interrupt, | |
803 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
804 | dev_name(&ch->cmt->pdev->dev), ch); | |
805 | if (ret) { | |
806 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", | |
807 | ch->index, irq); | |
808 | return ret; | |
809 | } | |
3fb1b6ad | 810 | |
3fb1b6ad MD |
811 | ced->name = name; |
812 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
813 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
b7fcbb0f | 814 | ced->rating = 125; |
f1ebe1e4 | 815 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad MD |
816 | ced->set_next_event = sh_cmt_clock_event_next; |
817 | ced->set_mode = sh_cmt_clock_event_mode; | |
9bb5ec88 RW |
818 | ced->suspend = sh_cmt_clock_event_suspend; |
819 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 820 | |
740a9518 LP |
821 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
822 | ch->index); | |
3fb1b6ad | 823 | clockevents_register_device(ced); |
bfa76bb1 LP |
824 | |
825 | return 0; | |
3fb1b6ad MD |
826 | } |
827 | ||
1d053e1d | 828 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
fb28a659 | 829 | bool clockevent, bool clocksource) |
3fb1b6ad | 830 | { |
bfa76bb1 LP |
831 | int ret; |
832 | ||
81b3b271 LP |
833 | if (clockevent) { |
834 | ch->cmt->has_clockevent = true; | |
bfa76bb1 LP |
835 | ret = sh_cmt_register_clockevent(ch, name); |
836 | if (ret < 0) | |
837 | return ret; | |
81b3b271 | 838 | } |
3fb1b6ad | 839 | |
81b3b271 LP |
840 | if (clocksource) { |
841 | ch->cmt->has_clocksource = true; | |
fb28a659 | 842 | sh_cmt_register_clocksource(ch, name); |
81b3b271 | 843 | } |
19bdc9d0 | 844 | |
3fb1b6ad MD |
845 | return 0; |
846 | } | |
847 | ||
740a9518 | 848 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
81b3b271 LP |
849 | unsigned int hwidx, bool clockevent, |
850 | bool clocksource, struct sh_cmt_device *cmt) | |
b882e7b1 | 851 | { |
b882e7b1 LP |
852 | int ret; |
853 | ||
81b3b271 LP |
854 | /* Skip unused channels. */ |
855 | if (!clockevent && !clocksource) | |
856 | return 0; | |
857 | ||
b882e7b1 | 858 | ch->cmt = cmt; |
740a9518 | 859 | ch->index = index; |
81b3b271 LP |
860 | ch->hwidx = hwidx; |
861 | ||
862 | /* | |
863 | * Compute the address of the channel control register block. For the | |
864 | * timers with a per-channel start/stop register, compute its address | |
865 | * as well. | |
866 | * | |
867 | * For legacy configuration the address has been mapped explicitly. | |
868 | */ | |
869 | if (cmt->legacy) { | |
870 | ch->ioctrl = cmt->mapbase_ch; | |
871 | } else { | |
872 | switch (cmt->info->model) { | |
873 | case SH_CMT_16BIT: | |
874 | ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; | |
875 | break; | |
876 | case SH_CMT_32BIT: | |
877 | case SH_CMT_48BIT: | |
878 | ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; | |
879 | break; | |
880 | case SH_CMT_32BIT_FAST: | |
881 | /* | |
882 | * The 32-bit "fast" timer has a single channel at hwidx | |
883 | * 5 but is located at offset 0x40 instead of 0x60 for | |
884 | * some reason. | |
885 | */ | |
886 | ch->ioctrl = cmt->mapbase + 0x40; | |
887 | break; | |
888 | case SH_CMT_48BIT_GEN2: | |
889 | ch->iostart = cmt->mapbase + ch->hwidx * 0x100; | |
890 | ch->ioctrl = ch->iostart + 0x10; | |
891 | break; | |
892 | } | |
893 | } | |
894 | ||
2cda3ac4 | 895 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
896 | ch->max_match_value = ~0; |
897 | else | |
2cda3ac4 | 898 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
899 | |
900 | ch->match_value = ch->max_match_value; | |
901 | raw_spin_lock_init(&ch->lock); | |
902 | ||
81b3b271 LP |
903 | if (cmt->legacy) { |
904 | ch->timer_bit = ch->hwidx; | |
905 | } else { | |
906 | ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 | |
907 | ? 0 : ch->hwidx; | |
908 | } | |
909 | ||
1d053e1d | 910 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
81b3b271 | 911 | clockevent, clocksource); |
b882e7b1 | 912 | if (ret) { |
740a9518 LP |
913 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
914 | ch->index); | |
b882e7b1 LP |
915 | return ret; |
916 | } | |
917 | ch->cs_enabled = false; | |
918 | ||
b882e7b1 LP |
919 | return 0; |
920 | } | |
921 | ||
81b3b271 | 922 | static int sh_cmt_map_memory(struct sh_cmt_device *cmt) |
3fb1b6ad | 923 | { |
81b3b271 | 924 | struct resource *mem; |
3fb1b6ad | 925 | |
81b3b271 LP |
926 | mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
927 | if (!mem) { | |
928 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); | |
929 | return -ENXIO; | |
930 | } | |
3fb1b6ad | 931 | |
81b3b271 LP |
932 | cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem)); |
933 | if (cmt->mapbase == NULL) { | |
934 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
935 | return -ENXIO; | |
3fb1b6ad MD |
936 | } |
937 | ||
81b3b271 LP |
938 | return 0; |
939 | } | |
940 | ||
941 | static int sh_cmt_map_memory_legacy(struct sh_cmt_device *cmt) | |
942 | { | |
943 | struct sh_timer_config *cfg = cmt->pdev->dev.platform_data; | |
944 | struct resource *res, *res2; | |
945 | ||
946 | /* map memory, let mapbase_ch point to our channel */ | |
2653caf4 | 947 | res = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
3fb1b6ad | 948 | if (!res) { |
2653caf4 | 949 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); |
81b3b271 | 950 | return -ENXIO; |
3fb1b6ad MD |
951 | } |
952 | ||
36f1ac98 LP |
953 | cmt->mapbase_ch = ioremap_nocache(res->start, resource_size(res)); |
954 | if (cmt->mapbase_ch == NULL) { | |
2653caf4 | 955 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); |
81b3b271 | 956 | return -ENXIO; |
3fb1b6ad MD |
957 | } |
958 | ||
81b3b271 LP |
959 | /* optional resource for the shared timer start/stop register */ |
960 | res2 = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 1); | |
961 | ||
8874c5e3 | 962 | /* map second resource for CMSTR */ |
36f1ac98 LP |
963 | cmt->mapbase = ioremap_nocache(res2 ? res2->start : |
964 | res->start - cfg->channel_offset, | |
965 | res2 ? resource_size(res2) : 2); | |
966 | if (cmt->mapbase == NULL) { | |
2653caf4 | 967 | dev_err(&cmt->pdev->dev, "failed to remap I/O second memory\n"); |
81b3b271 LP |
968 | iounmap(cmt->mapbase_ch); |
969 | return -ENXIO; | |
8874c5e3 MD |
970 | } |
971 | ||
81b3b271 LP |
972 | /* identify the model based on the resources */ |
973 | if (resource_size(res) == 6) | |
974 | cmt->info = &sh_cmt_info[SH_CMT_16BIT]; | |
975 | else if (res2 && (resource_size(res2) == 4)) | |
976 | cmt->info = &sh_cmt_info[SH_CMT_48BIT_GEN2]; | |
977 | else | |
978 | cmt->info = &sh_cmt_info[SH_CMT_32BIT]; | |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
983 | static void sh_cmt_unmap_memory(struct sh_cmt_device *cmt) | |
984 | { | |
985 | iounmap(cmt->mapbase); | |
986 | if (cmt->mapbase_ch) | |
987 | iounmap(cmt->mapbase_ch); | |
988 | } | |
989 | ||
990 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) | |
991 | { | |
992 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
993 | const struct platform_device_id *id = pdev->id_entry; | |
994 | unsigned int hw_channels; | |
995 | int ret; | |
996 | ||
997 | memset(cmt, 0, sizeof(*cmt)); | |
998 | cmt->pdev = pdev; | |
999 | ||
1000 | if (!cfg) { | |
1001 | dev_err(&cmt->pdev->dev, "missing platform data\n"); | |
1002 | return -ENXIO; | |
1003 | } | |
1004 | ||
1005 | cmt->info = (const struct sh_cmt_info *)id->driver_data; | |
1006 | cmt->legacy = cmt->info ? false : true; | |
1007 | ||
1008 | /* Get hold of clock. */ | |
24b4e07d | 1009 | cmt->clk = clk_get(&cmt->pdev->dev, cmt->legacy ? "cmt_fck" : "fck"); |
2653caf4 LP |
1010 | if (IS_ERR(cmt->clk)) { |
1011 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
81b3b271 | 1012 | return PTR_ERR(cmt->clk); |
3fb1b6ad MD |
1013 | } |
1014 | ||
2653caf4 | 1015 | ret = clk_prepare(cmt->clk); |
57dee992 | 1016 | if (ret < 0) |
81b3b271 | 1017 | goto err_clk_put; |
57dee992 | 1018 | |
81b3b271 LP |
1019 | /* |
1020 | * Map the memory resource(s). We need to support both the legacy | |
1021 | * platform device configuration (with one device per channel) and the | |
1022 | * new version (with multiple channels per device). | |
1023 | */ | |
1024 | if (cmt->legacy) | |
1025 | ret = sh_cmt_map_memory_legacy(cmt); | |
2cda3ac4 | 1026 | else |
81b3b271 | 1027 | ret = sh_cmt_map_memory(cmt); |
3fb1b6ad | 1028 | |
81b3b271 LP |
1029 | if (ret < 0) |
1030 | goto err_clk_unprepare; | |
1031 | ||
1032 | /* Allocate and setup the channels. */ | |
1033 | if (cmt->legacy) { | |
1034 | cmt->num_channels = 1; | |
1035 | hw_channels = 0; | |
1036 | } else { | |
1037 | cmt->num_channels = hweight8(cfg->channels_mask); | |
1038 | hw_channels = cfg->channels_mask; | |
1039 | } | |
1040 | ||
1041 | cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels), | |
1042 | GFP_KERNEL); | |
f5ec9b19 LP |
1043 | if (cmt->channels == NULL) { |
1044 | ret = -ENOMEM; | |
81b3b271 | 1045 | goto err_unmap; |
f5ec9b19 LP |
1046 | } |
1047 | ||
81b3b271 LP |
1048 | if (cmt->legacy) { |
1049 | ret = sh_cmt_setup_channel(&cmt->channels[0], | |
1050 | cfg->timer_bit, cfg->timer_bit, | |
1051 | cfg->clockevent_rating != 0, | |
1052 | cfg->clocksource_rating != 0, cmt); | |
1053 | if (ret < 0) | |
1054 | goto err_unmap; | |
1055 | } else { | |
1056 | unsigned int mask = hw_channels; | |
1057 | unsigned int i; | |
f5ec9b19 | 1058 | |
81b3b271 LP |
1059 | /* |
1060 | * Use the first channel as a clock event device and the second | |
1061 | * channel as a clock source. If only one channel is available | |
1062 | * use it for both. | |
1063 | */ | |
1064 | for (i = 0; i < cmt->num_channels; ++i) { | |
1065 | unsigned int hwidx = ffs(mask) - 1; | |
1066 | bool clocksource = i == 1 || cmt->num_channels == 1; | |
1067 | bool clockevent = i == 0; | |
1068 | ||
1069 | ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, | |
1070 | clockevent, clocksource, | |
1071 | cmt); | |
1072 | if (ret < 0) | |
1073 | goto err_unmap; | |
1074 | ||
1075 | mask &= ~(1 << hwidx); | |
1076 | } | |
1077 | } | |
da64c2a8 | 1078 | |
2653caf4 | 1079 | platform_set_drvdata(pdev, cmt); |
adccc69e | 1080 | |
da64c2a8 | 1081 | return 0; |
81b3b271 LP |
1082 | |
1083 | err_unmap: | |
f5ec9b19 | 1084 | kfree(cmt->channels); |
81b3b271 LP |
1085 | sh_cmt_unmap_memory(cmt); |
1086 | err_clk_unprepare: | |
2653caf4 | 1087 | clk_unprepare(cmt->clk); |
81b3b271 | 1088 | err_clk_put: |
2653caf4 | 1089 | clk_put(cmt->clk); |
3fb1b6ad MD |
1090 | return ret; |
1091 | } | |
1092 | ||
1850514b | 1093 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 1094 | { |
2653caf4 | 1095 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
3fb1b6ad MD |
1096 | int ret; |
1097 | ||
9bb5ec88 | 1098 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
1099 | pm_runtime_set_active(&pdev->dev); |
1100 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 1101 | } |
615a445f | 1102 | |
2653caf4 | 1103 | if (cmt) { |
214a607a | 1104 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 1105 | goto out; |
e475eedb MD |
1106 | } |
1107 | ||
b262bc74 | 1108 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
0178f41d | 1109 | if (cmt == NULL) |
3fb1b6ad | 1110 | return -ENOMEM; |
3fb1b6ad | 1111 | |
2653caf4 | 1112 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 1113 | if (ret) { |
2653caf4 | 1114 | kfree(cmt); |
bad81383 RW |
1115 | pm_runtime_idle(&pdev->dev); |
1116 | return ret; | |
3fb1b6ad | 1117 | } |
bad81383 RW |
1118 | if (is_early_platform_device(pdev)) |
1119 | return 0; | |
1120 | ||
1121 | out: | |
81b3b271 | 1122 | if (cmt->has_clockevent || cmt->has_clocksource) |
bad81383 RW |
1123 | pm_runtime_irq_safe(&pdev->dev); |
1124 | else | |
1125 | pm_runtime_idle(&pdev->dev); | |
1126 | ||
1127 | return 0; | |
3fb1b6ad MD |
1128 | } |
1129 | ||
1850514b | 1130 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
1131 | { |
1132 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
1133 | } | |
1134 | ||
81b3b271 LP |
1135 | static const struct platform_device_id sh_cmt_id_table[] = { |
1136 | { "sh_cmt", 0 }, | |
1137 | { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, | |
1138 | { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, | |
1139 | { "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] }, | |
1140 | { "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] }, | |
1141 | { "sh-cmt-48-gen2", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT_GEN2] }, | |
1142 | { } | |
1143 | }; | |
1144 | MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); | |
1145 | ||
3fb1b6ad MD |
1146 | static struct platform_driver sh_cmt_device_driver = { |
1147 | .probe = sh_cmt_probe, | |
1850514b | 1148 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
1149 | .driver = { |
1150 | .name = "sh_cmt", | |
81b3b271 LP |
1151 | }, |
1152 | .id_table = sh_cmt_id_table, | |
3fb1b6ad MD |
1153 | }; |
1154 | ||
1155 | static int __init sh_cmt_init(void) | |
1156 | { | |
1157 | return platform_driver_register(&sh_cmt_device_driver); | |
1158 | } | |
1159 | ||
1160 | static void __exit sh_cmt_exit(void) | |
1161 | { | |
1162 | platform_driver_unregister(&sh_cmt_device_driver); | |
1163 | } | |
1164 | ||
e475eedb | 1165 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
e903a031 | 1166 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1167 | module_exit(sh_cmt_exit); |
1168 | ||
1169 | MODULE_AUTHOR("Magnus Damm"); | |
1170 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
1171 | MODULE_LICENSE("GPL v2"); |