Commit | Line | Data |
---|---|---|
d5ed4c2e MD |
1 | /* |
2 | * SuperH Timer Support - MTU2 | |
3 | * | |
4 | * Copyright (C) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
d5ed4c2e MD |
14 | */ |
15 | ||
346f5e76 LP |
16 | #include <linux/clk.h> |
17 | #include <linux/clockchips.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/err.h> | |
d5ed4c2e | 20 | #include <linux/init.h> |
d5ed4c2e | 21 | #include <linux/interrupt.h> |
d5ed4c2e | 22 | #include <linux/io.h> |
346f5e76 | 23 | #include <linux/ioport.h> |
d5ed4c2e | 24 | #include <linux/irq.h> |
7deeab5d | 25 | #include <linux/module.h> |
cca8d059 | 26 | #include <linux/of.h> |
346f5e76 | 27 | #include <linux/platform_device.h> |
57d13370 | 28 | #include <linux/pm_domain.h> |
3cb6f10a | 29 | #include <linux/pm_runtime.h> |
346f5e76 LP |
30 | #include <linux/sh_timer.h> |
31 | #include <linux/slab.h> | |
32 | #include <linux/spinlock.h> | |
d5ed4c2e | 33 | |
7dad72de | 34 | struct sh_mtu2_device; |
42752cc6 LP |
35 | |
36 | struct sh_mtu2_channel { | |
7dad72de | 37 | struct sh_mtu2_device *mtu; |
d2b93177 | 38 | unsigned int index; |
da90a1c6 LP |
39 | |
40 | void __iomem *base; | |
da90a1c6 | 41 | |
42752cc6 LP |
42 | struct clock_event_device ced; |
43 | }; | |
44 | ||
7dad72de | 45 | struct sh_mtu2_device { |
42752cc6 LP |
46 | struct platform_device *pdev; |
47 | ||
d5ed4c2e MD |
48 | void __iomem *mapbase; |
49 | struct clk *clk; | |
42752cc6 | 50 | |
8b2463d8 LP |
51 | raw_spinlock_t lock; /* Protect the shared registers */ |
52 | ||
c54ccb43 LP |
53 | struct sh_mtu2_channel *channels; |
54 | unsigned int num_channels; | |
faf3f4f8 | 55 | |
faf3f4f8 | 56 | bool has_clockevent; |
d5ed4c2e MD |
57 | }; |
58 | ||
d5ed4c2e MD |
59 | #define TSTR -1 /* shared register */ |
60 | #define TCR 0 /* channel register */ | |
61 | #define TMDR 1 /* channel register */ | |
62 | #define TIOR 2 /* channel register */ | |
63 | #define TIER 3 /* channel register */ | |
64 | #define TSR 4 /* channel register */ | |
65 | #define TCNT 5 /* channel register */ | |
66 | #define TGR 6 /* channel register */ | |
67 | ||
f992c241 LP |
68 | #define TCR_CCLR_NONE (0 << 5) |
69 | #define TCR_CCLR_TGRA (1 << 5) | |
70 | #define TCR_CCLR_TGRB (2 << 5) | |
71 | #define TCR_CCLR_SYNC (3 << 5) | |
72 | #define TCR_CCLR_TGRC (5 << 5) | |
73 | #define TCR_CCLR_TGRD (6 << 5) | |
74 | #define TCR_CCLR_MASK (7 << 5) | |
75 | #define TCR_CKEG_RISING (0 << 3) | |
76 | #define TCR_CKEG_FALLING (1 << 3) | |
77 | #define TCR_CKEG_BOTH (2 << 3) | |
78 | #define TCR_CKEG_MASK (3 << 3) | |
79 | /* Values 4 to 7 are channel-dependent */ | |
80 | #define TCR_TPSC_P1 (0 << 0) | |
81 | #define TCR_TPSC_P4 (1 << 0) | |
82 | #define TCR_TPSC_P16 (2 << 0) | |
83 | #define TCR_TPSC_P64 (3 << 0) | |
84 | #define TCR_TPSC_CH0_TCLKA (4 << 0) | |
85 | #define TCR_TPSC_CH0_TCLKB (5 << 0) | |
86 | #define TCR_TPSC_CH0_TCLKC (6 << 0) | |
87 | #define TCR_TPSC_CH0_TCLKD (7 << 0) | |
88 | #define TCR_TPSC_CH1_TCLKA (4 << 0) | |
89 | #define TCR_TPSC_CH1_TCLKB (5 << 0) | |
90 | #define TCR_TPSC_CH1_P256 (6 << 0) | |
91 | #define TCR_TPSC_CH1_TCNT2 (7 << 0) | |
92 | #define TCR_TPSC_CH2_TCLKA (4 << 0) | |
93 | #define TCR_TPSC_CH2_TCLKB (5 << 0) | |
94 | #define TCR_TPSC_CH2_TCLKC (6 << 0) | |
95 | #define TCR_TPSC_CH2_P1024 (7 << 0) | |
96 | #define TCR_TPSC_CH34_P256 (4 << 0) | |
97 | #define TCR_TPSC_CH34_P1024 (5 << 0) | |
98 | #define TCR_TPSC_CH34_TCLKA (6 << 0) | |
99 | #define TCR_TPSC_CH34_TCLKB (7 << 0) | |
100 | #define TCR_TPSC_MASK (7 << 0) | |
101 | ||
102 | #define TMDR_BFE (1 << 6) | |
103 | #define TMDR_BFB (1 << 5) | |
104 | #define TMDR_BFA (1 << 4) | |
105 | #define TMDR_MD_NORMAL (0 << 0) | |
106 | #define TMDR_MD_PWM_1 (2 << 0) | |
107 | #define TMDR_MD_PWM_2 (3 << 0) | |
108 | #define TMDR_MD_PHASE_1 (4 << 0) | |
109 | #define TMDR_MD_PHASE_2 (5 << 0) | |
110 | #define TMDR_MD_PHASE_3 (6 << 0) | |
111 | #define TMDR_MD_PHASE_4 (7 << 0) | |
112 | #define TMDR_MD_PWM_SYNC (8 << 0) | |
113 | #define TMDR_MD_PWM_COMP_CREST (13 << 0) | |
114 | #define TMDR_MD_PWM_COMP_TROUGH (14 << 0) | |
115 | #define TMDR_MD_PWM_COMP_BOTH (15 << 0) | |
116 | #define TMDR_MD_MASK (15 << 0) | |
117 | ||
118 | #define TIOC_IOCH(n) ((n) << 4) | |
119 | #define TIOC_IOCL(n) ((n) << 0) | |
120 | #define TIOR_OC_RETAIN (0 << 0) | |
121 | #define TIOR_OC_0_CLEAR (1 << 0) | |
122 | #define TIOR_OC_0_SET (2 << 0) | |
123 | #define TIOR_OC_0_TOGGLE (3 << 0) | |
124 | #define TIOR_OC_1_CLEAR (5 << 0) | |
125 | #define TIOR_OC_1_SET (6 << 0) | |
126 | #define TIOR_OC_1_TOGGLE (7 << 0) | |
127 | #define TIOR_IC_RISING (8 << 0) | |
128 | #define TIOR_IC_FALLING (9 << 0) | |
129 | #define TIOR_IC_BOTH (10 << 0) | |
130 | #define TIOR_IC_TCNT (12 << 0) | |
131 | #define TIOR_MASK (15 << 0) | |
132 | ||
133 | #define TIER_TTGE (1 << 7) | |
134 | #define TIER_TTGE2 (1 << 6) | |
135 | #define TIER_TCIEU (1 << 5) | |
136 | #define TIER_TCIEV (1 << 4) | |
137 | #define TIER_TGIED (1 << 3) | |
138 | #define TIER_TGIEC (1 << 2) | |
139 | #define TIER_TGIEB (1 << 1) | |
140 | #define TIER_TGIEA (1 << 0) | |
141 | ||
142 | #define TSR_TCFD (1 << 7) | |
143 | #define TSR_TCFU (1 << 5) | |
144 | #define TSR_TCFV (1 << 4) | |
145 | #define TSR_TGFD (1 << 3) | |
146 | #define TSR_TGFC (1 << 2) | |
147 | #define TSR_TGFB (1 << 1) | |
148 | #define TSR_TGFA (1 << 0) | |
149 | ||
d5ed4c2e MD |
150 | static unsigned long mtu2_reg_offs[] = { |
151 | [TCR] = 0, | |
152 | [TMDR] = 1, | |
153 | [TIOR] = 2, | |
154 | [TIER] = 4, | |
155 | [TSR] = 5, | |
156 | [TCNT] = 6, | |
157 | [TGR] = 8, | |
158 | }; | |
159 | ||
42752cc6 | 160 | static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr) |
d5ed4c2e | 161 | { |
d5ed4c2e MD |
162 | unsigned long offs; |
163 | ||
1a5da0e4 LP |
164 | if (reg_nr == TSTR) |
165 | return ioread8(ch->mtu->mapbase + 0x280); | |
d5ed4c2e MD |
166 | |
167 | offs = mtu2_reg_offs[reg_nr]; | |
168 | ||
169 | if ((reg_nr == TCNT) || (reg_nr == TGR)) | |
da90a1c6 | 170 | return ioread16(ch->base + offs); |
d5ed4c2e | 171 | else |
da90a1c6 | 172 | return ioread8(ch->base + offs); |
d5ed4c2e MD |
173 | } |
174 | ||
42752cc6 | 175 | static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr, |
d5ed4c2e MD |
176 | unsigned long value) |
177 | { | |
d5ed4c2e MD |
178 | unsigned long offs; |
179 | ||
1a5da0e4 LP |
180 | if (reg_nr == TSTR) |
181 | return iowrite8(value, ch->mtu->mapbase + 0x280); | |
d5ed4c2e MD |
182 | |
183 | offs = mtu2_reg_offs[reg_nr]; | |
184 | ||
185 | if ((reg_nr == TCNT) || (reg_nr == TGR)) | |
da90a1c6 | 186 | iowrite16(value, ch->base + offs); |
d5ed4c2e | 187 | else |
da90a1c6 | 188 | iowrite8(value, ch->base + offs); |
d5ed4c2e MD |
189 | } |
190 | ||
42752cc6 | 191 | static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) |
d5ed4c2e | 192 | { |
d5ed4c2e MD |
193 | unsigned long flags, value; |
194 | ||
195 | /* start stop register shared by multiple timer channels */ | |
8b2463d8 | 196 | raw_spin_lock_irqsave(&ch->mtu->lock, flags); |
42752cc6 | 197 | value = sh_mtu2_read(ch, TSTR); |
d5ed4c2e MD |
198 | |
199 | if (start) | |
d2b93177 | 200 | value |= 1 << ch->index; |
d5ed4c2e | 201 | else |
d2b93177 | 202 | value &= ~(1 << ch->index); |
d5ed4c2e | 203 | |
42752cc6 | 204 | sh_mtu2_write(ch, TSTR, value); |
8b2463d8 | 205 | raw_spin_unlock_irqrestore(&ch->mtu->lock, flags); |
d5ed4c2e MD |
206 | } |
207 | ||
42752cc6 | 208 | static int sh_mtu2_enable(struct sh_mtu2_channel *ch) |
d5ed4c2e | 209 | { |
f92d62f5 LP |
210 | unsigned long periodic; |
211 | unsigned long rate; | |
d5ed4c2e MD |
212 | int ret; |
213 | ||
42752cc6 LP |
214 | pm_runtime_get_sync(&ch->mtu->pdev->dev); |
215 | dev_pm_syscore_device(&ch->mtu->pdev->dev, true); | |
3cb6f10a | 216 | |
d5ed4c2e | 217 | /* enable clock */ |
42752cc6 | 218 | ret = clk_enable(ch->mtu->clk); |
d5ed4c2e | 219 | if (ret) { |
d2b93177 LP |
220 | dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n", |
221 | ch->index); | |
d5ed4c2e MD |
222 | return ret; |
223 | } | |
224 | ||
225 | /* make sure channel is disabled */ | |
42752cc6 | 226 | sh_mtu2_start_stop_ch(ch, 0); |
d5ed4c2e | 227 | |
42752cc6 | 228 | rate = clk_get_rate(ch->mtu->clk) / 64; |
f92d62f5 | 229 | periodic = (rate + HZ/2) / HZ; |
d5ed4c2e | 230 | |
f992c241 LP |
231 | /* |
232 | * "Periodic Counter Operation" | |
233 | * Clear on TGRA compare match, divide clock by 64. | |
234 | */ | |
235 | sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64); | |
236 | sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) | | |
237 | TIOC_IOCL(TIOR_OC_0_CLEAR)); | |
42752cc6 LP |
238 | sh_mtu2_write(ch, TGR, periodic); |
239 | sh_mtu2_write(ch, TCNT, 0); | |
f992c241 LP |
240 | sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL); |
241 | sh_mtu2_write(ch, TIER, TIER_TGIEA); | |
d5ed4c2e MD |
242 | |
243 | /* enable channel */ | |
42752cc6 | 244 | sh_mtu2_start_stop_ch(ch, 1); |
d5ed4c2e MD |
245 | |
246 | return 0; | |
247 | } | |
248 | ||
42752cc6 | 249 | static void sh_mtu2_disable(struct sh_mtu2_channel *ch) |
d5ed4c2e MD |
250 | { |
251 | /* disable channel */ | |
42752cc6 | 252 | sh_mtu2_start_stop_ch(ch, 0); |
d5ed4c2e MD |
253 | |
254 | /* stop clock */ | |
42752cc6 | 255 | clk_disable(ch->mtu->clk); |
3cb6f10a | 256 | |
42752cc6 LP |
257 | dev_pm_syscore_device(&ch->mtu->pdev->dev, false); |
258 | pm_runtime_put(&ch->mtu->pdev->dev); | |
d5ed4c2e MD |
259 | } |
260 | ||
261 | static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id) | |
262 | { | |
42752cc6 | 263 | struct sh_mtu2_channel *ch = dev_id; |
d5ed4c2e MD |
264 | |
265 | /* acknowledge interrupt */ | |
42752cc6 | 266 | sh_mtu2_read(ch, TSR); |
f992c241 | 267 | sh_mtu2_write(ch, TSR, ~TSR_TGFA); |
d5ed4c2e MD |
268 | |
269 | /* notify clockevent layer */ | |
42752cc6 | 270 | ch->ced.event_handler(&ch->ced); |
d5ed4c2e MD |
271 | return IRQ_HANDLED; |
272 | } | |
273 | ||
42752cc6 | 274 | static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced) |
d5ed4c2e | 275 | { |
42752cc6 | 276 | return container_of(ced, struct sh_mtu2_channel, ced); |
d5ed4c2e MD |
277 | } |
278 | ||
19a9ffb3 | 279 | static int sh_mtu2_clock_event_shutdown(struct clock_event_device *ced) |
d5ed4c2e | 280 | { |
42752cc6 | 281 | struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced); |
d5ed4c2e | 282 | |
fe326c5c MD |
283 | if (clockevent_state_periodic(ced)) |
284 | sh_mtu2_disable(ch); | |
285 | ||
19a9ffb3 VK |
286 | return 0; |
287 | } | |
288 | ||
289 | static int sh_mtu2_clock_event_set_periodic(struct clock_event_device *ced) | |
290 | { | |
291 | struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced); | |
292 | ||
293 | if (clockevent_state_periodic(ced)) | |
42752cc6 | 294 | sh_mtu2_disable(ch); |
d5ed4c2e | 295 | |
19a9ffb3 VK |
296 | dev_info(&ch->mtu->pdev->dev, "ch%u: used for periodic clock events\n", |
297 | ch->index); | |
298 | sh_mtu2_enable(ch); | |
299 | return 0; | |
d5ed4c2e MD |
300 | } |
301 | ||
cc7ad456 RW |
302 | static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced) |
303 | { | |
42752cc6 | 304 | pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev); |
cc7ad456 RW |
305 | } |
306 | ||
307 | static void sh_mtu2_clock_event_resume(struct clock_event_device *ced) | |
308 | { | |
42752cc6 | 309 | pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev); |
cc7ad456 RW |
310 | } |
311 | ||
42752cc6 | 312 | static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch, |
207e21a9 | 313 | const char *name) |
d5ed4c2e | 314 | { |
42752cc6 | 315 | struct clock_event_device *ced = &ch->ced; |
d5ed4c2e | 316 | |
d5ed4c2e MD |
317 | ced->name = name; |
318 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
207e21a9 | 319 | ced->rating = 200; |
3cc95047 | 320 | ced->cpumask = cpu_possible_mask; |
19a9ffb3 VK |
321 | ced->set_state_shutdown = sh_mtu2_clock_event_shutdown; |
322 | ced->set_state_periodic = sh_mtu2_clock_event_set_periodic; | |
cc7ad456 RW |
323 | ced->suspend = sh_mtu2_clock_event_suspend; |
324 | ced->resume = sh_mtu2_clock_event_resume; | |
d5ed4c2e | 325 | |
d2b93177 LP |
326 | dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n", |
327 | ch->index); | |
da64c2a8 | 328 | clockevents_register_device(ced); |
d5ed4c2e MD |
329 | } |
330 | ||
1a5da0e4 | 331 | static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name) |
d5ed4c2e | 332 | { |
1a5da0e4 LP |
333 | ch->mtu->has_clockevent = true; |
334 | sh_mtu2_register_clockevent(ch, name); | |
d5ed4c2e MD |
335 | |
336 | return 0; | |
337 | } | |
338 | ||
faf3f4f8 | 339 | static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index, |
2e1a5326 LP |
340 | struct sh_mtu2_device *mtu) |
341 | { | |
faf3f4f8 LP |
342 | static const unsigned int channel_offsets[] = { |
343 | 0x300, 0x380, 0x000, | |
344 | }; | |
1a5da0e4 LP |
345 | char name[6]; |
346 | int irq; | |
347 | int ret; | |
2e1a5326 | 348 | |
2e1a5326 LP |
349 | ch->mtu = mtu; |
350 | ||
1a5da0e4 LP |
351 | sprintf(name, "tgi%ua", index); |
352 | irq = platform_get_irq_byname(mtu->pdev, name); | |
353 | if (irq < 0) { | |
faf3f4f8 | 354 | /* Skip channels with no declared interrupt. */ |
1a5da0e4 LP |
355 | return 0; |
356 | } | |
faf3f4f8 | 357 | |
1a5da0e4 LP |
358 | ret = request_irq(irq, sh_mtu2_interrupt, |
359 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
360 | dev_name(&ch->mtu->pdev->dev), ch); | |
361 | if (ret) { | |
362 | dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n", | |
363 | index, irq); | |
364 | return ret; | |
2e1a5326 LP |
365 | } |
366 | ||
1a5da0e4 LP |
367 | ch->base = mtu->mapbase + channel_offsets[index]; |
368 | ch->index = index; | |
369 | ||
370 | return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev)); | |
2e1a5326 LP |
371 | } |
372 | ||
faf3f4f8 | 373 | static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu) |
d5ed4c2e | 374 | { |
d5ed4c2e | 375 | struct resource *res; |
d5ed4c2e | 376 | |
7dad72de | 377 | res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0); |
d5ed4c2e | 378 | if (!res) { |
7dad72de | 379 | dev_err(&mtu->pdev->dev, "failed to get I/O memory\n"); |
faf3f4f8 | 380 | return -ENXIO; |
d5ed4c2e MD |
381 | } |
382 | ||
faf3f4f8 LP |
383 | mtu->mapbase = ioremap_nocache(res->start, resource_size(res)); |
384 | if (mtu->mapbase == NULL) | |
385 | return -ENXIO; | |
386 | ||
faf3f4f8 LP |
387 | return 0; |
388 | } | |
389 | ||
faf3f4f8 LP |
390 | static int sh_mtu2_setup(struct sh_mtu2_device *mtu, |
391 | struct platform_device *pdev) | |
392 | { | |
faf3f4f8 LP |
393 | unsigned int i; |
394 | int ret; | |
395 | ||
396 | mtu->pdev = pdev; | |
da90a1c6 | 397 | |
8b2463d8 LP |
398 | raw_spin_lock_init(&mtu->lock); |
399 | ||
faf3f4f8 | 400 | /* Get hold of clock. */ |
1a5da0e4 | 401 | mtu->clk = clk_get(&mtu->pdev->dev, "fck"); |
7dad72de LP |
402 | if (IS_ERR(mtu->clk)) { |
403 | dev_err(&mtu->pdev->dev, "cannot get clock\n"); | |
faf3f4f8 | 404 | return PTR_ERR(mtu->clk); |
d5ed4c2e MD |
405 | } |
406 | ||
7dad72de | 407 | ret = clk_prepare(mtu->clk); |
bd754930 | 408 | if (ret < 0) |
faf3f4f8 | 409 | goto err_clk_put; |
bd754930 | 410 | |
faf3f4f8 LP |
411 | /* Map the memory resource. */ |
412 | ret = sh_mtu2_map_memory(mtu); | |
413 | if (ret < 0) { | |
414 | dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n"); | |
415 | goto err_clk_unprepare; | |
416 | } | |
417 | ||
418 | /* Allocate and setup the channels. */ | |
1a5da0e4 | 419 | mtu->num_channels = 3; |
faf3f4f8 LP |
420 | |
421 | mtu->channels = kzalloc(sizeof(*mtu->channels) * mtu->num_channels, | |
422 | GFP_KERNEL); | |
c54ccb43 LP |
423 | if (mtu->channels == NULL) { |
424 | ret = -ENOMEM; | |
faf3f4f8 | 425 | goto err_unmap; |
c54ccb43 LP |
426 | } |
427 | ||
1a5da0e4 LP |
428 | for (i = 0; i < mtu->num_channels; ++i) { |
429 | ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu); | |
faf3f4f8 LP |
430 | if (ret < 0) |
431 | goto err_unmap; | |
faf3f4f8 | 432 | } |
c54ccb43 | 433 | |
faf3f4f8 | 434 | platform_set_drvdata(pdev, mtu); |
a4a5fc3b LP |
435 | |
436 | return 0; | |
faf3f4f8 LP |
437 | |
438 | err_unmap: | |
c54ccb43 | 439 | kfree(mtu->channels); |
1a5da0e4 | 440 | iounmap(mtu->mapbase); |
faf3f4f8 | 441 | err_clk_unprepare: |
7dad72de | 442 | clk_unprepare(mtu->clk); |
faf3f4f8 | 443 | err_clk_put: |
7dad72de | 444 | clk_put(mtu->clk); |
d5ed4c2e MD |
445 | return ret; |
446 | } | |
447 | ||
1850514b | 448 | static int sh_mtu2_probe(struct platform_device *pdev) |
d5ed4c2e | 449 | { |
7dad72de | 450 | struct sh_mtu2_device *mtu = platform_get_drvdata(pdev); |
d5ed4c2e | 451 | int ret; |
57d13370 | 452 | |
cc7ad456 | 453 | if (!is_early_platform_device(pdev)) { |
3cb6f10a RW |
454 | pm_runtime_set_active(&pdev->dev); |
455 | pm_runtime_enable(&pdev->dev); | |
cc7ad456 | 456 | } |
d5ed4c2e | 457 | |
7dad72de | 458 | if (mtu) { |
214a607a | 459 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
3cb6f10a | 460 | goto out; |
d5ed4c2e MD |
461 | } |
462 | ||
810c6513 | 463 | mtu = kzalloc(sizeof(*mtu), GFP_KERNEL); |
c77a565b | 464 | if (mtu == NULL) |
d5ed4c2e | 465 | return -ENOMEM; |
d5ed4c2e | 466 | |
7dad72de | 467 | ret = sh_mtu2_setup(mtu, pdev); |
d5ed4c2e | 468 | if (ret) { |
7dad72de | 469 | kfree(mtu); |
3cb6f10a RW |
470 | pm_runtime_idle(&pdev->dev); |
471 | return ret; | |
d5ed4c2e | 472 | } |
3cb6f10a RW |
473 | if (is_early_platform_device(pdev)) |
474 | return 0; | |
475 | ||
476 | out: | |
faf3f4f8 | 477 | if (mtu->has_clockevent) |
3cb6f10a RW |
478 | pm_runtime_irq_safe(&pdev->dev); |
479 | else | |
480 | pm_runtime_idle(&pdev->dev); | |
481 | ||
482 | return 0; | |
d5ed4c2e MD |
483 | } |
484 | ||
1850514b | 485 | static int sh_mtu2_remove(struct platform_device *pdev) |
d5ed4c2e MD |
486 | { |
487 | return -EBUSY; /* cannot unregister clockevent */ | |
488 | } | |
489 | ||
faf3f4f8 | 490 | static const struct platform_device_id sh_mtu2_id_table[] = { |
faf3f4f8 LP |
491 | { "sh-mtu2", 0 }, |
492 | { }, | |
493 | }; | |
494 | MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table); | |
495 | ||
cca8d059 LP |
496 | static const struct of_device_id sh_mtu2_of_table[] __maybe_unused = { |
497 | { .compatible = "renesas,mtu2" }, | |
498 | { } | |
499 | }; | |
500 | MODULE_DEVICE_TABLE(of, sh_mtu2_of_table); | |
501 | ||
d5ed4c2e MD |
502 | static struct platform_driver sh_mtu2_device_driver = { |
503 | .probe = sh_mtu2_probe, | |
1850514b | 504 | .remove = sh_mtu2_remove, |
d5ed4c2e MD |
505 | .driver = { |
506 | .name = "sh_mtu2", | |
cca8d059 | 507 | .of_match_table = of_match_ptr(sh_mtu2_of_table), |
faf3f4f8 LP |
508 | }, |
509 | .id_table = sh_mtu2_id_table, | |
d5ed4c2e MD |
510 | }; |
511 | ||
512 | static int __init sh_mtu2_init(void) | |
513 | { | |
514 | return platform_driver_register(&sh_mtu2_device_driver); | |
515 | } | |
516 | ||
517 | static void __exit sh_mtu2_exit(void) | |
518 | { | |
519 | platform_driver_unregister(&sh_mtu2_device_driver); | |
520 | } | |
521 | ||
522 | early_platform_init("earlytimer", &sh_mtu2_device_driver); | |
342896a5 | 523 | subsys_initcall(sh_mtu2_init); |
d5ed4c2e MD |
524 | module_exit(sh_mtu2_exit); |
525 | ||
526 | MODULE_AUTHOR("Magnus Damm"); | |
527 | MODULE_DESCRIPTION("SuperH MTU2 Timer Driver"); | |
528 | MODULE_LICENSE("GPL v2"); |