Commit | Line | Data |
---|---|---|
9570ef20 MD |
1 | /* |
2 | * SuperH Timer Support - TMU | |
3 | * | |
4 | * Copyright (C) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/clocksource.h> | |
31 | #include <linux/clockchips.h> | |
46a12f74 | 32 | #include <linux/sh_timer.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
7deeab5d | 34 | #include <linux/module.h> |
2ee619f9 | 35 | #include <linux/pm_domain.h> |
eaa49a8c | 36 | #include <linux/pm_runtime.h> |
9570ef20 | 37 | |
0a72aa39 | 38 | struct sh_tmu_device; |
de2d12c7 LP |
39 | |
40 | struct sh_tmu_channel { | |
0a72aa39 | 41 | struct sh_tmu_device *tmu; |
de2d12c7 | 42 | |
1c56cf6b | 43 | int irq; |
de2d12c7 | 44 | |
9570ef20 MD |
45 | unsigned long rate; |
46 | unsigned long periodic; | |
47 | struct clock_event_device ced; | |
48 | struct clocksource cs; | |
eaa49a8c | 49 | bool cs_enabled; |
61a53bfa | 50 | unsigned int enable_count; |
9570ef20 MD |
51 | }; |
52 | ||
0a72aa39 | 53 | struct sh_tmu_device { |
de2d12c7 LP |
54 | struct platform_device *pdev; |
55 | ||
56 | void __iomem *mapbase; | |
57 | struct clk *clk; | |
58 | ||
59 | struct sh_tmu_channel channel; | |
60 | }; | |
61 | ||
c2225a57 | 62 | static DEFINE_RAW_SPINLOCK(sh_tmu_lock); |
9570ef20 MD |
63 | |
64 | #define TSTR -1 /* shared register */ | |
65 | #define TCOR 0 /* channel register */ | |
66 | #define TCNT 1 /* channel register */ | |
67 | #define TCR 2 /* channel register */ | |
68 | ||
de2d12c7 | 69 | static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) |
9570ef20 | 70 | { |
de2d12c7 LP |
71 | struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data; |
72 | void __iomem *base = ch->tmu->mapbase; | |
9570ef20 MD |
73 | unsigned long offs; |
74 | ||
75 | if (reg_nr == TSTR) | |
76 | return ioread8(base - cfg->channel_offset); | |
77 | ||
78 | offs = reg_nr << 2; | |
79 | ||
80 | if (reg_nr == TCR) | |
81 | return ioread16(base + offs); | |
82 | else | |
83 | return ioread32(base + offs); | |
84 | } | |
85 | ||
de2d12c7 | 86 | static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, |
9570ef20 MD |
87 | unsigned long value) |
88 | { | |
de2d12c7 LP |
89 | struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data; |
90 | void __iomem *base = ch->tmu->mapbase; | |
9570ef20 MD |
91 | unsigned long offs; |
92 | ||
93 | if (reg_nr == TSTR) { | |
94 | iowrite8(value, base - cfg->channel_offset); | |
95 | return; | |
96 | } | |
97 | ||
98 | offs = reg_nr << 2; | |
99 | ||
100 | if (reg_nr == TCR) | |
101 | iowrite16(value, base + offs); | |
102 | else | |
103 | iowrite32(value, base + offs); | |
104 | } | |
105 | ||
de2d12c7 | 106 | static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) |
9570ef20 | 107 | { |
de2d12c7 | 108 | struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data; |
9570ef20 MD |
109 | unsigned long flags, value; |
110 | ||
111 | /* start stop register shared by multiple timer channels */ | |
c2225a57 | 112 | raw_spin_lock_irqsave(&sh_tmu_lock, flags); |
de2d12c7 | 113 | value = sh_tmu_read(ch, TSTR); |
9570ef20 MD |
114 | |
115 | if (start) | |
116 | value |= 1 << cfg->timer_bit; | |
117 | else | |
118 | value &= ~(1 << cfg->timer_bit); | |
119 | ||
de2d12c7 | 120 | sh_tmu_write(ch, TSTR, value); |
c2225a57 | 121 | raw_spin_unlock_irqrestore(&sh_tmu_lock, flags); |
9570ef20 MD |
122 | } |
123 | ||
de2d12c7 | 124 | static int __sh_tmu_enable(struct sh_tmu_channel *ch) |
9570ef20 | 125 | { |
9570ef20 MD |
126 | int ret; |
127 | ||
d4905ce3 | 128 | /* enable clock */ |
de2d12c7 | 129 | ret = clk_enable(ch->tmu->clk); |
9570ef20 | 130 | if (ret) { |
de2d12c7 | 131 | dev_err(&ch->tmu->pdev->dev, "cannot enable clock\n"); |
9570ef20 MD |
132 | return ret; |
133 | } | |
134 | ||
135 | /* make sure channel is disabled */ | |
de2d12c7 | 136 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 MD |
137 | |
138 | /* maximum timeout */ | |
de2d12c7 LP |
139 | sh_tmu_write(ch, TCOR, 0xffffffff); |
140 | sh_tmu_write(ch, TCNT, 0xffffffff); | |
9570ef20 MD |
141 | |
142 | /* configure channel to parent clock / 4, irq off */ | |
de2d12c7 LP |
143 | ch->rate = clk_get_rate(ch->tmu->clk) / 4; |
144 | sh_tmu_write(ch, TCR, 0x0000); | |
9570ef20 MD |
145 | |
146 | /* enable channel */ | |
de2d12c7 | 147 | sh_tmu_start_stop_ch(ch, 1); |
9570ef20 MD |
148 | |
149 | return 0; | |
150 | } | |
151 | ||
de2d12c7 | 152 | static int sh_tmu_enable(struct sh_tmu_channel *ch) |
61a53bfa | 153 | { |
de2d12c7 | 154 | if (ch->enable_count++ > 0) |
61a53bfa RW |
155 | return 0; |
156 | ||
de2d12c7 LP |
157 | pm_runtime_get_sync(&ch->tmu->pdev->dev); |
158 | dev_pm_syscore_device(&ch->tmu->pdev->dev, true); | |
61a53bfa | 159 | |
de2d12c7 | 160 | return __sh_tmu_enable(ch); |
61a53bfa RW |
161 | } |
162 | ||
de2d12c7 | 163 | static void __sh_tmu_disable(struct sh_tmu_channel *ch) |
9570ef20 MD |
164 | { |
165 | /* disable channel */ | |
de2d12c7 | 166 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 | 167 | |
be890a1a | 168 | /* disable interrupts in TMU block */ |
de2d12c7 | 169 | sh_tmu_write(ch, TCR, 0x0000); |
be890a1a | 170 | |
d4905ce3 | 171 | /* stop clock */ |
de2d12c7 | 172 | clk_disable(ch->tmu->clk); |
9570ef20 MD |
173 | } |
174 | ||
de2d12c7 | 175 | static void sh_tmu_disable(struct sh_tmu_channel *ch) |
61a53bfa | 176 | { |
de2d12c7 | 177 | if (WARN_ON(ch->enable_count == 0)) |
61a53bfa RW |
178 | return; |
179 | ||
de2d12c7 | 180 | if (--ch->enable_count > 0) |
61a53bfa RW |
181 | return; |
182 | ||
de2d12c7 | 183 | __sh_tmu_disable(ch); |
61a53bfa | 184 | |
de2d12c7 LP |
185 | dev_pm_syscore_device(&ch->tmu->pdev->dev, false); |
186 | pm_runtime_put(&ch->tmu->pdev->dev); | |
61a53bfa RW |
187 | } |
188 | ||
de2d12c7 | 189 | static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, |
9570ef20 MD |
190 | int periodic) |
191 | { | |
192 | /* stop timer */ | |
de2d12c7 | 193 | sh_tmu_start_stop_ch(ch, 0); |
9570ef20 MD |
194 | |
195 | /* acknowledge interrupt */ | |
de2d12c7 | 196 | sh_tmu_read(ch, TCR); |
9570ef20 MD |
197 | |
198 | /* enable interrupt */ | |
de2d12c7 | 199 | sh_tmu_write(ch, TCR, 0x0020); |
9570ef20 MD |
200 | |
201 | /* reload delta value in case of periodic timer */ | |
202 | if (periodic) | |
de2d12c7 | 203 | sh_tmu_write(ch, TCOR, delta); |
9570ef20 | 204 | else |
de2d12c7 | 205 | sh_tmu_write(ch, TCOR, 0xffffffff); |
9570ef20 | 206 | |
de2d12c7 | 207 | sh_tmu_write(ch, TCNT, delta); |
9570ef20 MD |
208 | |
209 | /* start timer */ | |
de2d12c7 | 210 | sh_tmu_start_stop_ch(ch, 1); |
9570ef20 MD |
211 | } |
212 | ||
213 | static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id) | |
214 | { | |
de2d12c7 | 215 | struct sh_tmu_channel *ch = dev_id; |
9570ef20 MD |
216 | |
217 | /* disable or acknowledge interrupt */ | |
de2d12c7 LP |
218 | if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) |
219 | sh_tmu_write(ch, TCR, 0x0000); | |
9570ef20 | 220 | else |
de2d12c7 | 221 | sh_tmu_write(ch, TCR, 0x0020); |
9570ef20 MD |
222 | |
223 | /* notify clockevent layer */ | |
de2d12c7 | 224 | ch->ced.event_handler(&ch->ced); |
9570ef20 MD |
225 | return IRQ_HANDLED; |
226 | } | |
227 | ||
de2d12c7 | 228 | static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) |
9570ef20 | 229 | { |
de2d12c7 | 230 | return container_of(cs, struct sh_tmu_channel, cs); |
9570ef20 MD |
231 | } |
232 | ||
233 | static cycle_t sh_tmu_clocksource_read(struct clocksource *cs) | |
234 | { | |
de2d12c7 | 235 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
9570ef20 | 236 | |
de2d12c7 | 237 | return sh_tmu_read(ch, TCNT) ^ 0xffffffff; |
9570ef20 MD |
238 | } |
239 | ||
240 | static int sh_tmu_clocksource_enable(struct clocksource *cs) | |
241 | { | |
de2d12c7 | 242 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
0aeac458 | 243 | int ret; |
9570ef20 | 244 | |
de2d12c7 | 245 | if (WARN_ON(ch->cs_enabled)) |
61a53bfa RW |
246 | return 0; |
247 | ||
de2d12c7 | 248 | ret = sh_tmu_enable(ch); |
eaa49a8c | 249 | if (!ret) { |
de2d12c7 LP |
250 | __clocksource_updatefreq_hz(cs, ch->rate); |
251 | ch->cs_enabled = true; | |
eaa49a8c | 252 | } |
61a53bfa | 253 | |
0aeac458 | 254 | return ret; |
9570ef20 MD |
255 | } |
256 | ||
257 | static void sh_tmu_clocksource_disable(struct clocksource *cs) | |
258 | { | |
de2d12c7 | 259 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 260 | |
de2d12c7 | 261 | if (WARN_ON(!ch->cs_enabled)) |
61a53bfa | 262 | return; |
eaa49a8c | 263 | |
de2d12c7 LP |
264 | sh_tmu_disable(ch); |
265 | ch->cs_enabled = false; | |
eaa49a8c RW |
266 | } |
267 | ||
268 | static void sh_tmu_clocksource_suspend(struct clocksource *cs) | |
269 | { | |
de2d12c7 | 270 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 271 | |
de2d12c7 | 272 | if (!ch->cs_enabled) |
61a53bfa | 273 | return; |
eaa49a8c | 274 | |
de2d12c7 LP |
275 | if (--ch->enable_count == 0) { |
276 | __sh_tmu_disable(ch); | |
277 | pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev); | |
61a53bfa | 278 | } |
eaa49a8c RW |
279 | } |
280 | ||
281 | static void sh_tmu_clocksource_resume(struct clocksource *cs) | |
282 | { | |
de2d12c7 | 283 | struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
eaa49a8c | 284 | |
de2d12c7 | 285 | if (!ch->cs_enabled) |
61a53bfa RW |
286 | return; |
287 | ||
de2d12c7 LP |
288 | if (ch->enable_count++ == 0) { |
289 | pm_genpd_syscore_poweron(&ch->tmu->pdev->dev); | |
290 | __sh_tmu_enable(ch); | |
61a53bfa | 291 | } |
9570ef20 MD |
292 | } |
293 | ||
de2d12c7 | 294 | static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, |
9570ef20 MD |
295 | char *name, unsigned long rating) |
296 | { | |
de2d12c7 | 297 | struct clocksource *cs = &ch->cs; |
9570ef20 MD |
298 | |
299 | cs->name = name; | |
300 | cs->rating = rating; | |
301 | cs->read = sh_tmu_clocksource_read; | |
302 | cs->enable = sh_tmu_clocksource_enable; | |
303 | cs->disable = sh_tmu_clocksource_disable; | |
eaa49a8c RW |
304 | cs->suspend = sh_tmu_clocksource_suspend; |
305 | cs->resume = sh_tmu_clocksource_resume; | |
9570ef20 MD |
306 | cs->mask = CLOCKSOURCE_MASK(32); |
307 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
66f49121 | 308 | |
de2d12c7 | 309 | dev_info(&ch->tmu->pdev->dev, "used as clock source\n"); |
0aeac458 MD |
310 | |
311 | /* Register with dummy 1 Hz value, gets updated in ->enable() */ | |
312 | clocksource_register_hz(cs, 1); | |
9570ef20 MD |
313 | return 0; |
314 | } | |
315 | ||
de2d12c7 | 316 | static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) |
9570ef20 | 317 | { |
de2d12c7 | 318 | return container_of(ced, struct sh_tmu_channel, ced); |
9570ef20 MD |
319 | } |
320 | ||
de2d12c7 | 321 | static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic) |
9570ef20 | 322 | { |
de2d12c7 | 323 | struct clock_event_device *ced = &ch->ced; |
9570ef20 | 324 | |
de2d12c7 | 325 | sh_tmu_enable(ch); |
9570ef20 | 326 | |
de2d12c7 | 327 | clockevents_config(ced, ch->rate); |
9570ef20 MD |
328 | |
329 | if (periodic) { | |
de2d12c7 LP |
330 | ch->periodic = (ch->rate + HZ/2) / HZ; |
331 | sh_tmu_set_next(ch, ch->periodic, 1); | |
9570ef20 MD |
332 | } |
333 | } | |
334 | ||
335 | static void sh_tmu_clock_event_mode(enum clock_event_mode mode, | |
336 | struct clock_event_device *ced) | |
337 | { | |
de2d12c7 | 338 | struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
9570ef20 MD |
339 | int disabled = 0; |
340 | ||
341 | /* deal with old setting first */ | |
342 | switch (ced->mode) { | |
343 | case CLOCK_EVT_MODE_PERIODIC: | |
344 | case CLOCK_EVT_MODE_ONESHOT: | |
de2d12c7 | 345 | sh_tmu_disable(ch); |
9570ef20 MD |
346 | disabled = 1; |
347 | break; | |
348 | default: | |
349 | break; | |
350 | } | |
351 | ||
352 | switch (mode) { | |
353 | case CLOCK_EVT_MODE_PERIODIC: | |
de2d12c7 LP |
354 | dev_info(&ch->tmu->pdev->dev, |
355 | "used for periodic clock events\n"); | |
356 | sh_tmu_clock_event_start(ch, 1); | |
9570ef20 MD |
357 | break; |
358 | case CLOCK_EVT_MODE_ONESHOT: | |
de2d12c7 LP |
359 | dev_info(&ch->tmu->pdev->dev, |
360 | "used for oneshot clock events\n"); | |
361 | sh_tmu_clock_event_start(ch, 0); | |
9570ef20 MD |
362 | break; |
363 | case CLOCK_EVT_MODE_UNUSED: | |
364 | if (!disabled) | |
de2d12c7 | 365 | sh_tmu_disable(ch); |
9570ef20 MD |
366 | break; |
367 | case CLOCK_EVT_MODE_SHUTDOWN: | |
368 | default: | |
369 | break; | |
370 | } | |
371 | } | |
372 | ||
373 | static int sh_tmu_clock_event_next(unsigned long delta, | |
374 | struct clock_event_device *ced) | |
375 | { | |
de2d12c7 | 376 | struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
9570ef20 MD |
377 | |
378 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
379 | ||
380 | /* program new delta value */ | |
de2d12c7 | 381 | sh_tmu_set_next(ch, delta, 0); |
9570ef20 MD |
382 | return 0; |
383 | } | |
384 | ||
eaa49a8c RW |
385 | static void sh_tmu_clock_event_suspend(struct clock_event_device *ced) |
386 | { | |
de2d12c7 | 387 | pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev); |
eaa49a8c RW |
388 | } |
389 | ||
390 | static void sh_tmu_clock_event_resume(struct clock_event_device *ced) | |
391 | { | |
de2d12c7 | 392 | pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev); |
eaa49a8c RW |
393 | } |
394 | ||
de2d12c7 | 395 | static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, |
9570ef20 MD |
396 | char *name, unsigned long rating) |
397 | { | |
de2d12c7 | 398 | struct clock_event_device *ced = &ch->ced; |
9570ef20 MD |
399 | int ret; |
400 | ||
401 | memset(ced, 0, sizeof(*ced)); | |
402 | ||
403 | ced->name = name; | |
404 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
405 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
406 | ced->rating = rating; | |
407 | ced->cpumask = cpumask_of(0); | |
408 | ced->set_next_event = sh_tmu_clock_event_next; | |
409 | ced->set_mode = sh_tmu_clock_event_mode; | |
eaa49a8c RW |
410 | ced->suspend = sh_tmu_clock_event_suspend; |
411 | ced->resume = sh_tmu_clock_event_resume; | |
9570ef20 | 412 | |
de2d12c7 | 413 | dev_info(&ch->tmu->pdev->dev, "used for clock events\n"); |
3977407e PM |
414 | |
415 | clockevents_config_and_register(ced, 1, 0x300, 0xffffffff); | |
da64c2a8 | 416 | |
de2d12c7 | 417 | ret = request_irq(ch->irq, sh_tmu_interrupt, |
1c56cf6b | 418 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, |
de2d12c7 | 419 | dev_name(&ch->tmu->pdev->dev), ch); |
9570ef20 | 420 | if (ret) { |
de2d12c7 LP |
421 | dev_err(&ch->tmu->pdev->dev, "failed to request irq %d\n", |
422 | ch->irq); | |
9570ef20 MD |
423 | return; |
424 | } | |
9570ef20 MD |
425 | } |
426 | ||
de2d12c7 | 427 | static int sh_tmu_register(struct sh_tmu_channel *ch, char *name, |
9570ef20 MD |
428 | unsigned long clockevent_rating, |
429 | unsigned long clocksource_rating) | |
430 | { | |
431 | if (clockevent_rating) | |
de2d12c7 | 432 | sh_tmu_register_clockevent(ch, name, clockevent_rating); |
9570ef20 | 433 | else if (clocksource_rating) |
de2d12c7 | 434 | sh_tmu_register_clocksource(ch, name, clocksource_rating); |
9570ef20 MD |
435 | |
436 | return 0; | |
437 | } | |
438 | ||
0a72aa39 | 439 | static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) |
9570ef20 | 440 | { |
46a12f74 | 441 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
9570ef20 | 442 | struct resource *res; |
1c56cf6b | 443 | int ret; |
9570ef20 MD |
444 | ret = -ENXIO; |
445 | ||
0a72aa39 LP |
446 | memset(tmu, 0, sizeof(*tmu)); |
447 | tmu->pdev = pdev; | |
9570ef20 MD |
448 | |
449 | if (!cfg) { | |
0a72aa39 | 450 | dev_err(&tmu->pdev->dev, "missing platform data\n"); |
9570ef20 MD |
451 | goto err0; |
452 | } | |
453 | ||
0a72aa39 | 454 | platform_set_drvdata(pdev, tmu); |
9570ef20 | 455 | |
0a72aa39 | 456 | res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); |
9570ef20 | 457 | if (!res) { |
0a72aa39 | 458 | dev_err(&tmu->pdev->dev, "failed to get I/O memory\n"); |
9570ef20 MD |
459 | goto err0; |
460 | } | |
461 | ||
0a72aa39 LP |
462 | tmu->channel.irq = platform_get_irq(tmu->pdev, 0); |
463 | if (tmu->channel.irq < 0) { | |
464 | dev_err(&tmu->pdev->dev, "failed to get irq\n"); | |
9570ef20 MD |
465 | goto err0; |
466 | } | |
467 | ||
468 | /* map memory, let mapbase point to our channel */ | |
0a72aa39 LP |
469 | tmu->mapbase = ioremap_nocache(res->start, resource_size(res)); |
470 | if (tmu->mapbase == NULL) { | |
471 | dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n"); | |
9570ef20 MD |
472 | goto err0; |
473 | } | |
474 | ||
9570ef20 | 475 | /* get hold of clock */ |
0a72aa39 LP |
476 | tmu->clk = clk_get(&tmu->pdev->dev, "tmu_fck"); |
477 | if (IS_ERR(tmu->clk)) { | |
478 | dev_err(&tmu->pdev->dev, "cannot get clock\n"); | |
479 | ret = PTR_ERR(tmu->clk); | |
03ff858c | 480 | goto err1; |
9570ef20 | 481 | } |
1c09eb3e | 482 | |
0a72aa39 | 483 | ret = clk_prepare(tmu->clk); |
1c09eb3e LP |
484 | if (ret < 0) |
485 | goto err2; | |
486 | ||
0a72aa39 LP |
487 | tmu->channel.cs_enabled = false; |
488 | tmu->channel.enable_count = 0; | |
489 | tmu->channel.tmu = tmu; | |
9570ef20 | 490 | |
0a72aa39 | 491 | ret = sh_tmu_register(&tmu->channel, (char *)dev_name(&tmu->pdev->dev), |
394a4486 LP |
492 | cfg->clockevent_rating, |
493 | cfg->clocksource_rating); | |
494 | if (ret < 0) | |
1c09eb3e | 495 | goto err3; |
394a4486 LP |
496 | |
497 | return 0; | |
498 | ||
1c09eb3e | 499 | err3: |
0a72aa39 | 500 | clk_unprepare(tmu->clk); |
394a4486 | 501 | err2: |
0a72aa39 | 502 | clk_put(tmu->clk); |
9570ef20 | 503 | err1: |
0a72aa39 | 504 | iounmap(tmu->mapbase); |
9570ef20 MD |
505 | err0: |
506 | return ret; | |
507 | } | |
508 | ||
1850514b | 509 | static int sh_tmu_probe(struct platform_device *pdev) |
9570ef20 | 510 | { |
0a72aa39 | 511 | struct sh_tmu_device *tmu = platform_get_drvdata(pdev); |
61a53bfa | 512 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
9570ef20 MD |
513 | int ret; |
514 | ||
eaa49a8c | 515 | if (!is_early_platform_device(pdev)) { |
61a53bfa RW |
516 | pm_runtime_set_active(&pdev->dev); |
517 | pm_runtime_enable(&pdev->dev); | |
eaa49a8c | 518 | } |
2ee619f9 | 519 | |
0a72aa39 | 520 | if (tmu) { |
214a607a | 521 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
61a53bfa | 522 | goto out; |
9570ef20 MD |
523 | } |
524 | ||
0a72aa39 LP |
525 | tmu = kmalloc(sizeof(*tmu), GFP_KERNEL); |
526 | if (tmu == NULL) { | |
9570ef20 MD |
527 | dev_err(&pdev->dev, "failed to allocate driver data\n"); |
528 | return -ENOMEM; | |
529 | } | |
530 | ||
0a72aa39 | 531 | ret = sh_tmu_setup(tmu, pdev); |
9570ef20 | 532 | if (ret) { |
0a72aa39 | 533 | kfree(tmu); |
61a53bfa RW |
534 | pm_runtime_idle(&pdev->dev); |
535 | return ret; | |
9570ef20 | 536 | } |
61a53bfa RW |
537 | if (is_early_platform_device(pdev)) |
538 | return 0; | |
539 | ||
540 | out: | |
541 | if (cfg->clockevent_rating || cfg->clocksource_rating) | |
542 | pm_runtime_irq_safe(&pdev->dev); | |
543 | else | |
544 | pm_runtime_idle(&pdev->dev); | |
545 | ||
546 | return 0; | |
9570ef20 MD |
547 | } |
548 | ||
1850514b | 549 | static int sh_tmu_remove(struct platform_device *pdev) |
9570ef20 MD |
550 | { |
551 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
552 | } | |
553 | ||
554 | static struct platform_driver sh_tmu_device_driver = { | |
555 | .probe = sh_tmu_probe, | |
1850514b | 556 | .remove = sh_tmu_remove, |
9570ef20 MD |
557 | .driver = { |
558 | .name = "sh_tmu", | |
559 | } | |
560 | }; | |
561 | ||
562 | static int __init sh_tmu_init(void) | |
563 | { | |
564 | return platform_driver_register(&sh_tmu_device_driver); | |
565 | } | |
566 | ||
567 | static void __exit sh_tmu_exit(void) | |
568 | { | |
569 | platform_driver_unregister(&sh_tmu_device_driver); | |
570 | } | |
571 | ||
572 | early_platform_init("earlytimer", &sh_tmu_device_driver); | |
b9773c3f | 573 | subsys_initcall(sh_tmu_init); |
9570ef20 MD |
574 | module_exit(sh_tmu_exit); |
575 | ||
576 | MODULE_AUTHOR("Magnus Damm"); | |
577 | MODULE_DESCRIPTION("SuperH TMU Timer Driver"); | |
578 | MODULE_LICENSE("GPL v2"); |