[deliverable/linux.git] / drivers / clocksource / sun4i_timer.c

/*
 * Allwinner A1X SoCs timer handling.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * Based on code from
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Benn Huang <benn@allwinnertech.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TIMER_IRQ_EN_REG	0x00
#define TIMER_IRQ_EN(val)		BIT(val)
#define TIMER_IRQ_ST_REG	0x04
#define TIMER_CTL_REG(val)	(0x10 * val + 0x10)
#define TIMER_CTL_ENABLE		BIT(0)
#define TIMER_CTL_RELOAD		BIT(1)
#define TIMER_CTL_ONESHOT		BIT(7)
#define TIMER_INTVAL_REG(val)	(0x10 * (val) + 0x14)
#define TIMER_CNTVAL_REG(val)	(0x10 * (val) + 0x18)

#define TIMER_SCAL		16

static void __iomem *timer_base;

/*
 * When we disable a timer, we need to wait at least for 2 cycles of
 * the timer source clock. We will use for that the clocksource timer
 * that is already setup and runs at the same frequency than the other
 * timers, and we never will be disabled.
 */
static void sun4i_clkevt_sync(void)
{
	u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));

	while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
		cpu_relax();
}

static void sun4i_clkevt_mode(enum clock_event_mode mode,
			      struct clock_event_device *clk)
{
	u32 u = readl(timer_base + TIMER_CTL_REG(0));

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		u &= ~(TIMER_CTL_ONESHOT);
		writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
		break;
	}
}

static int sun4i_clkevt_next_event(unsigned long evt,
				   struct clock_event_device *unused)
{
	u32 val = readl(timer_base + TIMER_CTL_REG(0));
	writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
	sun4i_clkevt_sync();

	writel(evt, timer_base + TIMER_INTVAL_REG(0));

	val = readl(timer_base + TIMER_CTL_REG(0));
	writel(val | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
	       timer_base + TIMER_CTL_REG(0));

	return 0;
}

static struct clock_event_device sun4i_clockevent = {
	.name = "sun4i_tick",
	.rating = 300,
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode = sun4i_clkevt_mode,
	.set_next_event = sun4i_clkevt_next_event,
};


static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;

	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction sun4i_timer_irq = {
	.name = "sun4i_timer0",
	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler = sun4i_timer_interrupt,
	.dev_id = &sun4i_clockevent,
};

static u32 sun4i_timer_sched_read(void)
{
	return ~readl(timer_base + TIMER_CNTVAL_REG(1));
}

static void __init sun4i_timer_init(struct device_node *node)
{
	unsigned long rate = 0;
	struct clk *clk;
	int ret, irq;
	u32 val;

	timer_base = of_iomap(node, 0);
	if (!timer_base)
		panic("Can't map registers");

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0)
		panic("Can't parse IRQ");

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk))
		panic("Can't get timer clock");
	clk_prepare_enable(clk);

	rate = clk_get_rate(clk);

	writel(~0, timer_base + TIMER_INTVAL_REG(1));
	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
	       TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	       timer_base + TIMER_CTL_REG(1));

	setup_sched_clock(sun4i_timer_sched_read, 32, rate);
	clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
			      rate, 300, 32, clocksource_mmio_readl_down);

	writel(rate / (TIMER_SCAL * HZ),
	       timer_base + TIMER_INTVAL_REG(0));

	/* set clock source to HOSC, 16 pre-division */
	val = readl(timer_base + TIMER_CTL_REG(0));
	val &= ~(0x07 << 4);
	val &= ~(0x03 << 2);
	val |= (4 << 4) | (1 << 2);
	writel(val, timer_base + TIMER_CTL_REG(0));

	/* set mode to auto reload */
	val = readl(timer_base + TIMER_CTL_REG(0));
	writel(val | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));

	ret = setup_irq(irq, &sun4i_timer_irq);
	if (ret)
		pr_warn("failed to setup irq %d\n", irq);

	/* Enable timer0 interrupt */
	val = readl(timer_base + TIMER_IRQ_EN_REG);
	writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);

	sun4i_clockevent.cpumask = cpumask_of(0);

	clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
					0x1, 0xff);
}
CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
		       sun4i_timer_init);
Commit	Line	Data
b2ac5d75 MR	1	/*
	2	* Allwinner A1X SoCs timer handling.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* Based on code from
	9	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	10	* Benn Huang <benn@allwinnertech.com>
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/irq.h>
	21	#include <linux/irqreturn.h>
137c6b3c	22	#include <linux/sched_clock.h>
b2ac5d75 MR	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
b2ac5d75	26
04981731	27	#define TIMER_IRQ_EN_REG 0x00
40777645	28	#define TIMER_IRQ_EN(val) BIT(val)
b2ac5d75	29	#define TIMER_IRQ_ST_REG 0x04
04981731	30	#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
40777645	31	#define TIMER_CTL_ENABLE BIT(0)
9eded232	32	#define TIMER_CTL_RELOAD BIT(1)
40777645	33	#define TIMER_CTL_ONESHOT BIT(7)
bb008b9e MR	34	#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
bb008b9e MR	35	#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
b2ac5d75 MR	36
	37	#define TIMER_SCAL 16
	38
	39	static void __iomem *timer_base;
	40
63d88f1a MR	41	/*
	42	* When we disable a timer, we need to wait at least for 2 cycles of
	43	* the timer source clock. We will use for that the clocksource timer
	44	* that is already setup and runs at the same frequency than the other
	45	* timers, and we never will be disabled.
	46	*/
	47	static void sun4i_clkevt_sync(void)
	48	{
	49	u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
	50
	51	while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
	52	cpu_relax();
	53	}
	54
119fd635	55	static void sun4i_clkevt_mode(enum clock_event_mode mode,
b2ac5d75 MR	56	struct clock_event_device *clk)
b2ac5d75 MR	57	{
04981731	58	u32 u = readl(timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	59
	60	switch (mode) {
	61	case CLOCK_EVT_MODE_PERIODIC:
04981731 MR	62	u &= ~(TIMER_CTL_ONESHOT);
04981731 MR	63	writel(u \| TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	64	break;
	65
	66	case CLOCK_EVT_MODE_ONESHOT:
04981731	67	writel(u \| TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	68	break;
	69	case CLOCK_EVT_MODE_UNUSED:
	70	case CLOCK_EVT_MODE_SHUTDOWN:
	71	default:
04981731	72	writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	73	break;
	74	}
	75	}
	76
119fd635	77	static int sun4i_clkevt_next_event(unsigned long evt,
b2ac5d75 MR	78	struct clock_event_device *unused)
b2ac5d75 MR	79	{
63d88f1a MR	80	u32 val = readl(timer_base + TIMER_CTL_REG(0));
	81	writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
	82	sun4i_clkevt_sync();
	83
	84	writel(evt, timer_base + TIMER_INTVAL_REG(0));
	85
	86	val = readl(timer_base + TIMER_CTL_REG(0));
	87	writel(val \| TIMER_CTL_ENABLE \| TIMER_CTL_AUTORELOAD,
04981731	88	timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	89
	90	return 0;
	91	}
	92
119fd635 MR	93	static struct clock_event_device sun4i_clockevent = {
119fd635 MR	94	.name = "sun4i_tick",
b2ac5d75 MR	95	.rating = 300,
b2ac5d75 MR	96	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
119fd635 MR	97	.set_mode = sun4i_clkevt_mode,
119fd635 MR	98	.set_next_event = sun4i_clkevt_next_event,
b2ac5d75 MR	99	};
	100
	101
119fd635	102	static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
b2ac5d75 MR	103	{
	104	struct clock_event_device evt = (struct clock_event_device )dev_id;
	105
	106	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	107	evt->event_handler(evt);
	108
	109	return IRQ_HANDLED;
	110	}
	111
119fd635 MR	112	static struct irqaction sun4i_timer_irq = {
119fd635 MR	113	.name = "sun4i_timer0",
b2ac5d75	114	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
119fd635 MR	115	.handler = sun4i_timer_interrupt,
119fd635 MR	116	.dev_id = &sun4i_clockevent,
b2ac5d75 MR	117	};
b2ac5d75 MR	118
137c6b3c MR	119	static u32 sun4i_timer_sched_read(void)
	120	{
	121	return ~readl(timer_base + TIMER_CNTVAL_REG(1));
	122	}
	123
119fd635	124	static void __init sun4i_timer_init(struct device_node *node)
b2ac5d75	125	{
b2ac5d75 MR	126	unsigned long rate = 0;
	127	struct clk *clk;
	128	int ret, irq;
	129	u32 val;
	130
b2ac5d75 MR	131	timer_base = of_iomap(node, 0);
	132	if (!timer_base)
	133	panic("Can't map registers");
	134
	135	irq = irq_of_parse_and_map(node, 0);
	136	if (irq <= 0)
	137	panic("Can't parse IRQ");
	138
b2ac5d75 MR	139	clk = of_clk_get(node, 0);
	140	if (IS_ERR(clk))
	141	panic("Can't get timer clock");
8c31bec2	142	clk_prepare_enable(clk);
b2ac5d75 MR	143
	144	rate = clk_get_rate(clk);
	145
137c6b3c MR	146	writel(~0, timer_base + TIMER_INTVAL_REG(1));
	147	writel(TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD \|
	148	TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	149	timer_base + TIMER_CTL_REG(1));
	150
	151	setup_sched_clock(sun4i_timer_sched_read, 32, rate);
	152	clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
	153	rate, 300, 32, clocksource_mmio_readl_down);
	154
b2ac5d75	155	writel(rate / (TIMER_SCAL * HZ),
04981731	156	timer_base + TIMER_INTVAL_REG(0));
b2ac5d75 MR	157
b2ac5d75 MR	158	/* set clock source to HOSC, 16 pre-division */
04981731	159	val = readl(timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	160	val &= ~(0x07 << 4);
	161	val &= ~(0x03 << 2);
	162	val \|= (4 << 4) \| (1 << 2);
04981731	163	writel(val, timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	164
b2ac5d75 MR	165	/* set mode to auto reload */
04981731	166	val = readl(timer_base + TIMER_CTL_REG(0));
9eded232	167	writel(val \| TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));
b2ac5d75	168
119fd635	169	ret = setup_irq(irq, &sun4i_timer_irq);
b2ac5d75 MR	170	if (ret)
	171	pr_warn("failed to setup irq %d\n", irq);
	172
	173	/* Enable timer0 interrupt */
04981731 MR	174	val = readl(timer_base + TIMER_IRQ_EN_REG);
04981731 MR	175	writel(val \| TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
b2ac5d75	176
119fd635	177	sun4i_clockevent.cpumask = cpumask_of(0);
b2ac5d75	178
119fd635	179	clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
77cc982f	180	0x1, 0xff);
b2ac5d75	181	}
119fd635 MR	182	CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
119fd635 MR	183	sun4i_timer_init);