[deliverable/linux.git] / drivers / clocksource / tcb_clksrc.c

#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/atmel_tc.h>


/*
 * We're configured to use a specific TC block, one that's not hooked
 * up to external hardware, to provide a time solution:
 *
 *   - Two channels combine to create a free-running 32 bit counter
 *     with a base rate of 5+ MHz, packaged as a clocksource (with
 *     resolution better than 200 nsec).
 *   - Some chips support 32 bit counter. A single channel is used for
 *     this 32 bit free-running counter. the second channel is not used.
 *
 *   - The third channel may be used to provide a 16-bit clockevent
 *     source, used in either periodic or oneshot mode.  This runs
 *     at 32 KiHZ, and can handle delays of up to two seconds.
 *
 * A boot clocksource and clockevent source are also currently needed,
 * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
 * this code can be used when init_timers() is called, well before most
 * devices are set up.  (Some low end AT91 parts, which can run uClinux,
 * have only the timers in one TC block... they currently don't support
 * the tclib code, because of that initialization issue.)
 *
 * REVISIT behavior during system suspend states... we should disable
 * all clocks and save the power.  Easily done for clockevent devices,
 * but clocksources won't necessarily get the needed notifications.
 * For deeper system sleep states, this will be mandatory...
 */

static void __iomem *tcaddr;

static cycle_t tc_get_cycles(struct clocksource *cs)
{
	unsigned long	flags;
	u32		lower, upper;

	raw_local_irq_save(flags);
	do {
		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));

	raw_local_irq_restore(flags);
	return (upper << 16) | lower;
}

static cycle_t tc_get_cycles32(struct clocksource *cs)
{
	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
}

static struct clocksource clksrc = {
	.name           = "tcb_clksrc",
	.rating         = 200,
	.read           = tc_get_cycles,
	.mask           = CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

#ifdef CONFIG_GENERIC_CLOCKEVENTS

struct tc_clkevt_device {
	struct clock_event_device	clkevt;
	struct clk			*clk;
	void __iomem			*regs;
};

static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
{
	return container_of(clkevt, struct tc_clkevt_device, clkevt);
}

/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
 * because using one of the divided clocks would usually mean the
 * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
 *
 * A divided clock could be good for high resolution timers, since
 * 30.5 usec resolution can seem "low".
 */
static u32 timer_clock;

static int tc_shutdown(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
	__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
	clk_disable(tcd->clk);

	return 0;
}

static int tc_set_oneshot(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
		tc_shutdown(d);

	clk_enable(tcd->clk);

	/* slow clock, count up to RC, then irq and stop */
	__raw_writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
		     ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
	__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));

	/* set_next_event() configures and starts the timer */
	return 0;
}

static int tc_set_periodic(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
		tc_shutdown(d);

	/* By not making the gentime core emulate periodic mode on top
	 * of oneshot, we get lower overhead and improved accuracy.
	 */
	clk_enable(tcd->clk);

	/* slow clock, count up to RC, then irq and restart */
	__raw_writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
		     regs + ATMEL_TC_REG(2, CMR));
	__raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));

	/* Enable clock and interrupts on RC compare */
	__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));

	/* go go gadget! */
	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
		     ATMEL_TC_REG(2, CCR));
	return 0;
}

static int tc_next_event(unsigned long delta, struct clock_event_device *d)
{
	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));

	/* go go gadget! */
	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
			tcaddr + ATMEL_TC_REG(2, CCR));
	return 0;
}

static struct tc_clkevt_device clkevt = {
	.clkevt	= {
		.name			= "tc_clkevt",
		.features		= CLOCK_EVT_FEAT_PERIODIC |
					  CLOCK_EVT_FEAT_ONESHOT,
		/* Should be lower than at91rm9200's system timer */
		.rating			= 125,
		.set_next_event		= tc_next_event,
		.set_state_shutdown	= tc_shutdown,
		.set_state_periodic	= tc_set_periodic,
		.set_state_oneshot	= tc_set_oneshot,
	},
};

static irqreturn_t ch2_irq(int irq, void *handle)
{
	struct tc_clkevt_device	*dev = handle;
	unsigned int		sr;

	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
	if (sr & ATMEL_TC_CPCS) {
		dev->clkevt.event_handler(&dev->clkevt);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
{
	int ret;
	struct clk *t2_clk = tc->clk[2];
	int irq = tc->irq[2];

	ret = clk_prepare_enable(tc->slow_clk);
	if (ret)
		return ret;

	/* try to enable t2 clk to avoid future errors in mode change */
	ret = clk_prepare_enable(t2_clk);
	if (ret) {
		clk_disable_unprepare(tc->slow_clk);
		return ret;
	}

	clk_disable(t2_clk);

	clkevt.regs = tc->regs;
	clkevt.clk = t2_clk;

	timer_clock = clk32k_divisor_idx;

	clkevt.clkevt.cpumask = cpumask_of(0);

	ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
	if (ret) {
		clk_unprepare(t2_clk);
		clk_disable_unprepare(tc->slow_clk);
		return ret;
	}

	clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);

	return ret;
}

#else /* !CONFIG_GENERIC_CLOCKEVENTS */

static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
{
	/* NOTHING */
	return 0;
}

#endif

static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
{
	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP		/* free-run */
			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
			tcaddr + ATMEL_TC_REG(0, CMR));
	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));

	/* channel 1:  waveform mode, input TIOA0 */
	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP,		/* free-run */
			tcaddr + ATMEL_TC_REG(1, CMR));
	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));

	/* chain channel 0 to channel 1*/
	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
	/* then reset all the timers */
	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
{
	/* channel 0:  waveform mode, input mclk/8 */
	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP,		/* free-run */
			tcaddr + ATMEL_TC_REG(0, CMR));
	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));

	/* then reset all the timers */
	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static int __init tcb_clksrc_init(void)
{
	static char bootinfo[] __initdata
		= KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";

	struct platform_device *pdev;
	struct atmel_tc *tc;
	struct clk *t0_clk;
	u32 rate, divided_rate = 0;
	int best_divisor_idx = -1;
	int clk32k_divisor_idx = -1;
	int i;
	int ret;

	tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
	if (!tc) {
		pr_debug("can't alloc TC for clocksource\n");
		return -ENODEV;
	}
	tcaddr = tc->regs;
	pdev = tc->pdev;

	t0_clk = tc->clk[0];
	ret = clk_prepare_enable(t0_clk);
	if (ret) {
		pr_debug("can't enable T0 clk\n");
		goto err_free_tc;
	}

	/* How fast will we be counting?  Pick something over 5 MHz.  */
	rate = (u32) clk_get_rate(t0_clk);
	for (i = 0; i < 5; i++) {
		unsigned divisor = atmel_tc_divisors[i];
		unsigned tmp;

		/* remember 32 KiHz clock for later */
		if (!divisor) {
			clk32k_divisor_idx = i;
			continue;
		}

		tmp = rate / divisor;
		pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
		if (best_divisor_idx > 0) {
			if (tmp < 5 * 1000 * 1000)
				continue;
		}
		divided_rate = tmp;
		best_divisor_idx = i;
	}


	printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
			divided_rate / 1000000,
			((divided_rate + 500000) % 1000000) / 1000);

	if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
		/* use apropriate function to read 32 bit counter */
		clksrc.read = tc_get_cycles32;
		/* setup ony channel 0 */
		tcb_setup_single_chan(tc, best_divisor_idx);
	} else {
		/* tclib will give us three clocks no matter what the
		 * underlying platform supports.
		 */
		ret = clk_prepare_enable(tc->clk[1]);
		if (ret) {
			pr_debug("can't enable T1 clk\n");
			goto err_disable_t0;
		}
		/* setup both channel 0 & 1 */
		tcb_setup_dual_chan(tc, best_divisor_idx);
	}

	/* and away we go! */
	ret = clocksource_register_hz(&clksrc, divided_rate);
	if (ret)
		goto err_disable_t1;

	/* channel 2:  periodic and oneshot timer support */
	ret = setup_clkevents(tc, clk32k_divisor_idx);
	if (ret)
		goto err_unregister_clksrc;

	return 0;

err_unregister_clksrc:
	clocksource_unregister(&clksrc);

err_disable_t1:
	if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
		clk_disable_unprepare(tc->clk[1]);

err_disable_t0:
	clk_disable_unprepare(t0_clk);

err_free_tc:
	atmel_tc_free(tc);
	return ret;
}
arch_initcall(tcb_clksrc_init);
Commit	Line	Data
4d243f92 DB	1	#include <linux/init.h>
	2	#include <linux/clocksource.h>
	3	#include <linux/clockchips.h>
	4	#include <linux/interrupt.h>
	5	#include <linux/irq.h>
	6
	7	#include <linux/clk.h>
	8	#include <linux/err.h>
	9	#include <linux/ioport.h>
	10	#include <linux/io.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/atmel_tc.h>
	13
	14
	15	/*
	16	* We're configured to use a specific TC block, one that's not hooked
	17	* up to external hardware, to provide a time solution:
	18	*
	19	* - Two channels combine to create a free-running 32 bit counter
	20	* with a base rate of 5+ MHz, packaged as a clocksource (with
	21	* resolution better than 200 nsec).
8e315a7b NF	22	* - Some chips support 32 bit counter. A single channel is used for
8e315a7b NF	23	* this 32 bit free-running counter. the second channel is not used.
4d243f92 DB	24	*
	25	* - The third channel may be used to provide a 16-bit clockevent
	26	* source, used in either periodic or oneshot mode. This runs
	27	* at 32 KiHZ, and can handle delays of up to two seconds.
	28	*
	29	* A boot clocksource and clockevent source are also currently needed,
	30	* unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
	31	* this code can be used when init_timers() is called, well before most
	32	* devices are set up. (Some low end AT91 parts, which can run uClinux,
	33	* have only the timers in one TC block... they currently don't support
	34	* the tclib code, because of that initialization issue.)
	35	*
	36	* REVISIT behavior during system suspend states... we should disable
	37	* all clocks and save the power. Easily done for clockevent devices,
	38	* but clocksources won't necessarily get the needed notifications.
	39	* For deeper system sleep states, this will be mandatory...
	40	*/
	41
	42	static void __iomem *tcaddr;
	43
8e19608e	44	static cycle_t tc_get_cycles(struct clocksource *cs)
4d243f92 DB	45	{
	46	unsigned long flags;
	47	u32 lower, upper;
	48
	49	raw_local_irq_save(flags);
	50	do {
	51	upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
	52	lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
	53	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
	54
	55	raw_local_irq_restore(flags);
	56	return (upper << 16) \| lower;
	57	}
	58
8e315a7b NF	59	static cycle_t tc_get_cycles32(struct clocksource *cs)
	60	{
	61	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
	62	}
	63
4d243f92 DB	64	static struct clocksource clksrc = {
	65	.name = "tcb_clksrc",
	66	.rating = 200,
	67	.read = tc_get_cycles,
	68	.mask = CLOCKSOURCE_MASK(32),
4d243f92 DB	69	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	70	};
	71
	72	#ifdef CONFIG_GENERIC_CLOCKEVENTS
	73
	74	struct tc_clkevt_device {
	75	struct clock_event_device clkevt;
	76	struct clk *clk;
	77	void __iomem *regs;
	78	};
	79
	80	static struct tc_clkevt_device to_tc_clkevt(struct clock_event_device clkevt)
	81	{
	82	return container_of(clkevt, struct tc_clkevt_device, clkevt);
	83	}
	84
	85	/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
	86	* because using one of the divided clocks would usually mean the
	87	* tick rate can never be less than several dozen Hz (vs 0.5 Hz).
	88	*
	89	* A divided clock could be good for high resolution timers, since
	90	* 30.5 usec resolution can seem "low".
	91	*/
	92	static u32 timer_clock;
	93
cf4541c1	94	static int tc_shutdown(struct clock_event_device *d)
4d243f92 DB	95	{
	96	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	97	void __iomem *regs = tcd->regs;
	98
cf4541c1 VK	99	__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
	100	__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
	101	clk_disable(tcd->clk);
4d243f92	102
cf4541c1 VK	103	return 0;
cf4541c1 VK	104	}
4d243f92	105
cf4541c1 VK	106	static int tc_set_oneshot(struct clock_event_device *d)
	107	{
	108	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	109	void __iomem *regs = tcd->regs;
4d243f92	110
cf4541c1 VK	111	if (clockevent_state_oneshot(d) \|\| clockevent_state_periodic(d))
cf4541c1 VK	112	tc_shutdown(d);
4d243f92	113
cf4541c1	114	clk_enable(tcd->clk);
4d243f92	115
cf4541c1 VK	116	/* slow clock, count up to RC, then irq and stop */
	117	__raw_writel(timer_clock \| ATMEL_TC_CPCSTOP \| ATMEL_TC_WAVE \|
	118	ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
	119	__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
4d243f92	120
cf4541c1 VK	121	/* set_next_event() configures and starts the timer */
	122	return 0;
	123	}
4d243f92	124
cf4541c1 VK	125	static int tc_set_periodic(struct clock_event_device *d)
	126	{
	127	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	128	void __iomem *regs = tcd->regs;
4d243f92	129
cf4541c1 VK	130	if (clockevent_state_oneshot(d) \|\| clockevent_state_periodic(d))
cf4541c1 VK	131	tc_shutdown(d);
4d243f92	132
cf4541c1 VK	133	/* By not making the gentime core emulate periodic mode on top
	134	* of oneshot, we get lower overhead and improved accuracy.
	135	*/
	136	clk_enable(tcd->clk);
	137
	138	/* slow clock, count up to RC, then irq and restart */
	139	__raw_writel(timer_clock \| ATMEL_TC_WAVE \| ATMEL_TC_WAVESEL_UP_AUTO,
	140	regs + ATMEL_TC_REG(2, CMR));
	141	__raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
	142
	143	/* Enable clock and interrupts on RC compare */
	144	__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
	145
	146	/* go go gadget! */
	147	__raw_writel(ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG, regs +
	148	ATMEL_TC_REG(2, CCR));
	149	return 0;
4d243f92 DB	150	}
	151
	152	static int tc_next_event(unsigned long delta, struct clock_event_device *d)
	153	{
	154	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
	155
	156	/* go go gadget! */
	157	__raw_writel(ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG,
	158	tcaddr + ATMEL_TC_REG(2, CCR));
	159	return 0;
	160	}
	161
	162	static struct tc_clkevt_device clkevt = {
	163	.clkevt = {
cf4541c1 VK	164	.name = "tc_clkevt",
	165	.features = CLOCK_EVT_FEAT_PERIODIC \|
	166	CLOCK_EVT_FEAT_ONESHOT,
4d243f92	167	/* Should be lower than at91rm9200's system timer */
cf4541c1 VK	168	.rating = 125,
	169	.set_next_event = tc_next_event,
	170	.set_state_shutdown = tc_shutdown,
	171	.set_state_periodic = tc_set_periodic,
	172	.set_state_oneshot = tc_set_oneshot,
4d243f92 DB	173	},
	174	};
	175
	176	static irqreturn_t ch2_irq(int irq, void *handle)
	177	{
	178	struct tc_clkevt_device *dev = handle;
	179	unsigned int sr;
	180
	181	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
	182	if (sr & ATMEL_TC_CPCS) {
	183	dev->clkevt.event_handler(&dev->clkevt);
	184	return IRQ_HANDLED;
	185	}
	186
	187	return IRQ_NONE;
	188	}
	189
5b3c11da	190	static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
4d243f92	191	{
5b3c11da	192	int ret;
4d243f92 DB	193	struct clk *t2_clk = tc->clk[2];
	194	int irq = tc->irq[2];
	195
7d8d05d1 BB	196	ret = clk_prepare_enable(tc->slow_clk);
	197	if (ret)
	198	return ret;
	199
5b3c11da BB	200	/* try to enable t2 clk to avoid future errors in mode change */
5b3c11da BB	201	ret = clk_prepare_enable(t2_clk);
7d8d05d1 BB	202	if (ret) {
7d8d05d1 BB	203	clk_disable_unprepare(tc->slow_clk);
5b3c11da	204	return ret;
7d8d05d1 BB	205	}
7d8d05d1 BB	206
acbf6d21	207	clk_disable(t2_clk);
5b3c11da	208
4d243f92 DB	209	clkevt.regs = tc->regs;
4d243f92 DB	210	clkevt.clk = t2_clk;
4d243f92 DB	211
	212	timer_clock = clk32k_divisor_idx;
	213
320ab2b0	214	clkevt.clkevt.cpumask = cpumask_of(0);
4d243f92	215
d07a1ecd GP	216	ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
d07a1ecd GP	217	if (ret) {
eed9fb9d	218	clk_unprepare(t2_clk);
7d8d05d1	219	clk_disable_unprepare(tc->slow_clk);
5b3c11da	220	return ret;
d07a1ecd	221	}
5b3c11da	222
77cc982f	223	clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
1817dc03	224
5b3c11da	225	return ret;
4d243f92 DB	226	}
	227
	228	#else /* !CONFIG_GENERIC_CLOCKEVENTS */
	229
5b3c11da	230	static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
4d243f92 DB	231	{
4d243f92 DB	232	/* NOTHING */
5b3c11da	233	return 0;
4d243f92 DB	234	}
	235
	236	#endif
	237
8e315a7b NF	238	static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
	239	{
	240	/* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
	241	__raw_writel(mck_divisor_idx /* likely divide-by-8 */
	242	\| ATMEL_TC_WAVE
	243	\| ATMEL_TC_WAVESEL_UP /* free-run */
	244	\| ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
	245	\| ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
	246	tcaddr + ATMEL_TC_REG(0, CMR));
	247	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
	248	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
	249	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
	250	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
	251
	252	/* channel 1: waveform mode, input TIOA0 */
	253	__raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
	254	\| ATMEL_TC_WAVE
	255	\| ATMEL_TC_WAVESEL_UP, /* free-run */
	256	tcaddr + ATMEL_TC_REG(1, CMR));
	257	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
	258	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
	259
	260	/* chain channel 0 to channel 1*/
	261	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
	262	/* then reset all the timers */
	263	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
	264	}
	265
	266	static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
	267	{
	268	/* channel 0: waveform mode, input mclk/8 */
	269	__raw_writel(mck_divisor_idx /* likely divide-by-8 */
	270	\| ATMEL_TC_WAVE
	271	\| ATMEL_TC_WAVESEL_UP, /* free-run */
	272	tcaddr + ATMEL_TC_REG(0, CMR));
	273	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
	274	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
	275
	276	/* then reset all the timers */
	277	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
	278	}
	279
4d243f92 DB	280	static int __init tcb_clksrc_init(void)
	281	{
	282	static char bootinfo[] __initdata
	283	= KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
	284
	285	struct platform_device *pdev;
	286	struct atmel_tc *tc;
3ee08aea	287	struct clk *t0_clk;
4d243f92 DB	288	u32 rate, divided_rate = 0;
	289	int best_divisor_idx = -1;
	290	int clk32k_divisor_idx = -1;
	291	int i;
0e746ec5	292	int ret;
4d243f92	293
4930d247	294	tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
4d243f92 DB	295	if (!tc) {
	296	pr_debug("can't alloc TC for clocksource\n");
	297	return -ENODEV;
	298	}
	299	tcaddr = tc->regs;
	300	pdev = tc->pdev;
	301
	302	t0_clk = tc->clk[0];
0e746ec5 BB	303	ret = clk_prepare_enable(t0_clk);
	304	if (ret) {
	305	pr_debug("can't enable T0 clk\n");
	306	goto err_free_tc;
	307	}
4d243f92 DB	308
	309	/* How fast will we be counting? Pick something over 5 MHz. */
	310	rate = (u32) clk_get_rate(t0_clk);
	311	for (i = 0; i < 5; i++) {
	312	unsigned divisor = atmel_tc_divisors[i];
	313	unsigned tmp;
	314
	315	/* remember 32 KiHz clock for later */
	316	if (!divisor) {
	317	clk32k_divisor_idx = i;
	318	continue;
	319	}
	320
	321	tmp = rate / divisor;
	322	pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
	323	if (best_divisor_idx > 0) {
	324	if (tmp < 5 * 1000 * 1000)
	325	continue;
	326	}
	327	divided_rate = tmp;
	328	best_divisor_idx = i;
	329	}
	330
4d243f92 DB	331
	332	printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
	333	divided_rate / 1000000,
	334	((divided_rate + 500000) % 1000000) / 1000);
	335
8e315a7b NF	336	if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
	337	/* use apropriate function to read 32 bit counter */
	338	clksrc.read = tc_get_cycles32;
	339	/* setup ony channel 0 */
	340	tcb_setup_single_chan(tc, best_divisor_idx);
	341	} else {
	342	/* tclib will give us three clocks no matter what the
	343	* underlying platform supports.
	344	*/
0e746ec5 BB	345	ret = clk_prepare_enable(tc->clk[1]);
	346	if (ret) {
	347	pr_debug("can't enable T1 clk\n");
	348	goto err_disable_t0;
	349	}
8e315a7b NF	350	/* setup both channel 0 & 1 */
	351	tcb_setup_dual_chan(tc, best_divisor_idx);
	352	}
4d243f92 DB	353
4d243f92 DB	354	/* and away we go! */
5b3c11da BB	355	ret = clocksource_register_hz(&clksrc, divided_rate);
	356	if (ret)
	357	goto err_disable_t1;
4d243f92 DB	358
4d243f92 DB	359	/* channel 2: periodic and oneshot timer support */
5b3c11da BB	360	ret = setup_clkevents(tc, clk32k_divisor_idx);
	361	if (ret)
	362	goto err_unregister_clksrc;
4d243f92 DB	363
4d243f92 DB	364	return 0;
0e746ec5	365
5b3c11da BB	366	err_unregister_clksrc:
	367	clocksource_unregister(&clksrc);
	368
	369	err_disable_t1:
	370	if (!tc->tcb_config \|\| tc->tcb_config->counter_width != 32)
	371	clk_disable_unprepare(tc->clk[1]);
	372
0e746ec5 BB	373	err_disable_t0:
	374	clk_disable_unprepare(t0_clk);
	375
	376	err_free_tc:
	377	atmel_tc_free(tc);
	378	return ret;
4d243f92 DB	379	}
4d243f92 DB	380	arch_initcall(tcb_clksrc_init);