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2d5cd9a3 | 1 | /* |
2d5cd9a3 CC |
2 | * Copyright (C) 2010 Google, Inc. |
3 | * | |
4 | * Author: | |
5 | * Colin Cross <ccross@google.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
62248ae8 | 19 | #include <linux/err.h> |
2d5cd9a3 CC |
20 | #include <linux/time.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/clockchips.h> | |
24 | #include <linux/clocksource.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/io.h> | |
3a04931e | 27 | #include <linux/of_address.h> |
56415480 | 28 | #include <linux/of_irq.h> |
38ff87f7 | 29 | #include <linux/sched_clock.h> |
2d5cd9a3 | 30 | |
2d5cd9a3 | 31 | #include <asm/mach/time.h> |
1fcf3a6e | 32 | #include <asm/smp_twd.h> |
2d5cd9a3 | 33 | |
09361785 CC |
34 | #define RTC_SECONDS 0x08 |
35 | #define RTC_SHADOW_SECONDS 0x0c | |
36 | #define RTC_MILLISECONDS 0x10 | |
37 | ||
2d5cd9a3 CC |
38 | #define TIMERUS_CNTR_1US 0x10 |
39 | #define TIMERUS_USEC_CFG 0x14 | |
40 | #define TIMERUS_CNTR_FREEZE 0x4c | |
41 | ||
42 | #define TIMER1_BASE 0x0 | |
43 | #define TIMER2_BASE 0x8 | |
44 | #define TIMER3_BASE 0x50 | |
45 | #define TIMER4_BASE 0x58 | |
46 | ||
47 | #define TIMER_PTV 0x0 | |
48 | #define TIMER_PCR 0x4 | |
49 | ||
3a04931e SW |
50 | static void __iomem *timer_reg_base; |
51 | static void __iomem *rtc_base; | |
09361785 CC |
52 | |
53 | static struct timespec persistent_ts; | |
54 | static u64 persistent_ms, last_persistent_ms; | |
2d5cd9a3 CC |
55 | |
56 | #define timer_writel(value, reg) \ | |
75d71166 | 57 | __raw_writel(value, timer_reg_base + (reg)) |
2d5cd9a3 | 58 | #define timer_readl(reg) \ |
75d71166 | 59 | __raw_readl(timer_reg_base + (reg)) |
2d5cd9a3 CC |
60 | |
61 | static int tegra_timer_set_next_event(unsigned long cycles, | |
62 | struct clock_event_device *evt) | |
63 | { | |
64 | u32 reg; | |
65 | ||
66 | reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); | |
67 | timer_writel(reg, TIMER3_BASE + TIMER_PTV); | |
68 | ||
69 | return 0; | |
70 | } | |
71 | ||
72 | static void tegra_timer_set_mode(enum clock_event_mode mode, | |
73 | struct clock_event_device *evt) | |
74 | { | |
75 | u32 reg; | |
76 | ||
77 | timer_writel(0, TIMER3_BASE + TIMER_PTV); | |
78 | ||
79 | switch (mode) { | |
80 | case CLOCK_EVT_MODE_PERIODIC: | |
81 | reg = 0xC0000000 | ((1000000/HZ)-1); | |
82 | timer_writel(reg, TIMER3_BASE + TIMER_PTV); | |
83 | break; | |
84 | case CLOCK_EVT_MODE_ONESHOT: | |
85 | break; | |
86 | case CLOCK_EVT_MODE_UNUSED: | |
87 | case CLOCK_EVT_MODE_SHUTDOWN: | |
88 | case CLOCK_EVT_MODE_RESUME: | |
89 | break; | |
90 | } | |
91 | } | |
92 | ||
2d5cd9a3 CC |
93 | static struct clock_event_device tegra_clockevent = { |
94 | .name = "timer0", | |
95 | .rating = 300, | |
96 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, | |
97 | .set_next_event = tegra_timer_set_next_event, | |
98 | .set_mode = tegra_timer_set_mode, | |
99 | }; | |
100 | ||
2f0778af | 101 | static u32 notrace tegra_read_sched_clock(void) |
e3f4c0ab | 102 | { |
2f0778af | 103 | return timer_readl(TIMERUS_CNTR_1US); |
2d5cd9a3 CC |
104 | } |
105 | ||
09361785 CC |
106 | /* |
107 | * tegra_rtc_read - Reads the Tegra RTC registers | |
108 | * Care must be taken that this funciton is not called while the | |
109 | * tegra_rtc driver could be executing to avoid race conditions | |
110 | * on the RTC shadow register | |
111 | */ | |
b28fba2a | 112 | static u64 tegra_rtc_read_ms(void) |
09361785 CC |
113 | { |
114 | u32 ms = readl(rtc_base + RTC_MILLISECONDS); | |
115 | u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); | |
116 | return (u64)s * MSEC_PER_SEC + ms; | |
117 | } | |
118 | ||
119 | /* | |
bd0493ea | 120 | * tegra_read_persistent_clock - Return time from a persistent clock. |
09361785 CC |
121 | * |
122 | * Reads the time from a source which isn't disabled during PM, the | |
123 | * 32k sync timer. Convert the cycles elapsed since last read into | |
124 | * nsecs and adds to a monotonically increasing timespec. | |
125 | * Care must be taken that this funciton is not called while the | |
126 | * tegra_rtc driver could be executing to avoid race conditions | |
127 | * on the RTC shadow register | |
128 | */ | |
bd0493ea | 129 | static void tegra_read_persistent_clock(struct timespec *ts) |
09361785 CC |
130 | { |
131 | u64 delta; | |
132 | struct timespec *tsp = &persistent_ts; | |
133 | ||
134 | last_persistent_ms = persistent_ms; | |
135 | persistent_ms = tegra_rtc_read_ms(); | |
136 | delta = persistent_ms - last_persistent_ms; | |
137 | ||
138 | timespec_add_ns(tsp, delta * NSEC_PER_MSEC); | |
139 | *ts = *tsp; | |
140 | } | |
141 | ||
2d5cd9a3 CC |
142 | static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) |
143 | { | |
144 | struct clock_event_device *evt = (struct clock_event_device *)dev_id; | |
145 | timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); | |
146 | evt->event_handler(evt); | |
147 | return IRQ_HANDLED; | |
148 | } | |
149 | ||
150 | static struct irqaction tegra_timer_irq = { | |
151 | .name = "timer0", | |
152 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH, | |
153 | .handler = tegra_timer_interrupt, | |
154 | .dev_id = &tegra_clockevent, | |
2d5cd9a3 CC |
155 | }; |
156 | ||
effbfdd7 | 157 | static void __init tegra20_init_timer(struct device_node *np) |
2d5cd9a3 | 158 | { |
62248ae8 | 159 | struct clk *clk; |
8e4fab2c | 160 | unsigned long rate; |
2d5cd9a3 CC |
161 | int ret; |
162 | ||
3a04931e SW |
163 | timer_reg_base = of_iomap(np, 0); |
164 | if (!timer_reg_base) { | |
37340866 | 165 | pr_err("Can't map timer registers\n"); |
3a04931e SW |
166 | BUG(); |
167 | } | |
168 | ||
56415480 SW |
169 | tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); |
170 | if (tegra_timer_irq.irq <= 0) { | |
171 | pr_err("Failed to map timer IRQ\n"); | |
172 | BUG(); | |
173 | } | |
174 | ||
6f88fb8a | 175 | clk = of_clk_get(np, 0); |
8e4fab2c | 176 | if (IS_ERR(clk)) { |
58664f90 | 177 | pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); |
8e4fab2c PDS |
178 | rate = 12000000; |
179 | } else { | |
6a5278d0 | 180 | clk_prepare_enable(clk); |
8e4fab2c PDS |
181 | rate = clk_get_rate(clk); |
182 | } | |
62248ae8 | 183 | |
3a04931e SW |
184 | of_node_put(np); |
185 | ||
2d5cd9a3 CC |
186 | switch (rate) { |
187 | case 12000000: | |
188 | timer_writel(0x000b, TIMERUS_USEC_CFG); | |
189 | break; | |
190 | case 13000000: | |
191 | timer_writel(0x000c, TIMERUS_USEC_CFG); | |
192 | break; | |
193 | case 19200000: | |
194 | timer_writel(0x045f, TIMERUS_USEC_CFG); | |
195 | break; | |
196 | case 26000000: | |
197 | timer_writel(0x0019, TIMERUS_USEC_CFG); | |
198 | break; | |
199 | default: | |
200 | WARN(1, "Unknown clock rate"); | |
201 | } | |
202 | ||
2f0778af | 203 | setup_sched_clock(tegra_read_sched_clock, 32, 1000000); |
e3f4c0ab | 204 | |
234b6ced RK |
205 | if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, |
206 | "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { | |
58664f90 | 207 | pr_err("Failed to register clocksource\n"); |
2d5cd9a3 CC |
208 | BUG(); |
209 | } | |
210 | ||
211 | ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); | |
212 | if (ret) { | |
58664f90 | 213 | pr_err("Failed to register timer IRQ: %d\n", ret); |
2d5cd9a3 CC |
214 | BUG(); |
215 | } | |
216 | ||
2d5cd9a3 CC |
217 | tegra_clockevent.cpumask = cpu_all_mask; |
218 | tegra_clockevent.irq = tegra_timer_irq.irq; | |
838a2ae8 SG |
219 | clockevents_config_and_register(&tegra_clockevent, 1000000, |
220 | 0x1, 0x1fffffff); | |
1d16cfb3 RH |
221 | } |
222 | CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); | |
223 | ||
224 | static void __init tegra20_init_rtc(struct device_node *np) | |
225 | { | |
226 | struct clk *clk; | |
227 | ||
228 | rtc_base = of_iomap(np, 0); | |
229 | if (!rtc_base) { | |
230 | pr_err("Can't map RTC registers"); | |
231 | BUG(); | |
232 | } | |
233 | ||
234 | /* | |
235 | * rtc registers are used by read_persistent_clock, keep the rtc clock | |
236 | * enabled | |
237 | */ | |
8024206d | 238 | clk = of_clk_get(np, 0); |
1d16cfb3 RH |
239 | if (IS_ERR(clk)) |
240 | pr_warn("Unable to get rtc-tegra clock\n"); | |
241 | else | |
242 | clk_prepare_enable(clk); | |
243 | ||
244 | of_node_put(np); | |
245 | ||
bd0493ea | 246 | register_persistent_clock(NULL, tegra_read_persistent_clock); |
2d5cd9a3 | 247 | } |
1d16cfb3 | 248 | CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); |
2d5cd9a3 | 249 | |
09361785 CC |
250 | #ifdef CONFIG_PM |
251 | static u32 usec_config; | |
252 | ||
253 | void tegra_timer_suspend(void) | |
254 | { | |
255 | usec_config = timer_readl(TIMERUS_USEC_CFG); | |
256 | } | |
257 | ||
258 | void tegra_timer_resume(void) | |
259 | { | |
260 | timer_writel(usec_config, TIMERUS_USEC_CFG); | |
261 | } | |
262 | #endif |