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beb5818b LW |
1 | /* |
2 | * Integrator/AP timer driver | |
3 | * Copyright (C) 2000-2003 Deep Blue Solutions Ltd | |
4 | * Copyright (c) 2014, Linaro Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/clocksource.h> | |
23 | #include <linux/of_irq.h> | |
24 | #include <linux/of_address.h> | |
25 | #include <linux/of_platform.h> | |
26 | #include <linux/clockchips.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/sched_clock.h> | |
29 | #include <asm/hardware/arm_timer.h> | |
30 | ||
31 | static void __iomem * sched_clk_base; | |
32 | ||
33 | static u64 notrace integrator_read_sched_clock(void) | |
34 | { | |
35 | return -readl(sched_clk_base + TIMER_VALUE); | |
36 | } | |
37 | ||
38 | static void integrator_clocksource_init(unsigned long inrate, | |
39 | void __iomem *base) | |
40 | { | |
41 | u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; | |
42 | unsigned long rate = inrate; | |
43 | ||
44 | if (rate >= 1500000) { | |
45 | rate /= 16; | |
46 | ctrl |= TIMER_CTRL_DIV16; | |
47 | } | |
48 | ||
49 | writel(0xffff, base + TIMER_LOAD); | |
50 | writel(ctrl, base + TIMER_CTRL); | |
51 | ||
52 | clocksource_mmio_init(base + TIMER_VALUE, "timer2", | |
53 | rate, 200, 16, clocksource_mmio_readl_down); | |
54 | ||
55 | sched_clk_base = base; | |
56 | sched_clock_register(integrator_read_sched_clock, 16, rate); | |
57 | } | |
58 | ||
59 | static unsigned long timer_reload; | |
60 | static void __iomem * clkevt_base; | |
61 | ||
62 | /* | |
63 | * IRQ handler for the timer | |
64 | */ | |
65 | static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id) | |
66 | { | |
67 | struct clock_event_device *evt = dev_id; | |
68 | ||
69 | /* clear the interrupt */ | |
70 | writel(1, clkevt_base + TIMER_INTCLR); | |
71 | ||
72 | evt->event_handler(evt); | |
73 | ||
74 | return IRQ_HANDLED; | |
75 | } | |
76 | ||
77 | static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) | |
78 | { | |
79 | u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; | |
80 | ||
81 | /* Disable timer */ | |
82 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
83 | ||
84 | switch (mode) { | |
85 | case CLOCK_EVT_MODE_PERIODIC: | |
86 | /* Enable the timer and start the periodic tick */ | |
87 | writel(timer_reload, clkevt_base + TIMER_LOAD); | |
88 | ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; | |
89 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
90 | break; | |
91 | case CLOCK_EVT_MODE_ONESHOT: | |
92 | /* Leave the timer disabled, .set_next_event will enable it */ | |
93 | ctrl &= ~TIMER_CTRL_PERIODIC; | |
94 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
95 | break; | |
96 | case CLOCK_EVT_MODE_UNUSED: | |
97 | case CLOCK_EVT_MODE_SHUTDOWN: | |
98 | case CLOCK_EVT_MODE_RESUME: | |
99 | default: | |
100 | /* Just leave in disabled state */ | |
101 | break; | |
102 | } | |
103 | ||
104 | } | |
105 | ||
106 | static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt) | |
107 | { | |
108 | unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); | |
109 | ||
110 | writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | |
111 | writel(next, clkevt_base + TIMER_LOAD); | |
112 | writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
117 | static struct clock_event_device integrator_clockevent = { | |
118 | .name = "timer1", | |
119 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
120 | .set_mode = clkevt_set_mode, | |
121 | .set_next_event = clkevt_set_next_event, | |
122 | .rating = 300, | |
123 | }; | |
124 | ||
125 | static struct irqaction integrator_timer_irq = { | |
126 | .name = "timer", | |
127 | .flags = IRQF_TIMER | IRQF_IRQPOLL, | |
128 | .handler = integrator_timer_interrupt, | |
129 | .dev_id = &integrator_clockevent, | |
130 | }; | |
131 | ||
132 | static void integrator_clockevent_init(unsigned long inrate, | |
133 | void __iomem *base, int irq) | |
134 | { | |
135 | unsigned long rate = inrate; | |
136 | unsigned int ctrl = 0; | |
137 | ||
138 | clkevt_base = base; | |
139 | /* Calculate and program a divisor */ | |
140 | if (rate > 0x100000 * HZ) { | |
141 | rate /= 256; | |
142 | ctrl |= TIMER_CTRL_DIV256; | |
143 | } else if (rate > 0x10000 * HZ) { | |
144 | rate /= 16; | |
145 | ctrl |= TIMER_CTRL_DIV16; | |
146 | } | |
147 | timer_reload = rate / HZ; | |
148 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
149 | ||
150 | setup_irq(irq, &integrator_timer_irq); | |
151 | clockevents_config_and_register(&integrator_clockevent, | |
152 | rate, | |
153 | 1, | |
154 | 0xffffU); | |
155 | } | |
156 | ||
157 | static void __init integrator_ap_timer_init_of(struct device_node *node) | |
158 | { | |
159 | const char *path; | |
160 | void __iomem *base; | |
161 | int err; | |
162 | int irq; | |
163 | struct clk *clk; | |
164 | unsigned long rate; | |
165 | struct device_node *pri_node; | |
166 | struct device_node *sec_node; | |
167 | ||
168 | base = of_io_request_and_map(node, 0, "integrator-timer"); | |
169 | if (!base) | |
170 | return; | |
171 | ||
172 | clk = of_clk_get(node, 0); | |
173 | if (IS_ERR(clk)) { | |
174 | pr_err("No clock for %s\n", node->name); | |
175 | return; | |
176 | } | |
177 | clk_prepare_enable(clk); | |
178 | rate = clk_get_rate(clk); | |
179 | writel(0, base + TIMER_CTRL); | |
180 | ||
181 | err = of_property_read_string(of_aliases, | |
182 | "arm,timer-primary", &path); | |
183 | if (WARN_ON(err)) | |
184 | return; | |
185 | pri_node = of_find_node_by_path(path); | |
186 | err = of_property_read_string(of_aliases, | |
187 | "arm,timer-secondary", &path); | |
188 | if (WARN_ON(err)) | |
189 | return; | |
190 | sec_node = of_find_node_by_path(path); | |
191 | ||
192 | if (node == pri_node) { | |
193 | /* The primary timer lacks IRQ, use as clocksource */ | |
194 | integrator_clocksource_init(rate, base); | |
195 | return; | |
196 | } | |
197 | ||
198 | if (node == sec_node) { | |
199 | /* The secondary timer will drive the clock event */ | |
200 | irq = irq_of_parse_and_map(node, 0); | |
201 | integrator_clockevent_init(rate, base, irq); | |
202 | return; | |
203 | } | |
204 | ||
205 | pr_info("Timer @%p unused\n", base); | |
206 | clk_disable_unprepare(clk); | |
207 | } | |
208 | ||
209 | CLOCKSOURCE_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer", | |
210 | integrator_ap_timer_init_of); |