projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a06ae860 PP |
1 | /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. |
| 2 | * | |
| 3 | * This program is free software; you can redistribute it and/or modify | |
| 4 | * it under the terms of the GNU General Public License version 2 and | |
| 5 | * only version 2 as published by the Free Software Foundation. | |
| 6 | * | |
| 7 | * This program is distributed in the hope that it will be useful, | |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 10 | * GNU General Public License for more details. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef _CORESIGHT_PRIV_H | |
| 14 | #define _CORESIGHT_PRIV_H | |
| 15 | ||
| 16 | #include <linux/bitops.h> | |
| 17 | #include <linux/io.h> | |
| 18 | #include <linux/coresight.h> | |
| 19 | ||
| 20 | /* | |
| 21 | * Coresight management registers (0xf00-0xfcc) | |
| 22 | * 0xfa0 - 0xfa4: Management registers in PFTv1.0 | |
| 23 | * Trace registers in PFTv1.1 | |
| 24 | */ | |
| 25 | #define CORESIGHT_ITCTRL 0xf00 | |
| 26 | #define CORESIGHT_CLAIMSET 0xfa0 | |
| 27 | #define CORESIGHT_CLAIMCLR 0xfa4 | |
| 28 | #define CORESIGHT_LAR 0xfb0 | |
| 29 | #define CORESIGHT_LSR 0xfb4 | |
| 30 | #define CORESIGHT_AUTHSTATUS 0xfb8 | |
| 31 | #define CORESIGHT_DEVID 0xfc8 | |
| 32 | #define CORESIGHT_DEVTYPE 0xfcc | |
| 33 | ||
| 34 | #define TIMEOUT_US 100 | |
| 35 | #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) | |
| 36 | ||
| 37 | static inline void CS_LOCK(void __iomem *addr) | |
| 38 | { | |
| 39 | do { | |
| 40 | /* Wait for things to settle */ | |
| 41 | mb(); | |
| 42 | writel_relaxed(0x0, addr + CORESIGHT_LAR); | |
| 43 | } while (0); | |
| 44 | } | |
| 45 | ||
| 46 | static inline void CS_UNLOCK(void __iomem *addr) | |
| 47 | { | |
| 48 | do { | |
| 49 | writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR); | |
| 84b763d5 | 50 | /* Make sure everyone has seen this */ |
| a06ae860 PP |
51 | mb(); |
| 52 | } while (0); | |
| 53 | } | |
| 54 | ||
| 55 | #ifdef CONFIG_CORESIGHT_SOURCE_ETM3X | |
| 56 | extern int etm_readl_cp14(u32 off, unsigned int *val); | |
| 57 | extern int etm_writel_cp14(u32 off, u32 val); | |
| 58 | #else | |
| 59 | static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } | |
| 60 | static inline int etm_writel_cp14(u32 val, u32 off) { return 0; } | |
| 61 | #endif | |
| 62 | ||
| 63 | #endif |