Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3a58df35 | 2 | * acpi-cpufreq.c - ACPI Processor P-States Driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 7 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
8 | * |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
24 | * | |
25 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
26 | */ | |
27 | ||
1c5864e2 JP |
28 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/init.h> | |
fe27cb35 VP |
33 | #include <linux/smp.h> |
34 | #include <linux/sched.h> | |
1da177e4 | 35 | #include <linux/cpufreq.h> |
d395bf12 | 36 | #include <linux/compiler.h> |
8adcc0c6 | 37 | #include <linux/dmi.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
1da177e4 LT |
39 | |
40 | #include <linux/acpi.h> | |
3a58df35 DJ |
41 | #include <linux/io.h> |
42 | #include <linux/delay.h> | |
43 | #include <linux/uaccess.h> | |
44 | ||
1da177e4 LT |
45 | #include <acpi/processor.h> |
46 | ||
dde9f7ba | 47 | #include <asm/msr.h> |
fe27cb35 VP |
48 | #include <asm/processor.h> |
49 | #include <asm/cpufeature.h> | |
fe27cb35 | 50 | |
1da177e4 LT |
51 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); |
52 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
53 | MODULE_LICENSE("GPL"); | |
54 | ||
dde9f7ba VP |
55 | enum { |
56 | UNDEFINED_CAPABLE = 0, | |
57 | SYSTEM_INTEL_MSR_CAPABLE, | |
3dc9a633 | 58 | SYSTEM_AMD_MSR_CAPABLE, |
dde9f7ba VP |
59 | SYSTEM_IO_CAPABLE, |
60 | }; | |
61 | ||
62 | #define INTEL_MSR_RANGE (0xffff) | |
3dc9a633 | 63 | #define AMD_MSR_RANGE (0x7) |
dde9f7ba | 64 | |
615b7300 AP |
65 | #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) |
66 | ||
fe27cb35 | 67 | struct acpi_cpufreq_data { |
64be7eed VP |
68 | unsigned int resume; |
69 | unsigned int cpu_feature; | |
8cfcfd39 | 70 | unsigned int acpi_perf_cpu; |
f4fd3797 | 71 | cpumask_var_t freqdomain_cpus; |
ed757a2c RW |
72 | void (*cpu_freq_write)(struct acpi_pct_register *reg, u32 val); |
73 | u32 (*cpu_freq_read)(struct acpi_pct_register *reg); | |
1da177e4 LT |
74 | }; |
75 | ||
50109292 | 76 | /* acpi_perf_data is a pointer to percpu data. */ |
3f6c4df7 | 77 | static struct acpi_processor_performance __percpu *acpi_perf_data; |
1da177e4 | 78 | |
3427616b RW |
79 | static inline struct acpi_processor_performance *to_perf_data(struct acpi_cpufreq_data *data) |
80 | { | |
81 | return per_cpu_ptr(acpi_perf_data, data->acpi_perf_cpu); | |
82 | } | |
83 | ||
1da177e4 LT |
84 | static struct cpufreq_driver acpi_cpufreq_driver; |
85 | ||
d395bf12 | 86 | static unsigned int acpi_pstate_strict; |
615b7300 AP |
87 | static struct msr __percpu *msrs; |
88 | ||
89 | static bool boost_state(unsigned int cpu) | |
90 | { | |
91 | u32 lo, hi; | |
92 | u64 msr; | |
93 | ||
94 | switch (boot_cpu_data.x86_vendor) { | |
95 | case X86_VENDOR_INTEL: | |
96 | rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); | |
97 | msr = lo | ((u64)hi << 32); | |
98 | return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
99 | case X86_VENDOR_AMD: | |
100 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
101 | msr = lo | ((u64)hi << 32); | |
102 | return !(msr & MSR_K7_HWCR_CPB_DIS); | |
103 | } | |
104 | return false; | |
105 | } | |
106 | ||
107 | static void boost_set_msrs(bool enable, const struct cpumask *cpumask) | |
108 | { | |
109 | u32 cpu; | |
110 | u32 msr_addr; | |
111 | u64 msr_mask; | |
112 | ||
113 | switch (boot_cpu_data.x86_vendor) { | |
114 | case X86_VENDOR_INTEL: | |
115 | msr_addr = MSR_IA32_MISC_ENABLE; | |
116 | msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; | |
117 | break; | |
118 | case X86_VENDOR_AMD: | |
119 | msr_addr = MSR_K7_HWCR; | |
120 | msr_mask = MSR_K7_HWCR_CPB_DIS; | |
121 | break; | |
122 | default: | |
123 | return; | |
124 | } | |
125 | ||
126 | rdmsr_on_cpus(cpumask, msr_addr, msrs); | |
127 | ||
128 | for_each_cpu(cpu, cpumask) { | |
129 | struct msr *reg = per_cpu_ptr(msrs, cpu); | |
130 | if (enable) | |
131 | reg->q &= ~msr_mask; | |
132 | else | |
133 | reg->q |= msr_mask; | |
134 | } | |
135 | ||
136 | wrmsr_on_cpus(cpumask, msr_addr, msrs); | |
137 | } | |
138 | ||
17135782 | 139 | static int set_boost(int val) |
615b7300 | 140 | { |
615b7300 | 141 | get_online_cpus(); |
615b7300 | 142 | boost_set_msrs(val, cpu_online_mask); |
615b7300 | 143 | put_online_cpus(); |
615b7300 AP |
144 | pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); |
145 | ||
cfc9c8ed | 146 | return 0; |
615b7300 AP |
147 | } |
148 | ||
f4fd3797 LT |
149 | static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) |
150 | { | |
eb0b3e78 | 151 | struct acpi_cpufreq_data *data = policy->driver_data; |
f4fd3797 | 152 | |
e2530367 SP |
153 | if (unlikely(!data)) |
154 | return -ENODEV; | |
155 | ||
f4fd3797 LT |
156 | return cpufreq_show_cpus(data->freqdomain_cpus, buf); |
157 | } | |
158 | ||
159 | cpufreq_freq_attr_ro(freqdomain_cpus); | |
160 | ||
11269ff5 | 161 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
17135782 RW |
162 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, |
163 | size_t count) | |
cfc9c8ed LM |
164 | { |
165 | int ret; | |
17135782 | 166 | unsigned int val = 0; |
cfc9c8ed | 167 | |
7a6c79f2 | 168 | if (!acpi_cpufreq_driver.set_boost) |
cfc9c8ed LM |
169 | return -EINVAL; |
170 | ||
17135782 RW |
171 | ret = kstrtouint(buf, 10, &val); |
172 | if (ret || val > 1) | |
cfc9c8ed LM |
173 | return -EINVAL; |
174 | ||
17135782 | 175 | set_boost(val); |
cfc9c8ed LM |
176 | |
177 | return count; | |
178 | } | |
179 | ||
11269ff5 AP |
180 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) |
181 | { | |
cfc9c8ed | 182 | return sprintf(buf, "%u\n", acpi_cpufreq_driver.boost_enabled); |
11269ff5 AP |
183 | } |
184 | ||
59027d35 | 185 | cpufreq_freq_attr_rw(cpb); |
11269ff5 AP |
186 | #endif |
187 | ||
dde9f7ba VP |
188 | static int check_est_cpu(unsigned int cpuid) |
189 | { | |
92cb7612 | 190 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); |
dde9f7ba | 191 | |
0de51088 | 192 | return cpu_has(cpu, X86_FEATURE_EST); |
dde9f7ba VP |
193 | } |
194 | ||
3dc9a633 MG |
195 | static int check_amd_hwpstate_cpu(unsigned int cpuid) |
196 | { | |
197 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); | |
198 | ||
199 | return cpu_has(cpu, X86_FEATURE_HW_PSTATE); | |
200 | } | |
201 | ||
8cee1eed | 202 | static unsigned extract_io(struct cpufreq_policy *policy, u32 value) |
fe27cb35 | 203 | { |
8cee1eed | 204 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed VP |
205 | struct acpi_processor_performance *perf; |
206 | int i; | |
fe27cb35 | 207 | |
3427616b | 208 | perf = to_perf_data(data); |
fe27cb35 | 209 | |
3a58df35 | 210 | for (i = 0; i < perf->state_count; i++) { |
fe27cb35 | 211 | if (value == perf->states[i].status) |
8cee1eed | 212 | return policy->freq_table[i].frequency; |
fe27cb35 VP |
213 | } |
214 | return 0; | |
215 | } | |
216 | ||
8cee1eed | 217 | static unsigned extract_msr(struct cpufreq_policy *policy, u32 msr) |
dde9f7ba | 218 | { |
8cee1eed | 219 | struct acpi_cpufreq_data *data = policy->driver_data; |
041526f9 | 220 | struct cpufreq_frequency_table *pos; |
a6f6e6e6 | 221 | struct acpi_processor_performance *perf; |
dde9f7ba | 222 | |
3dc9a633 MG |
223 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
224 | msr &= AMD_MSR_RANGE; | |
225 | else | |
226 | msr &= INTEL_MSR_RANGE; | |
227 | ||
3427616b | 228 | perf = to_perf_data(data); |
a6f6e6e6 | 229 | |
8cee1eed | 230 | cpufreq_for_each_entry(pos, policy->freq_table) |
041526f9 SK |
231 | if (msr == perf->states[pos->driver_data].status) |
232 | return pos->frequency; | |
8cee1eed | 233 | return policy->freq_table[0].frequency; |
dde9f7ba VP |
234 | } |
235 | ||
8cee1eed | 236 | static unsigned extract_freq(struct cpufreq_policy *policy, u32 val) |
dde9f7ba | 237 | { |
8cee1eed VK |
238 | struct acpi_cpufreq_data *data = policy->driver_data; |
239 | ||
dde9f7ba | 240 | switch (data->cpu_feature) { |
64be7eed | 241 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 242 | case SYSTEM_AMD_MSR_CAPABLE: |
8cee1eed | 243 | return extract_msr(policy, val); |
64be7eed | 244 | case SYSTEM_IO_CAPABLE: |
8cee1eed | 245 | return extract_io(policy, val); |
64be7eed | 246 | default: |
dde9f7ba VP |
247 | return 0; |
248 | } | |
249 | } | |
250 | ||
ac13b996 | 251 | static u32 cpu_freq_read_intel(struct acpi_pct_register *not_used) |
ed757a2c RW |
252 | { |
253 | u32 val, dummy; | |
dde9f7ba | 254 | |
ed757a2c RW |
255 | rdmsr(MSR_IA32_PERF_CTL, val, dummy); |
256 | return val; | |
257 | } | |
258 | ||
ac13b996 | 259 | static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val) |
ed757a2c RW |
260 | { |
261 | u32 lo, hi; | |
262 | ||
263 | rdmsr(MSR_IA32_PERF_CTL, lo, hi); | |
264 | lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE); | |
265 | wrmsr(MSR_IA32_PERF_CTL, lo, hi); | |
266 | } | |
267 | ||
ac13b996 | 268 | static u32 cpu_freq_read_amd(struct acpi_pct_register *not_used) |
ed757a2c RW |
269 | { |
270 | u32 val, dummy; | |
271 | ||
272 | rdmsr(MSR_AMD_PERF_CTL, val, dummy); | |
273 | return val; | |
274 | } | |
275 | ||
ac13b996 | 276 | static void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val) |
ed757a2c RW |
277 | { |
278 | wrmsr(MSR_AMD_PERF_CTL, val, 0); | |
279 | } | |
280 | ||
ac13b996 | 281 | static u32 cpu_freq_read_io(struct acpi_pct_register *reg) |
ed757a2c RW |
282 | { |
283 | u32 val; | |
284 | ||
285 | acpi_os_read_port(reg->address, &val, reg->bit_width); | |
286 | return val; | |
287 | } | |
288 | ||
ac13b996 | 289 | static void cpu_freq_write_io(struct acpi_pct_register *reg, u32 val) |
ed757a2c RW |
290 | { |
291 | acpi_os_write_port(reg->address, val, reg->bit_width); | |
292 | } | |
fe27cb35 VP |
293 | |
294 | struct drv_cmd { | |
ed757a2c | 295 | struct acpi_pct_register *reg; |
fe27cb35 | 296 | u32 val; |
ed757a2c RW |
297 | union { |
298 | void (*write)(struct acpi_pct_register *reg, u32 val); | |
299 | u32 (*read)(struct acpi_pct_register *reg); | |
300 | } func; | |
fe27cb35 VP |
301 | }; |
302 | ||
01599fca AM |
303 | /* Called via smp_call_function_single(), on the target CPU */ |
304 | static void do_drv_read(void *_cmd) | |
1da177e4 | 305 | { |
72859081 | 306 | struct drv_cmd *cmd = _cmd; |
dde9f7ba | 307 | |
ed757a2c | 308 | cmd->val = cmd->func.read(cmd->reg); |
fe27cb35 | 309 | } |
1da177e4 | 310 | |
ed757a2c | 311 | static u32 drv_read(struct acpi_cpufreq_data *data, const struct cpumask *mask) |
fe27cb35 | 312 | { |
ed757a2c RW |
313 | struct acpi_processor_performance *perf = to_perf_data(data); |
314 | struct drv_cmd cmd = { | |
315 | .reg = &perf->control_register, | |
316 | .func.read = data->cpu_freq_read, | |
317 | }; | |
318 | int err; | |
dde9f7ba | 319 | |
ed757a2c RW |
320 | err = smp_call_function_any(mask, do_drv_read, &cmd, 1); |
321 | WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ | |
322 | return cmd.val; | |
fe27cb35 | 323 | } |
1da177e4 | 324 | |
ed757a2c RW |
325 | /* Called via smp_call_function_many(), on the target CPUs */ |
326 | static void do_drv_write(void *_cmd) | |
fe27cb35 | 327 | { |
ed757a2c | 328 | struct drv_cmd *cmd = _cmd; |
fe27cb35 | 329 | |
ed757a2c | 330 | cmd->func.write(cmd->reg, cmd->val); |
fe27cb35 VP |
331 | } |
332 | ||
ed757a2c RW |
333 | static void drv_write(struct acpi_cpufreq_data *data, |
334 | const struct cpumask *mask, u32 val) | |
fe27cb35 | 335 | { |
ed757a2c RW |
336 | struct acpi_processor_performance *perf = to_perf_data(data); |
337 | struct drv_cmd cmd = { | |
338 | .reg = &perf->control_register, | |
339 | .val = val, | |
340 | .func.write = data->cpu_freq_write, | |
341 | }; | |
ea34f43a LT |
342 | int this_cpu; |
343 | ||
344 | this_cpu = get_cpu(); | |
ed757a2c RW |
345 | if (cpumask_test_cpu(this_cpu, mask)) |
346 | do_drv_write(&cmd); | |
347 | ||
348 | smp_call_function_many(mask, do_drv_write, &cmd, 1); | |
ea34f43a | 349 | put_cpu(); |
fe27cb35 | 350 | } |
1da177e4 | 351 | |
ed757a2c | 352 | static u32 get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data) |
fe27cb35 | 353 | { |
ed757a2c | 354 | u32 val; |
1da177e4 | 355 | |
4d8bb537 | 356 | if (unlikely(cpumask_empty(mask))) |
fe27cb35 | 357 | return 0; |
1da177e4 | 358 | |
ed757a2c | 359 | val = drv_read(data, mask); |
1da177e4 | 360 | |
ed757a2c | 361 | pr_debug("get_cur_val = %u\n", val); |
fe27cb35 | 362 | |
ed757a2c | 363 | return val; |
fe27cb35 | 364 | } |
1da177e4 | 365 | |
fe27cb35 VP |
366 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
367 | { | |
eb0b3e78 PX |
368 | struct acpi_cpufreq_data *data; |
369 | struct cpufreq_policy *policy; | |
64be7eed | 370 | unsigned int freq; |
e56a727b | 371 | unsigned int cached_freq; |
fe27cb35 | 372 | |
2d06d8c4 | 373 | pr_debug("get_cur_freq_on_cpu (%d)\n", cpu); |
fe27cb35 | 374 | |
1f0bd44e | 375 | policy = cpufreq_cpu_get_raw(cpu); |
eb0b3e78 PX |
376 | if (unlikely(!policy)) |
377 | return 0; | |
378 | ||
379 | data = policy->driver_data; | |
8cee1eed | 380 | if (unlikely(!data || !policy->freq_table)) |
fe27cb35 | 381 | return 0; |
1da177e4 | 382 | |
8cee1eed VK |
383 | cached_freq = policy->freq_table[to_perf_data(data)->state].frequency; |
384 | freq = extract_freq(policy, get_cur_val(cpumask_of(cpu), data)); | |
e56a727b VP |
385 | if (freq != cached_freq) { |
386 | /* | |
387 | * The dreaded BIOS frequency change behind our back. | |
388 | * Force set the frequency on next target call. | |
389 | */ | |
390 | data->resume = 1; | |
391 | } | |
392 | ||
2d06d8c4 | 393 | pr_debug("cur freq = %u\n", freq); |
1da177e4 | 394 | |
fe27cb35 | 395 | return freq; |
1da177e4 LT |
396 | } |
397 | ||
8cee1eed VK |
398 | static unsigned int check_freqs(struct cpufreq_policy *policy, |
399 | const struct cpumask *mask, unsigned int freq) | |
fe27cb35 | 400 | { |
8cee1eed | 401 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed VP |
402 | unsigned int cur_freq; |
403 | unsigned int i; | |
1da177e4 | 404 | |
3a58df35 | 405 | for (i = 0; i < 100; i++) { |
8cee1eed | 406 | cur_freq = extract_freq(policy, get_cur_val(mask, data)); |
fe27cb35 VP |
407 | if (cur_freq == freq) |
408 | return 1; | |
409 | udelay(10); | |
410 | } | |
411 | return 0; | |
412 | } | |
413 | ||
414 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 415 | unsigned int index) |
1da177e4 | 416 | { |
eb0b3e78 | 417 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed | 418 | struct acpi_processor_performance *perf; |
ed757a2c | 419 | const struct cpumask *mask; |
8edc59d9 | 420 | unsigned int next_perf_state = 0; /* Index into perf table */ |
64be7eed | 421 | int result = 0; |
fe27cb35 | 422 | |
8cee1eed | 423 | if (unlikely(!data)) { |
fe27cb35 VP |
424 | return -ENODEV; |
425 | } | |
1da177e4 | 426 | |
3427616b | 427 | perf = to_perf_data(data); |
8cee1eed | 428 | next_perf_state = policy->freq_table[index].driver_data; |
7650b281 | 429 | if (perf->state == next_perf_state) { |
fe27cb35 | 430 | if (unlikely(data->resume)) { |
2d06d8c4 | 431 | pr_debug("Called after resume, resetting to P%d\n", |
64be7eed | 432 | next_perf_state); |
fe27cb35 VP |
433 | data->resume = 0; |
434 | } else { | |
2d06d8c4 | 435 | pr_debug("Already at target state (P%d)\n", |
64be7eed | 436 | next_perf_state); |
9a909a14 | 437 | return 0; |
fe27cb35 | 438 | } |
09b4d1ee VP |
439 | } |
440 | ||
ed757a2c RW |
441 | /* |
442 | * The core won't allow CPUs to go away until the governor has been | |
443 | * stopped, so we can rely on the stability of policy->cpus. | |
444 | */ | |
445 | mask = policy->shared_type == CPUFREQ_SHARED_TYPE_ANY ? | |
446 | cpumask_of(policy->cpu) : policy->cpus; | |
09b4d1ee | 447 | |
ed757a2c | 448 | drv_write(data, mask, perf->states[next_perf_state].control); |
09b4d1ee | 449 | |
fe27cb35 | 450 | if (acpi_pstate_strict) { |
8cee1eed VK |
451 | if (!check_freqs(policy, mask, |
452 | policy->freq_table[index].frequency)) { | |
2d06d8c4 | 453 | pr_debug("acpi_cpufreq_target failed (%d)\n", |
64be7eed | 454 | policy->cpu); |
4d8bb537 | 455 | result = -EAGAIN; |
09b4d1ee VP |
456 | } |
457 | } | |
458 | ||
e15d8309 VK |
459 | if (!result) |
460 | perf->state = next_perf_state; | |
fe27cb35 VP |
461 | |
462 | return result; | |
1da177e4 LT |
463 | } |
464 | ||
b7898fda RW |
465 | unsigned int acpi_cpufreq_fast_switch(struct cpufreq_policy *policy, |
466 | unsigned int target_freq) | |
467 | { | |
468 | struct acpi_cpufreq_data *data = policy->driver_data; | |
469 | struct acpi_processor_performance *perf; | |
470 | struct cpufreq_frequency_table *entry; | |
471 | unsigned int next_perf_state, next_freq, freq; | |
472 | ||
473 | /* | |
474 | * Find the closest frequency above target_freq. | |
475 | * | |
476 | * The table is sorted in the reverse order with respect to the | |
477 | * frequency and all of the entries are valid (see the initialization). | |
478 | */ | |
8cee1eed | 479 | entry = policy->freq_table; |
b7898fda RW |
480 | do { |
481 | entry++; | |
482 | freq = entry->frequency; | |
483 | } while (freq >= target_freq && freq != CPUFREQ_TABLE_END); | |
484 | entry--; | |
485 | next_freq = entry->frequency; | |
486 | next_perf_state = entry->driver_data; | |
487 | ||
488 | perf = to_perf_data(data); | |
489 | if (perf->state == next_perf_state) { | |
490 | if (unlikely(data->resume)) | |
491 | data->resume = 0; | |
492 | else | |
493 | return next_freq; | |
494 | } | |
495 | ||
496 | data->cpu_freq_write(&perf->control_register, | |
497 | perf->states[next_perf_state].control); | |
498 | perf->state = next_perf_state; | |
499 | return next_freq; | |
500 | } | |
501 | ||
1da177e4 | 502 | static unsigned long |
64be7eed | 503 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 504 | { |
3427616b | 505 | struct acpi_processor_performance *perf; |
09b4d1ee | 506 | |
3427616b | 507 | perf = to_perf_data(data); |
1da177e4 LT |
508 | if (cpu_khz) { |
509 | /* search the closest match to cpu_khz */ | |
510 | unsigned int i; | |
511 | unsigned long freq; | |
09b4d1ee | 512 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 513 | |
3a58df35 | 514 | for (i = 0; i < (perf->state_count-1); i++) { |
1da177e4 | 515 | freq = freqn; |
95dd7227 | 516 | freqn = perf->states[i+1].core_frequency * 1000; |
1da177e4 | 517 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 518 | perf->state = i; |
64be7eed | 519 | return freq; |
1da177e4 LT |
520 | } |
521 | } | |
95dd7227 | 522 | perf->state = perf->state_count-1; |
64be7eed | 523 | return freqn; |
09b4d1ee | 524 | } else { |
1da177e4 | 525 | /* assume CPU is at P0... */ |
09b4d1ee VP |
526 | perf->state = 0; |
527 | return perf->states[0].core_frequency * 1000; | |
528 | } | |
1da177e4 LT |
529 | } |
530 | ||
2fdf66b4 RR |
531 | static void free_acpi_perf_data(void) |
532 | { | |
533 | unsigned int i; | |
534 | ||
535 | /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ | |
536 | for_each_possible_cpu(i) | |
537 | free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) | |
538 | ->shared_cpu_map); | |
539 | free_percpu(acpi_perf_data); | |
540 | } | |
541 | ||
615b7300 AP |
542 | static int boost_notify(struct notifier_block *nb, unsigned long action, |
543 | void *hcpu) | |
544 | { | |
545 | unsigned cpu = (long)hcpu; | |
546 | const struct cpumask *cpumask; | |
547 | ||
548 | cpumask = get_cpu_mask(cpu); | |
549 | ||
550 | /* | |
551 | * Clear the boost-disable bit on the CPU_DOWN path so that | |
552 | * this cpu cannot block the remaining ones from boosting. On | |
553 | * the CPU_UP path we simply keep the boost-disable flag in | |
554 | * sync with the current global state. | |
555 | */ | |
556 | ||
557 | switch (action) { | |
ed72662a RC |
558 | case CPU_DOWN_FAILED: |
559 | case CPU_DOWN_FAILED_FROZEN: | |
560 | case CPU_ONLINE: | |
561 | case CPU_ONLINE_FROZEN: | |
cfc9c8ed | 562 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, cpumask); |
615b7300 AP |
563 | break; |
564 | ||
565 | case CPU_DOWN_PREPARE: | |
566 | case CPU_DOWN_PREPARE_FROZEN: | |
567 | boost_set_msrs(1, cpumask); | |
568 | break; | |
569 | ||
570 | default: | |
571 | break; | |
572 | } | |
573 | ||
574 | return NOTIFY_OK; | |
575 | } | |
576 | ||
577 | ||
578 | static struct notifier_block boost_nb = { | |
579 | .notifier_call = boost_notify, | |
580 | }; | |
581 | ||
09b4d1ee VP |
582 | /* |
583 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
584 | * | |
585 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
586 | * in order to determine correct frequency and voltage pairings. We can | |
587 | * do _PDC and _PSD and find out the processor dependency for the | |
588 | * actual init that will happen later... | |
589 | */ | |
50109292 | 590 | static int __init acpi_cpufreq_early_init(void) |
09b4d1ee | 591 | { |
2fdf66b4 | 592 | unsigned int i; |
2d06d8c4 | 593 | pr_debug("acpi_cpufreq_early_init\n"); |
09b4d1ee | 594 | |
50109292 FY |
595 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); |
596 | if (!acpi_perf_data) { | |
2d06d8c4 | 597 | pr_debug("Memory allocation error for acpi_perf_data.\n"); |
50109292 | 598 | return -ENOMEM; |
09b4d1ee | 599 | } |
2fdf66b4 | 600 | for_each_possible_cpu(i) { |
eaa95840 | 601 | if (!zalloc_cpumask_var_node( |
80855f73 MT |
602 | &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, |
603 | GFP_KERNEL, cpu_to_node(i))) { | |
2fdf66b4 RR |
604 | |
605 | /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ | |
606 | free_acpi_perf_data(); | |
607 | return -ENOMEM; | |
608 | } | |
609 | } | |
09b4d1ee VP |
610 | |
611 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
612 | acpi_processor_preregister_performance(acpi_perf_data); |
613 | return 0; | |
09b4d1ee VP |
614 | } |
615 | ||
95625b8f | 616 | #ifdef CONFIG_SMP |
8adcc0c6 VP |
617 | /* |
618 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
619 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
620 | * detected, this has a side effect of making CPU run at a different speed | |
621 | * than OS intended it to run at. Detect it and handle it cleanly. | |
622 | */ | |
623 | static int bios_with_sw_any_bug; | |
624 | ||
1855256c | 625 | static int sw_any_bug_found(const struct dmi_system_id *d) |
8adcc0c6 VP |
626 | { |
627 | bios_with_sw_any_bug = 1; | |
628 | return 0; | |
629 | } | |
630 | ||
1855256c | 631 | static const struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
632 | { |
633 | .callback = sw_any_bug_found, | |
634 | .ident = "Supermicro Server X6DLP", | |
635 | .matches = { | |
636 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
637 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
638 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
639 | }, | |
640 | }, | |
641 | { } | |
642 | }; | |
1a8e42fa PB |
643 | |
644 | static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) | |
645 | { | |
293afe44 JV |
646 | /* Intel Xeon Processor 7100 Series Specification Update |
647 | * http://www.intel.com/Assets/PDF/specupdate/314554.pdf | |
1a8e42fa PB |
648 | * AL30: A Machine Check Exception (MCE) Occurring during an |
649 | * Enhanced Intel SpeedStep Technology Ratio Change May Cause | |
293afe44 | 650 | * Both Processor Cores to Lock Up. */ |
1a8e42fa PB |
651 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
652 | if ((c->x86 == 15) && | |
653 | (c->x86_model == 6) && | |
293afe44 | 654 | (c->x86_mask == 8)) { |
1c5864e2 | 655 | pr_info("Intel(R) Xeon(R) 7100 Errata AL30, processors may lock up on frequency changes: disabling acpi-cpufreq\n"); |
1a8e42fa | 656 | return -ENODEV; |
293afe44 | 657 | } |
1a8e42fa PB |
658 | } |
659 | return 0; | |
660 | } | |
95625b8f | 661 | #endif |
8adcc0c6 | 662 | |
64be7eed | 663 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 664 | { |
64be7eed VP |
665 | unsigned int i; |
666 | unsigned int valid_states = 0; | |
667 | unsigned int cpu = policy->cpu; | |
668 | struct acpi_cpufreq_data *data; | |
64be7eed | 669 | unsigned int result = 0; |
92cb7612 | 670 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
64be7eed | 671 | struct acpi_processor_performance *perf; |
8cee1eed | 672 | struct cpufreq_frequency_table *freq_table; |
293afe44 JV |
673 | #ifdef CONFIG_SMP |
674 | static int blacklisted; | |
675 | #endif | |
1da177e4 | 676 | |
2d06d8c4 | 677 | pr_debug("acpi_cpufreq_cpu_init\n"); |
1da177e4 | 678 | |
1a8e42fa | 679 | #ifdef CONFIG_SMP |
293afe44 JV |
680 | if (blacklisted) |
681 | return blacklisted; | |
682 | blacklisted = acpi_cpufreq_blacklist(c); | |
683 | if (blacklisted) | |
684 | return blacklisted; | |
1a8e42fa PB |
685 | #endif |
686 | ||
d5b73cd8 | 687 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
1da177e4 | 688 | if (!data) |
64be7eed | 689 | return -ENOMEM; |
1da177e4 | 690 | |
f4fd3797 LT |
691 | if (!zalloc_cpumask_var(&data->freqdomain_cpus, GFP_KERNEL)) { |
692 | result = -ENOMEM; | |
693 | goto err_free; | |
694 | } | |
695 | ||
3427616b | 696 | perf = per_cpu_ptr(acpi_perf_data, cpu); |
8cfcfd39 | 697 | data->acpi_perf_cpu = cpu; |
eb0b3e78 | 698 | policy->driver_data = data; |
1da177e4 | 699 | |
95dd7227 | 700 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) |
fe27cb35 | 701 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 702 | |
3427616b | 703 | result = acpi_processor_register_performance(perf, cpu); |
1da177e4 | 704 | if (result) |
f4fd3797 | 705 | goto err_free_mask; |
1da177e4 | 706 | |
09b4d1ee | 707 | policy->shared_type = perf->shared_type; |
95dd7227 | 708 | |
46f18e3a | 709 | /* |
95dd7227 | 710 | * Will let policy->cpus know about dependency only when software |
46f18e3a VP |
711 | * coordination is required. |
712 | */ | |
713 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 714 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
835481d9 | 715 | cpumask_copy(policy->cpus, perf->shared_cpu_map); |
8adcc0c6 | 716 | } |
f4fd3797 | 717 | cpumask_copy(data->freqdomain_cpus, perf->shared_cpu_map); |
8adcc0c6 VP |
718 | |
719 | #ifdef CONFIG_SMP | |
720 | dmi_check_system(sw_any_bug_dmi_table); | |
2624f90c | 721 | if (bios_with_sw_any_bug && !policy_is_shared(policy)) { |
8adcc0c6 | 722 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; |
3280c3c8 | 723 | cpumask_copy(policy->cpus, topology_core_cpumask(cpu)); |
8adcc0c6 | 724 | } |
acd31624 AP |
725 | |
726 | if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { | |
727 | cpumask_clear(policy->cpus); | |
728 | cpumask_set_cpu(cpu, policy->cpus); | |
3280c3c8 BG |
729 | cpumask_copy(data->freqdomain_cpus, |
730 | topology_sibling_cpumask(cpu)); | |
acd31624 | 731 | policy->shared_type = CPUFREQ_SHARED_TYPE_HW; |
1c5864e2 | 732 | pr_info_once("overriding BIOS provided _PSD data\n"); |
acd31624 | 733 | } |
8adcc0c6 | 734 | #endif |
09b4d1ee | 735 | |
1da177e4 | 736 | /* capability check */ |
09b4d1ee | 737 | if (perf->state_count <= 1) { |
2d06d8c4 | 738 | pr_debug("No P-States\n"); |
1da177e4 LT |
739 | result = -ENODEV; |
740 | goto err_unreg; | |
741 | } | |
09b4d1ee | 742 | |
fe27cb35 VP |
743 | if (perf->control_register.space_id != perf->status_register.space_id) { |
744 | result = -ENODEV; | |
745 | goto err_unreg; | |
746 | } | |
747 | ||
748 | switch (perf->control_register.space_id) { | |
64be7eed | 749 | case ACPI_ADR_SPACE_SYSTEM_IO: |
c40a4518 MG |
750 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
751 | boot_cpu_data.x86 == 0xf) { | |
752 | pr_debug("AMD K8 systems must use native drivers.\n"); | |
753 | result = -ENODEV; | |
754 | goto err_unreg; | |
755 | } | |
2d06d8c4 | 756 | pr_debug("SYSTEM IO addr space\n"); |
dde9f7ba | 757 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
ed757a2c RW |
758 | data->cpu_freq_read = cpu_freq_read_io; |
759 | data->cpu_freq_write = cpu_freq_write_io; | |
dde9f7ba | 760 | break; |
64be7eed | 761 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
2d06d8c4 | 762 | pr_debug("HARDWARE addr space\n"); |
3dc9a633 MG |
763 | if (check_est_cpu(cpu)) { |
764 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
ed757a2c RW |
765 | data->cpu_freq_read = cpu_freq_read_intel; |
766 | data->cpu_freq_write = cpu_freq_write_intel; | |
3dc9a633 | 767 | break; |
dde9f7ba | 768 | } |
3dc9a633 MG |
769 | if (check_amd_hwpstate_cpu(cpu)) { |
770 | data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; | |
ed757a2c RW |
771 | data->cpu_freq_read = cpu_freq_read_amd; |
772 | data->cpu_freq_write = cpu_freq_write_amd; | |
3dc9a633 MG |
773 | break; |
774 | } | |
775 | result = -ENODEV; | |
776 | goto err_unreg; | |
64be7eed | 777 | default: |
2d06d8c4 | 778 | pr_debug("Unknown addr space %d\n", |
64be7eed | 779 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
780 | result = -ENODEV; |
781 | goto err_unreg; | |
782 | } | |
783 | ||
8cee1eed | 784 | freq_table = kzalloc(sizeof(*freq_table) * |
95dd7227 | 785 | (perf->state_count+1), GFP_KERNEL); |
8cee1eed | 786 | if (!freq_table) { |
1da177e4 LT |
787 | result = -ENOMEM; |
788 | goto err_unreg; | |
789 | } | |
790 | ||
791 | /* detect transition latency */ | |
792 | policy->cpuinfo.transition_latency = 0; | |
3a58df35 | 793 | for (i = 0; i < perf->state_count; i++) { |
64be7eed VP |
794 | if ((perf->states[i].transition_latency * 1000) > |
795 | policy->cpuinfo.transition_latency) | |
796 | policy->cpuinfo.transition_latency = | |
797 | perf->states[i].transition_latency * 1000; | |
1da177e4 | 798 | } |
1da177e4 | 799 | |
a59d1637 PV |
800 | /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ |
801 | if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && | |
802 | policy->cpuinfo.transition_latency > 20 * 1000) { | |
a59d1637 | 803 | policy->cpuinfo.transition_latency = 20 * 1000; |
b49c22a6 | 804 | pr_info_once("P-state transition latency capped at 20 uS\n"); |
a59d1637 PV |
805 | } |
806 | ||
1da177e4 | 807 | /* table init */ |
3a58df35 DJ |
808 | for (i = 0; i < perf->state_count; i++) { |
809 | if (i > 0 && perf->states[i].core_frequency >= | |
8cee1eed | 810 | freq_table[valid_states-1].frequency / 1000) |
fe27cb35 VP |
811 | continue; |
812 | ||
8cee1eed VK |
813 | freq_table[valid_states].driver_data = i; |
814 | freq_table[valid_states].frequency = | |
64be7eed | 815 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 816 | valid_states++; |
1da177e4 | 817 | } |
8cee1eed | 818 | freq_table[valid_states].frequency = CPUFREQ_TABLE_END; |
8edc59d9 | 819 | perf->state = 0; |
1da177e4 | 820 | |
8cee1eed | 821 | result = cpufreq_table_validate_and_show(policy, freq_table); |
95dd7227 | 822 | if (result) |
1da177e4 | 823 | goto err_freqfree; |
1da177e4 | 824 | |
d876dfbb | 825 | if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq) |
b49c22a6 | 826 | pr_warn(FW_WARN "P-state 0 is not max freq\n"); |
d876dfbb | 827 | |
a507ac4b | 828 | switch (perf->control_register.space_id) { |
64be7eed | 829 | case ACPI_ADR_SPACE_SYSTEM_IO: |
1bab64d5 VK |
830 | /* |
831 | * The core will not set policy->cur, because | |
832 | * cpufreq_driver->get is NULL, so we need to set it here. | |
833 | * However, we have to guess it, because the current speed is | |
834 | * unknown and not detectable via IO ports. | |
835 | */ | |
dde9f7ba VP |
836 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); |
837 | break; | |
64be7eed | 838 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 839 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba | 840 | break; |
64be7eed | 841 | default: |
dde9f7ba VP |
842 | break; |
843 | } | |
844 | ||
1da177e4 LT |
845 | /* notify BIOS that we exist */ |
846 | acpi_processor_notify_smm(THIS_MODULE); | |
847 | ||
2d06d8c4 | 848 | pr_debug("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 849 | for (i = 0; i < perf->state_count; i++) |
2d06d8c4 | 850 | pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 851 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
852 | (u32) perf->states[i].core_frequency, |
853 | (u32) perf->states[i].power, | |
854 | (u32) perf->states[i].transition_latency); | |
1da177e4 | 855 | |
4b31e774 DB |
856 | /* |
857 | * the first call to ->target() should result in us actually | |
858 | * writing something to the appropriate registers. | |
859 | */ | |
860 | data->resume = 1; | |
64be7eed | 861 | |
b7898fda RW |
862 | policy->fast_switch_possible = !acpi_pstate_strict && |
863 | !(policy_is_shared(policy) && policy->shared_type != CPUFREQ_SHARED_TYPE_ANY); | |
864 | ||
fe27cb35 | 865 | return result; |
1da177e4 | 866 | |
95dd7227 | 867 | err_freqfree: |
8cee1eed | 868 | kfree(freq_table); |
95dd7227 | 869 | err_unreg: |
b2f8dc4c | 870 | acpi_processor_unregister_performance(cpu); |
f4fd3797 LT |
871 | err_free_mask: |
872 | free_cpumask_var(data->freqdomain_cpus); | |
95dd7227 | 873 | err_free: |
1da177e4 | 874 | kfree(data); |
eb0b3e78 | 875 | policy->driver_data = NULL; |
1da177e4 | 876 | |
64be7eed | 877 | return result; |
1da177e4 LT |
878 | } |
879 | ||
64be7eed | 880 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 881 | { |
eb0b3e78 | 882 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 883 | |
2d06d8c4 | 884 | pr_debug("acpi_cpufreq_cpu_exit\n"); |
1da177e4 | 885 | |
9b55f55a VK |
886 | policy->fast_switch_possible = false; |
887 | policy->driver_data = NULL; | |
888 | acpi_processor_unregister_performance(data->acpi_perf_cpu); | |
889 | free_cpumask_var(data->freqdomain_cpus); | |
8cee1eed | 890 | kfree(policy->freq_table); |
9b55f55a | 891 | kfree(data); |
1da177e4 | 892 | |
64be7eed | 893 | return 0; |
1da177e4 LT |
894 | } |
895 | ||
64be7eed | 896 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 897 | { |
eb0b3e78 | 898 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 899 | |
2d06d8c4 | 900 | pr_debug("acpi_cpufreq_resume\n"); |
1da177e4 LT |
901 | |
902 | data->resume = 1; | |
903 | ||
64be7eed | 904 | return 0; |
1da177e4 LT |
905 | } |
906 | ||
64be7eed | 907 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 | 908 | &cpufreq_freq_attr_scaling_available_freqs, |
f4fd3797 | 909 | &freqdomain_cpus, |
f56c50e3 RW |
910 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
911 | &cpb, | |
912 | #endif | |
1da177e4 LT |
913 | NULL, |
914 | }; | |
915 | ||
916 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
db9be219 | 917 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 918 | .target_index = acpi_cpufreq_target, |
b7898fda | 919 | .fast_switch = acpi_cpufreq_fast_switch, |
e2f74f35 TR |
920 | .bios_limit = acpi_processor_get_bios_limit, |
921 | .init = acpi_cpufreq_cpu_init, | |
922 | .exit = acpi_cpufreq_cpu_exit, | |
923 | .resume = acpi_cpufreq_resume, | |
924 | .name = "acpi-cpufreq", | |
e2f74f35 | 925 | .attr = acpi_cpufreq_attr, |
1da177e4 LT |
926 | }; |
927 | ||
615b7300 AP |
928 | static void __init acpi_cpufreq_boost_init(void) |
929 | { | |
930 | if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { | |
931 | msrs = msrs_alloc(); | |
932 | ||
933 | if (!msrs) | |
934 | return; | |
935 | ||
7a6c79f2 | 936 | acpi_cpufreq_driver.set_boost = set_boost; |
cfc9c8ed | 937 | acpi_cpufreq_driver.boost_enabled = boost_state(0); |
0197fbd2 SB |
938 | |
939 | cpu_notifier_register_begin(); | |
615b7300 AP |
940 | |
941 | /* Force all MSRs to the same value */ | |
cfc9c8ed LM |
942 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, |
943 | cpu_online_mask); | |
615b7300 | 944 | |
0197fbd2 | 945 | __register_cpu_notifier(&boost_nb); |
615b7300 | 946 | |
0197fbd2 | 947 | cpu_notifier_register_done(); |
cfc9c8ed | 948 | } |
615b7300 AP |
949 | } |
950 | ||
eb8c68ef | 951 | static void acpi_cpufreq_boost_exit(void) |
615b7300 | 952 | { |
615b7300 AP |
953 | if (msrs) { |
954 | unregister_cpu_notifier(&boost_nb); | |
955 | ||
956 | msrs_free(msrs); | |
957 | msrs = NULL; | |
958 | } | |
959 | } | |
960 | ||
64be7eed | 961 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 962 | { |
50109292 FY |
963 | int ret; |
964 | ||
75c07581 RW |
965 | if (acpi_disabled) |
966 | return -ENODEV; | |
967 | ||
8a61e12e YL |
968 | /* don't keep reloading if cpufreq_driver exists */ |
969 | if (cpufreq_get_current_driver()) | |
75c07581 | 970 | return -EEXIST; |
ee297533 | 971 | |
2d06d8c4 | 972 | pr_debug("acpi_cpufreq_init\n"); |
1da177e4 | 973 | |
50109292 FY |
974 | ret = acpi_cpufreq_early_init(); |
975 | if (ret) | |
976 | return ret; | |
09b4d1ee | 977 | |
11269ff5 AP |
978 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
979 | /* this is a sysfs file with a strange name and an even stranger | |
980 | * semantic - per CPU instantiation, but system global effect. | |
981 | * Lets enable it only on AMD CPUs for compatibility reasons and | |
982 | * only if configured. This is considered legacy code, which | |
983 | * will probably be removed at some point in the future. | |
984 | */ | |
f56c50e3 RW |
985 | if (!check_amd_hwpstate_cpu(0)) { |
986 | struct freq_attr **attr; | |
11269ff5 | 987 | |
f56c50e3 | 988 | pr_debug("CPB unsupported, do not expose it\n"); |
11269ff5 | 989 | |
f56c50e3 RW |
990 | for (attr = acpi_cpufreq_attr; *attr; attr++) |
991 | if (*attr == &cpb) { | |
992 | *attr = NULL; | |
993 | break; | |
994 | } | |
11269ff5 AP |
995 | } |
996 | #endif | |
cfc9c8ed | 997 | acpi_cpufreq_boost_init(); |
11269ff5 | 998 | |
847aef6f | 999 | ret = cpufreq_register_driver(&acpi_cpufreq_driver); |
eb8c68ef | 1000 | if (ret) { |
2fdf66b4 | 1001 | free_acpi_perf_data(); |
eb8c68ef KRW |
1002 | acpi_cpufreq_boost_exit(); |
1003 | } | |
847aef6f | 1004 | return ret; |
1da177e4 LT |
1005 | } |
1006 | ||
64be7eed | 1007 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 1008 | { |
2d06d8c4 | 1009 | pr_debug("acpi_cpufreq_exit\n"); |
1da177e4 | 1010 | |
615b7300 AP |
1011 | acpi_cpufreq_boost_exit(); |
1012 | ||
1da177e4 LT |
1013 | cpufreq_unregister_driver(&acpi_cpufreq_driver); |
1014 | ||
50f4ddd4 | 1015 | free_acpi_perf_data(); |
1da177e4 LT |
1016 | } |
1017 | ||
d395bf12 | 1018 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed | 1019 | MODULE_PARM_DESC(acpi_pstate_strict, |
95dd7227 DJ |
1020 | "value 0 or non-zero. non-zero -> strict ACPI checks are " |
1021 | "performed during frequency changes."); | |
1da177e4 LT |
1022 | |
1023 | late_initcall(acpi_cpufreq_init); | |
1024 | module_exit(acpi_cpufreq_exit); | |
1025 | ||
efa17194 MG |
1026 | static const struct x86_cpu_id acpi_cpufreq_ids[] = { |
1027 | X86_FEATURE_MATCH(X86_FEATURE_ACPI), | |
1028 | X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), | |
1029 | {} | |
1030 | }; | |
1031 | MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); | |
1032 | ||
c655affb RW |
1033 | static const struct acpi_device_id processor_device_ids[] = { |
1034 | {ACPI_PROCESSOR_OBJECT_HID, }, | |
1035 | {ACPI_PROCESSOR_DEVICE_HID, }, | |
1036 | {}, | |
1037 | }; | |
1038 | MODULE_DEVICE_TABLE(acpi, processor_device_ids); | |
1039 | ||
1da177e4 | 1040 | MODULE_ALIAS("acpi"); |