[media] vb2: fix nasty vb2_thread regression
[deliverable/linux.git] / drivers / cpufreq / cpufreq-dt.c
CommitLineData
95ceafd4
SG
1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
748c8766
VK
4 * Copyright (C) 2014 Linaro.
5 * Viresh Kumar <viresh.kumar@linaro.org>
6 *
bbcf0719 7 * The OPP code in function set_target() is reused from
95ceafd4
SG
8 * drivers/cpufreq/omap-cpufreq.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/clk.h>
e1825b25 18#include <linux/cpu.h>
77cff592 19#include <linux/cpu_cooling.h>
95ceafd4 20#include <linux/cpufreq.h>
34e5a527 21#include <linux/cpufreq-dt.h>
77cff592 22#include <linux/cpumask.h>
95ceafd4
SG
23#include <linux/err.h>
24#include <linux/module.h>
25#include <linux/of.h>
e4db1c74 26#include <linux/pm_opp.h>
5553f9e2 27#include <linux/platform_device.h>
95ceafd4
SG
28#include <linux/regulator/consumer.h>
29#include <linux/slab.h>
77cff592 30#include <linux/thermal.h>
95ceafd4 31
d2f31f1d
VK
32struct private_data {
33 struct device *cpu_dev;
34 struct regulator *cpu_reg;
35 struct thermal_cooling_device *cdev;
36 unsigned int voltage_tolerance; /* in percentage */
37};
95ceafd4 38
21c36d35
BZ
39static struct freq_attr *cpufreq_dt_attr[] = {
40 &cpufreq_freq_attr_scaling_available_freqs,
41 NULL, /* Extra space for boost-attr if required */
42 NULL,
43};
44
bbcf0719 45static int set_target(struct cpufreq_policy *policy, unsigned int index)
95ceafd4 46{
47d43ba7 47 struct dev_pm_opp *opp;
d2f31f1d
VK
48 struct cpufreq_frequency_table *freq_table = policy->freq_table;
49 struct clk *cpu_clk = policy->clk;
50 struct private_data *priv = policy->driver_data;
51 struct device *cpu_dev = priv->cpu_dev;
52 struct regulator *cpu_reg = priv->cpu_reg;
929ca89c
AH
53 unsigned long volt = 0, tol = 0;
54 int volt_old = 0;
d4019f0a 55 unsigned int old_freq, new_freq;
0ca68436 56 long freq_Hz, freq_exact;
95ceafd4
SG
57 int ret;
58
95ceafd4 59 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
2209b0c9 60 if (freq_Hz <= 0)
95ceafd4 61 freq_Hz = freq_table[index].frequency * 1000;
95ceafd4 62
d4019f0a
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63 freq_exact = freq_Hz;
64 new_freq = freq_Hz / 1000;
65 old_freq = clk_get_rate(cpu_clk) / 1000;
95ceafd4 66
4a511de9 67 if (!IS_ERR(cpu_reg)) {
0a1e879d
SW
68 unsigned long opp_freq;
69
78e8eb8f 70 rcu_read_lock();
5d4879cd 71 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
95ceafd4 72 if (IS_ERR(opp)) {
78e8eb8f 73 rcu_read_unlock();
fbd48ca5
VK
74 dev_err(cpu_dev, "failed to find OPP for %ld\n",
75 freq_Hz);
d4019f0a 76 return PTR_ERR(opp);
95ceafd4 77 }
5d4879cd 78 volt = dev_pm_opp_get_voltage(opp);
0a1e879d 79 opp_freq = dev_pm_opp_get_freq(opp);
78e8eb8f 80 rcu_read_unlock();
d2f31f1d 81 tol = volt * priv->voltage_tolerance / 100;
95ceafd4 82 volt_old = regulator_get_voltage(cpu_reg);
0a1e879d
SW
83 dev_dbg(cpu_dev, "Found OPP: %ld kHz, %ld uV\n",
84 opp_freq / 1000, volt);
95ceafd4
SG
85 }
86
929ca89c 87 dev_dbg(cpu_dev, "%u MHz, %d mV --> %u MHz, %ld mV\n",
8197bb1b 88 old_freq / 1000, (volt_old > 0) ? volt_old / 1000 : -1,
fbd48ca5 89 new_freq / 1000, volt ? volt / 1000 : -1);
95ceafd4
SG
90
91 /* scaling up? scale voltage before frequency */
d4019f0a 92 if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
95ceafd4
SG
93 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
94 if (ret) {
fbd48ca5
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95 dev_err(cpu_dev, "failed to scale voltage up: %d\n",
96 ret);
d4019f0a 97 return ret;
95ceafd4
SG
98 }
99 }
100
0ca68436 101 ret = clk_set_rate(cpu_clk, freq_exact);
95ceafd4 102 if (ret) {
fbd48ca5 103 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
8197bb1b 104 if (!IS_ERR(cpu_reg) && volt_old > 0)
95ceafd4 105 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
d4019f0a 106 return ret;
95ceafd4
SG
107 }
108
109 /* scaling down? scale voltage after frequency */
d4019f0a 110 if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
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SG
111 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
112 if (ret) {
fbd48ca5
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113 dev_err(cpu_dev, "failed to scale voltage down: %d\n",
114 ret);
d4019f0a 115 clk_set_rate(cpu_clk, old_freq * 1000);
95ceafd4
SG
116 }
117 }
118
fd143b4d 119 return ret;
95ceafd4
SG
120}
121
95b61058 122static int allocate_resources(int cpu, struct device **cdev,
d2f31f1d 123 struct regulator **creg, struct clk **cclk)
95ceafd4 124{
d2f31f1d
VK
125 struct device *cpu_dev;
126 struct regulator *cpu_reg;
127 struct clk *cpu_clk;
128 int ret = 0;
2d2c5e0e 129 char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg;
95ceafd4 130
95b61058 131 cpu_dev = get_cpu_device(cpu);
e1825b25 132 if (!cpu_dev) {
95b61058 133 pr_err("failed to get cpu%d device\n", cpu);
e1825b25
SK
134 return -ENODEV;
135 }
6754f556 136
2d2c5e0e 137 /* Try "cpu0" for older DTs */
95b61058
VK
138 if (!cpu)
139 reg = reg_cpu0;
140 else
141 reg = reg_cpu;
2d2c5e0e
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142
143try_again:
144 cpu_reg = regulator_get_optional(cpu_dev, reg);
fc31d6f5
NM
145 if (IS_ERR(cpu_reg)) {
146 /*
95b61058 147 * If cpu's regulator supply node is present, but regulator is
fc31d6f5
NM
148 * not yet registered, we should try defering probe.
149 */
150 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
95b61058
VK
151 dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n",
152 cpu);
d2f31f1d 153 return -EPROBE_DEFER;
fc31d6f5 154 }
2d2c5e0e
VK
155
156 /* Try with "cpu-supply" */
157 if (reg == reg_cpu0) {
158 reg = reg_cpu;
159 goto try_again;
160 }
161
a00de1ab
TP
162 dev_dbg(cpu_dev, "no regulator for cpu%d: %ld\n",
163 cpu, PTR_ERR(cpu_reg));
fc31d6f5
NM
164 }
165
e3beb0ac 166 cpu_clk = clk_get(cpu_dev, NULL);
95ceafd4 167 if (IS_ERR(cpu_clk)) {
d2f31f1d
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168 /* put regulator */
169 if (!IS_ERR(cpu_reg))
170 regulator_put(cpu_reg);
171
95ceafd4 172 ret = PTR_ERR(cpu_clk);
48a8624b
VK
173
174 /*
175 * If cpu's clk node is present, but clock is not yet
176 * registered, we should try defering probe.
177 */
178 if (ret == -EPROBE_DEFER)
95b61058 179 dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu);
48a8624b 180 else
71796210
AK
181 dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", cpu,
182 ret);
d2f31f1d
VK
183 } else {
184 *cdev = cpu_dev;
185 *creg = cpu_reg;
186 *cclk = cpu_clk;
187 }
188
189 return ret;
190}
191
bbcf0719 192static int cpufreq_init(struct cpufreq_policy *policy)
d2f31f1d
VK
193{
194 struct cpufreq_frequency_table *freq_table;
d2f31f1d
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195 struct device_node *np;
196 struct private_data *priv;
197 struct device *cpu_dev;
198 struct regulator *cpu_reg;
199 struct clk *cpu_clk;
953ba9ff 200 struct dev_pm_opp *suspend_opp;
045ee45c 201 unsigned long min_uV = ~0, max_uV = 0;
d2f31f1d 202 unsigned int transition_latency;
2e02d872 203 bool need_update = false;
d2f31f1d
VK
204 int ret;
205
95b61058 206 ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk);
d2f31f1d 207 if (ret) {
edd52b1c 208 pr_err("%s: Failed to allocate resources: %d\n", __func__, ret);
d2f31f1d
VK
209 return ret;
210 }
48a8624b 211
d2f31f1d
VK
212 np = of_node_get(cpu_dev->of_node);
213 if (!np) {
214 dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
215 ret = -ENOENT;
216 goto out_put_reg_clk;
95ceafd4
SG
217 }
218
2e02d872 219 /* Get OPP-sharing information from "operating-points-v2" bindings */
8f8d37b2 220 ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, policy->cpus);
2e02d872
VK
221 if (ret) {
222 /*
223 * operating-points-v2 not supported, fallback to old method of
224 * finding shared-OPPs for backward compatibility.
225 */
226 if (ret == -ENOENT)
227 need_update = true;
228 else
229 goto out_node_put;
230 }
231
232 /*
233 * Initialize OPP tables for all policy->cpus. They will be shared by
234 * all CPUs which have marked their CPUs shared with OPP bindings.
235 *
236 * For platforms not using operating-points-v2 bindings, we do this
237 * before updating policy->cpus. Otherwise, we will end up creating
238 * duplicate OPPs for policy->cpus.
239 *
240 * OPPs might be populated at runtime, don't check for error here
241 */
8f8d37b2 242 dev_pm_opp_of_cpumask_add_table(policy->cpus);
2e02d872 243
7d5d0c8b
VK
244 /*
245 * But we need OPP table to function so if it is not there let's
246 * give platform code chance to provide it for us.
247 */
248 ret = dev_pm_opp_get_opp_count(cpu_dev);
249 if (ret <= 0) {
250 pr_debug("OPP table is not ready, deferring probe\n");
251 ret = -EPROBE_DEFER;
252 goto out_free_opp;
253 }
254
2e02d872
VK
255 if (need_update) {
256 struct cpufreq_dt_platform_data *pd = cpufreq_get_driver_data();
257
258 if (!pd || !pd->independent_clocks)
259 cpumask_setall(policy->cpus);
260
261 /*
262 * OPP tables are initialized only for policy->cpu, do it for
263 * others as well.
264 */
8f8d37b2 265 ret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
8bc86284
VK
266 if (ret)
267 dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n",
268 __func__, ret);
2e02d872
VK
269
270 of_property_read_u32(np, "clock-latency", &transition_latency);
271 } else {
272 transition_latency = dev_pm_opp_get_max_clock_latency(cpu_dev);
273 }
95ceafd4 274
d2f31f1d
VK
275 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
276 if (!priv) {
277 ret = -ENOMEM;
2f0f609f 278 goto out_free_opp;
95ceafd4
SG
279 }
280
d2f31f1d 281 of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
95ceafd4 282
2e02d872 283 if (!transition_latency)
95ceafd4
SG
284 transition_latency = CPUFREQ_ETERNAL;
285
43c638e3 286 if (!IS_ERR(cpu_reg)) {
045ee45c 287 unsigned long opp_freq = 0;
95ceafd4
SG
288
289 /*
045ee45c
LS
290 * Disable any OPPs where the connected regulator isn't able to
291 * provide the specified voltage and record minimum and maximum
292 * voltage levels.
95ceafd4 293 */
045ee45c
LS
294 while (1) {
295 struct dev_pm_opp *opp;
296 unsigned long opp_uV, tol_uV;
297
298 rcu_read_lock();
299 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq);
300 if (IS_ERR(opp)) {
301 rcu_read_unlock();
302 break;
303 }
304 opp_uV = dev_pm_opp_get_voltage(opp);
305 rcu_read_unlock();
306
307 tol_uV = opp_uV * priv->voltage_tolerance / 100;
a2022001
VK
308 if (regulator_is_supported_voltage(cpu_reg,
309 opp_uV - tol_uV,
045ee45c
LS
310 opp_uV + tol_uV)) {
311 if (opp_uV < min_uV)
312 min_uV = opp_uV;
313 if (opp_uV > max_uV)
314 max_uV = opp_uV;
315 } else {
316 dev_pm_opp_disable(cpu_dev, opp_freq);
317 }
318
319 opp_freq++;
320 }
321
95ceafd4
SG
322 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
323 if (ret > 0)
324 transition_latency += ret * 1000;
325 }
326
045ee45c
LS
327 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
328 if (ret) {
329 pr_err("failed to init cpufreq table: %d\n", ret);
330 goto out_free_priv;
331 }
332
d2f31f1d
VK
333 priv->cpu_dev = cpu_dev;
334 priv->cpu_reg = cpu_reg;
335 policy->driver_data = priv;
336
337 policy->clk = cpu_clk;
953ba9ff
BZ
338
339 rcu_read_lock();
340 suspend_opp = dev_pm_opp_get_suspend_opp(cpu_dev);
341 if (suspend_opp)
342 policy->suspend_freq = dev_pm_opp_get_freq(suspend_opp) / 1000;
343 rcu_read_unlock();
344
34e5a527
TP
345 ret = cpufreq_table_validate_and_show(policy, freq_table);
346 if (ret) {
347 dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
348 ret);
9a004428 349 goto out_free_cpufreq_table;
d15fa862
VK
350 }
351
352 /* Support turbo/boost mode */
353 if (policy_has_boost_freq(policy)) {
354 /* This gets disabled by core on driver unregister */
355 ret = cpufreq_enable_boost_support();
356 if (ret)
357 goto out_free_cpufreq_table;
21c36d35 358 cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;
34e5a527
TP
359 }
360
361 policy->cpuinfo.transition_latency = transition_latency;
362
f9739d27
LS
363 of_node_put(np);
364
95ceafd4
SG
365 return 0;
366
9a004428 367out_free_cpufreq_table:
5d4879cd 368 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
045ee45c
LS
369out_free_priv:
370 kfree(priv);
2f0f609f 371out_free_opp:
8f8d37b2 372 dev_pm_opp_of_cpumask_remove_table(policy->cpus);
2e02d872 373out_node_put:
d2f31f1d
VK
374 of_node_put(np);
375out_put_reg_clk:
ed4b053c 376 clk_put(cpu_clk);
e3beb0ac
LS
377 if (!IS_ERR(cpu_reg))
378 regulator_put(cpu_reg);
d2f31f1d
VK
379
380 return ret;
381}
382
bbcf0719 383static int cpufreq_exit(struct cpufreq_policy *policy)
d2f31f1d
VK
384{
385 struct private_data *priv = policy->driver_data;
386
17ad13ba 387 cpufreq_cooling_unregister(priv->cdev);
d2f31f1d 388 dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
8f8d37b2 389 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
d2f31f1d
VK
390 clk_put(policy->clk);
391 if (!IS_ERR(priv->cpu_reg))
392 regulator_put(priv->cpu_reg);
393 kfree(priv);
394
395 return 0;
396}
397
9a004428
VK
398static void cpufreq_ready(struct cpufreq_policy *policy)
399{
400 struct private_data *priv = policy->driver_data;
401 struct device_node *np = of_node_get(priv->cpu_dev->of_node);
402
403 if (WARN_ON(!np))
404 return;
405
406 /*
407 * For now, just loading the cooling device;
408 * thermal DT code takes care of matching them.
409 */
410 if (of_find_property(np, "#cooling-cells", NULL)) {
f8fa8ae0
PA
411 u32 power_coefficient = 0;
412
413 of_property_read_u32(np, "dynamic-power-coefficient",
414 &power_coefficient);
415
416 priv->cdev = of_cpufreq_power_cooling_register(np,
417 policy->related_cpus, power_coefficient, NULL);
9a004428
VK
418 if (IS_ERR(priv->cdev)) {
419 dev_err(priv->cpu_dev,
420 "running cpufreq without cooling device: %ld\n",
421 PTR_ERR(priv->cdev));
422
423 priv->cdev = NULL;
424 }
425 }
426
427 of_node_put(np);
428}
429
bbcf0719 430static struct cpufreq_driver dt_cpufreq_driver = {
d2f31f1d
VK
431 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
432 .verify = cpufreq_generic_frequency_table_verify,
bbcf0719 433 .target_index = set_target,
d2f31f1d 434 .get = cpufreq_generic_get,
bbcf0719
VK
435 .init = cpufreq_init,
436 .exit = cpufreq_exit,
9a004428 437 .ready = cpufreq_ready,
bbcf0719 438 .name = "cpufreq-dt",
21c36d35 439 .attr = cpufreq_dt_attr,
953ba9ff 440 .suspend = cpufreq_generic_suspend,
d2f31f1d
VK
441};
442
bbcf0719 443static int dt_cpufreq_probe(struct platform_device *pdev)
d2f31f1d
VK
444{
445 struct device *cpu_dev;
446 struct regulator *cpu_reg;
447 struct clk *cpu_clk;
448 int ret;
449
450 /*
451 * All per-cluster (CPUs sharing clock/voltages) initialization is done
452 * from ->init(). In probe(), we just need to make sure that clk and
453 * regulators are available. Else defer probe and retry.
454 *
455 * FIXME: Is checking this only for CPU0 sufficient ?
456 */
95b61058 457 ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk);
d2f31f1d
VK
458 if (ret)
459 return ret;
460
461 clk_put(cpu_clk);
462 if (!IS_ERR(cpu_reg))
463 regulator_put(cpu_reg);
464
34e5a527
TP
465 dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev);
466
bbcf0719 467 ret = cpufreq_register_driver(&dt_cpufreq_driver);
d2f31f1d
VK
468 if (ret)
469 dev_err(cpu_dev, "failed register driver: %d\n", ret);
470
95ceafd4
SG
471 return ret;
472}
5553f9e2 473
bbcf0719 474static int dt_cpufreq_remove(struct platform_device *pdev)
5553f9e2 475{
bbcf0719 476 cpufreq_unregister_driver(&dt_cpufreq_driver);
5553f9e2
SG
477 return 0;
478}
479
bbcf0719 480static struct platform_driver dt_cpufreq_platdrv = {
5553f9e2 481 .driver = {
bbcf0719 482 .name = "cpufreq-dt",
5553f9e2 483 },
bbcf0719
VK
484 .probe = dt_cpufreq_probe,
485 .remove = dt_cpufreq_remove,
5553f9e2 486};
bbcf0719 487module_platform_driver(dt_cpufreq_platdrv);
95ceafd4 488
07949bf9 489MODULE_ALIAS("platform:cpufreq-dt");
748c8766 490MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
95ceafd4 491MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
bbcf0719 492MODULE_DESCRIPTION("Generic cpufreq driver");
95ceafd4 493MODULE_LICENSE("GPL");
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