Commit | Line | Data |
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7c1a70e9 | 1 | /* |
7c1a70e9 MP |
2 | * Copyright (C) STMicroelectronics 2009 |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
4 | * | |
5 | * License Terms: GNU General Public License v2 | |
7c1a70e9 MP |
6 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> |
7 | * Author: Martin Persson <martin.persson@stericsson.com> | |
8 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> | |
9 | * | |
10 | */ | |
7c1a70e9 MP |
11 | #include <linux/kernel.h> |
12 | #include <linux/cpufreq.h> | |
13 | #include <linux/delay.h> | |
72b2fd5c | 14 | #include <linux/slab.h> |
73180f85 | 15 | #include <linux/mfd/dbx500-prcmu.h> |
72b2fd5c | 16 | #include <mach/id.h> |
7c1a70e9 MP |
17 | |
18 | static struct cpufreq_frequency_table freq_table[] = { | |
19 | [0] = { | |
20 | .index = 0, | |
6283e328 | 21 | .frequency = 200000, |
7c1a70e9 MP |
22 | }, |
23 | [1] = { | |
24 | .index = 1, | |
6283e328 | 25 | .frequency = 300000, |
7c1a70e9 MP |
26 | }, |
27 | [2] = { | |
28 | .index = 2, | |
6283e328 | 29 | .frequency = 600000, |
7c1a70e9 MP |
30 | }, |
31 | [3] = { | |
6283e328 | 32 | /* Used for MAX_OPP, if available */ |
7c1a70e9 MP |
33 | .index = 3, |
34 | .frequency = CPUFREQ_TABLE_END, | |
35 | }, | |
6283e328 LW |
36 | [4] = { |
37 | .index = 4, | |
38 | .frequency = CPUFREQ_TABLE_END, | |
39 | }, | |
7c1a70e9 MP |
40 | }; |
41 | ||
72b2fd5c | 42 | static enum arm_opp idx2opp[] = { |
6283e328 | 43 | ARM_EXTCLK, |
72b2fd5c LW |
44 | ARM_50_OPP, |
45 | ARM_100_OPP, | |
46 | ARM_MAX_OPP | |
47 | }; | |
48 | ||
49 | static struct freq_attr *db8500_cpufreq_attr[] = { | |
50 | &cpufreq_freq_attr_scaling_available_freqs, | |
51 | NULL, | |
7c1a70e9 MP |
52 | }; |
53 | ||
72b2fd5c | 54 | static int db8500_cpufreq_verify_speed(struct cpufreq_policy *policy) |
7c1a70e9 MP |
55 | { |
56 | return cpufreq_frequency_table_verify(policy, freq_table); | |
57 | } | |
58 | ||
72b2fd5c | 59 | static int db8500_cpufreq_target(struct cpufreq_policy *policy, |
7c1a70e9 MP |
60 | unsigned int target_freq, |
61 | unsigned int relation) | |
62 | { | |
63 | struct cpufreq_freqs freqs; | |
72b2fd5c | 64 | unsigned int idx; |
7c1a70e9 | 65 | |
72b2fd5c | 66 | /* scale the target frequency to one of the extremes supported */ |
7c1a70e9 MP |
67 | if (target_freq < policy->cpuinfo.min_freq) |
68 | target_freq = policy->cpuinfo.min_freq; | |
69 | if (target_freq > policy->cpuinfo.max_freq) | |
70 | target_freq = policy->cpuinfo.max_freq; | |
71 | ||
72b2fd5c LW |
72 | /* Lookup the next frequency */ |
73 | if (cpufreq_frequency_table_target | |
74 | (policy, freq_table, target_freq, relation, &idx)) { | |
75 | return -EINVAL; | |
7c1a70e9 MP |
76 | } |
77 | ||
78 | freqs.old = policy->cur; | |
72b2fd5c | 79 | freqs.new = freq_table[idx].frequency; |
7c1a70e9 | 80 | |
72b2fd5c | 81 | if (freqs.old == freqs.new) |
7c1a70e9 | 82 | return 0; |
7c1a70e9 | 83 | |
72b2fd5c | 84 | /* pre-change notification */ |
8efd072b VG |
85 | for_each_cpu(freqs.cpu, policy->cpus) |
86 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
7c1a70e9 | 87 | |
72b2fd5c LW |
88 | /* request the PRCM unit for opp change */ |
89 | if (prcmu_set_arm_opp(idx2opp[idx])) { | |
90 | pr_err("db8500-cpufreq: Failed to set OPP level\n"); | |
91 | return -EINVAL; | |
7c1a70e9 MP |
92 | } |
93 | ||
72b2fd5c | 94 | /* post change notification */ |
8efd072b VG |
95 | for_each_cpu(freqs.cpu, policy->cpus) |
96 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
7c1a70e9 | 97 | |
72b2fd5c | 98 | return 0; |
7c1a70e9 MP |
99 | } |
100 | ||
72b2fd5c | 101 | static unsigned int db8500_cpufreq_getspeed(unsigned int cpu) |
7c1a70e9 MP |
102 | { |
103 | int i; | |
72b2fd5c LW |
104 | /* request the prcm to get the current ARM opp */ |
105 | for (i = 0; prcmu_get_arm_opp() != idx2opp[i]; i++) | |
7c1a70e9 MP |
106 | ; |
107 | return freq_table[i].frequency; | |
108 | } | |
109 | ||
72b2fd5c | 110 | static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy) |
7c1a70e9 | 111 | { |
eb0b38a5 | 112 | int i, res; |
7c1a70e9 | 113 | |
72b2fd5c | 114 | BUILD_BUG_ON(ARRAY_SIZE(idx2opp) + 1 != ARRAY_SIZE(freq_table)); |
7c1a70e9 | 115 | |
6283e328 LW |
116 | if (!prcmu_is_u8400()) { |
117 | freq_table[1].frequency = 400000; | |
118 | freq_table[2].frequency = 800000; | |
7c1a70e9 | 119 | if (prcmu_has_arm_maxopp()) |
6283e328 | 120 | freq_table[3].frequency = 1000000; |
7c1a70e9 | 121 | } |
6283e328 | 122 | pr_info("db8500-cpufreq : Available frequencies:\n"); |
eb0b38a5 AL |
123 | for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) |
124 | pr_info(" %d Mhz\n", freq_table[i].frequency/1000); | |
7c1a70e9 MP |
125 | |
126 | /* get policy fields based on the table */ | |
127 | res = cpufreq_frequency_table_cpuinfo(policy, freq_table); | |
128 | if (!res) | |
129 | cpufreq_frequency_table_get_attr(freq_table, policy->cpu); | |
130 | else { | |
72b2fd5c | 131 | pr_err("db8500-cpufreq : Failed to read policy table\n"); |
7c1a70e9 MP |
132 | return res; |
133 | } | |
134 | ||
135 | policy->min = policy->cpuinfo.min_freq; | |
136 | policy->max = policy->cpuinfo.max_freq; | |
72b2fd5c | 137 | policy->cur = db8500_cpufreq_getspeed(policy->cpu); |
7c1a70e9 MP |
138 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; |
139 | ||
140 | /* | |
141 | * FIXME : Need to take time measurement across the target() | |
142 | * function with no/some/all drivers in the notification | |
143 | * list. | |
144 | */ | |
72b2fd5c | 145 | policy->cpuinfo.transition_latency = 20 * 1000; /* in ns */ |
7c1a70e9 MP |
146 | |
147 | /* policy sharing between dual CPUs */ | |
148 | cpumask_copy(policy->cpus, &cpu_present_map); | |
149 | ||
150 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
151 | ||
7c1a70e9 MP |
152 | return 0; |
153 | } | |
154 | ||
72b2fd5c LW |
155 | static struct cpufreq_driver db8500_cpufreq_driver = { |
156 | .flags = CPUFREQ_STICKY, | |
157 | .verify = db8500_cpufreq_verify_speed, | |
158 | .target = db8500_cpufreq_target, | |
159 | .get = db8500_cpufreq_getspeed, | |
160 | .init = db8500_cpufreq_init, | |
161 | .name = "DB8500", | |
162 | .attr = db8500_cpufreq_attr, | |
7c1a70e9 MP |
163 | }; |
164 | ||
72b2fd5c | 165 | static int __init db8500_cpufreq_register(void) |
7c1a70e9 | 166 | { |
72b2fd5c LW |
167 | if (!cpu_is_u8500v20_or_later()) |
168 | return -ENODEV; | |
7c1a70e9 | 169 | |
72b2fd5c LW |
170 | pr_info("cpufreq for DB8500 started\n"); |
171 | return cpufreq_register_driver(&db8500_cpufreq_driver); | |
7c1a70e9 | 172 | } |
72b2fd5c | 173 | device_initcall(db8500_cpufreq_register); |