[deliverable/linux.git] / drivers / cpufreq / exynos4x12-cpufreq.c

/*
 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4X12 - CPU frequency scaling support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/cpufreq.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include "exynos-cpufreq.h"

static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;
static struct exynos_dvfs_info *cpufreq;

static unsigned int exynos4x12_volt_table[] = {
	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
	1000000,  987500,  975000,  950000,  925000,  900000,  900000
};

static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
	{CPUFREQ_BOOST_FREQ, L0, 1500 * 1000},
	{0, L1, 1400 * 1000},
	{0, L2, 1300 * 1000},
	{0, L3, 1200 * 1000},
	{0, L4, 1100 * 1000},
	{0, L5, 1000 * 1000},
	{0, L6,  900 * 1000},
	{0, L7,  800 * 1000},
	{0, L8,  700 * 1000},
	{0, L9,  600 * 1000},
	{0, L10, 500 * 1000},
	{0, L11, 400 * 1000},
	{0, L12, 300 * 1000},
	{0, L13, 200 * 1000},
	{0, 0, CPUFREQ_TABLE_END},
};

static struct apll_freq *apll_freq_4x12;

static struct apll_freq apll_freq_4212[] = {
	/*
	 * values:
	 * freq
	 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
	 * clock divider for COPY, HPM, RESERVED
	 * PLL M, P, S
	 */
	APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
	APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
	APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
	APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
	APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
	APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
	APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
	APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
	APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
	APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
	APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
	APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
	APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
	APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
};

static struct apll_freq apll_freq_4412[] = {
	/*
	 * values:
	 * freq
	 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
	 * clock divider for COPY, HPM, CORES
	 * PLL M, P, S
	 */
	APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
	APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
	APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
	APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
	APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
	APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
	APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
	APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
	APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
	APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
	APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
	APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
	APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
	APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
};

static void exynos4x12_set_clkdiv(unsigned int div_index)
{
	unsigned int tmp;

	/* Change Divider - CPU0 */

	tmp = apll_freq_4x12[div_index].clk_div_cpu0;

	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);

	while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
	       & 0x11111111)
		cpu_relax();

	/* Change Divider - CPU1 */
	tmp = apll_freq_4x12[div_index].clk_div_cpu1;

	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);

	do {
		cpu_relax();
		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
	} while (tmp != 0x0);
}

static void exynos4x12_set_apll(unsigned int index)
{
	unsigned int tmp, freq = apll_freq_4x12[index].freq;

	/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
	clk_set_parent(moutcore, mout_mpll);

	do {
		cpu_relax();
		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
		tmp &= 0x7;
	} while (tmp != 0x2);

	clk_set_rate(mout_apll, freq * 1000);

	/* MUX_CORE_SEL = APLL */
	clk_set_parent(moutcore, mout_apll);

	do {
		cpu_relax();
		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
}

static void exynos4x12_set_frequency(unsigned int old_index,
				  unsigned int new_index)
{
	if (old_index > new_index) {
		exynos4x12_set_clkdiv(new_index);
		exynos4x12_set_apll(new_index);
	} else if (old_index < new_index) {
		exynos4x12_set_apll(new_index);
		exynos4x12_set_clkdiv(new_index);
	}
}

int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
{
	struct device_node *np;
	unsigned long rate;

	/*
	 * HACK: This is a temporary workaround to get access to clock
	 * controller registers directly and remove static mappings and
	 * dependencies on platform headers. It is necessary to enable
	 * Exynos multi-platform support and will be removed together with
	 * this whole driver as soon as Exynos gets migrated to use
	 * cpufreq-dt driver.
	 */
	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
	if (!np) {
		pr_err("%s: failed to find clock controller DT node\n",
			__func__);
		return -ENODEV;
	}

	info->cmu_regs = of_iomap(np, 0);
	if (!info->cmu_regs) {
		pr_err("%s: failed to map CMU registers\n", __func__);
		return -EFAULT;
	}

	cpu_clk = clk_get(NULL, "armclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	moutcore = clk_get(NULL, "moutcore");
	if (IS_ERR(moutcore))
		goto err_moutcore;

	mout_mpll = clk_get(NULL, "mout_mpll");
	if (IS_ERR(mout_mpll))
		goto err_mout_mpll;

	rate = clk_get_rate(mout_mpll) / 1000;

	mout_apll = clk_get(NULL, "mout_apll");
	if (IS_ERR(mout_apll))
		goto err_mout_apll;

	if (info->type == EXYNOS_SOC_4212)
		apll_freq_4x12 = apll_freq_4212;
	else
		apll_freq_4x12 = apll_freq_4412;

	info->mpll_freq_khz = rate;
	/* 800Mhz */
	info->pll_safe_idx = L7;
	info->cpu_clk = cpu_clk;
	info->volt_table = exynos4x12_volt_table;
	info->freq_table = exynos4x12_freq_table;
	info->set_freq = exynos4x12_set_frequency;

	cpufreq = info;

	return 0;

err_mout_apll:
	clk_put(mout_mpll);
err_mout_mpll:
	clk_put(moutcore);
err_moutcore:
	clk_put(cpu_clk);

	pr_debug("%s: failed initialization\n", __func__);
	return -EINVAL;
}
Commit	Line	Data
a35c5051 JL	1	/*
	2	* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* EXYNOS4X12 - CPU frequency scaling support
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
	16	#include <linux/io.h>
	17	#include <linux/slab.h>
	18	#include <linux/cpufreq.h>
4c8d8193 TF	19	#include <linux/of.h>
4c8d8193 TF	20	#include <linux/of_address.h>
a35c5051	21
c4aaa295	22	#include "exynos-cpufreq.h"
a35c5051	23
a35c5051 JL	24	static struct clk *cpu_clk;
	25	static struct clk *moutcore;
	26	static struct clk *mout_mpll;
	27	static struct clk *mout_apll;
4c8d8193	28	static struct exynos_dvfs_info *cpufreq;
a35c5051	29
9d0554ff JC	30	static unsigned int exynos4x12_volt_table[] = {
	31	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
	32	1000000, 987500, 975000, 950000, 925000, 900000, 900000
a35c5051 JL	33	};
a35c5051 JL	34
a35c5051	35	static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
7f4b0461 VK	36	{CPUFREQ_BOOST_FREQ, L0, 1500 * 1000},
	37	{0, L1, 1400 * 1000},
	38	{0, L2, 1300 * 1000},
	39	{0, L3, 1200 * 1000},
	40	{0, L4, 1100 * 1000},
	41	{0, L5, 1000 * 1000},
	42	{0, L6, 900 * 1000},
	43	{0, L7, 800 * 1000},
	44	{0, L8, 700 * 1000},
	45	{0, L9, 600 * 1000},
	46	{0, L10, 500 * 1000},
	47	{0, L11, 400 * 1000},
	48	{0, L12, 300 * 1000},
	49	{0, L13, 200 * 1000},
	50	{0, 0, CPUFREQ_TABLE_END},
a35c5051 JL	51	};
a35c5051 JL	52
9d0554ff	53	static struct apll_freq *apll_freq_4x12;
a35c5051	54
9d0554ff	55	static struct apll_freq apll_freq_4212[] = {
a35c5051	56	/*
9d0554ff JC	57	* values:
	58	* freq
	59	* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
	60	* clock divider for COPY, HPM, RESERVED
	61	* PLL M, P, S
a35c5051	62	*/
9d0554ff JC	63	APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
	64	APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
	65	APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
	66	APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
	67	APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
	68	APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
	69	APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
	70	APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
	71	APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
	72	APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
	73	APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
	74	APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
	75	APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
	76	APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
a35c5051 JL	77	};
a35c5051 JL	78
9d0554ff	79	static struct apll_freq apll_freq_4412[] = {
a35c5051	80	/*
9d0554ff JC	81	* values:
	82	* freq
	83	* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
	84	* clock divider for COPY, HPM, CORES
	85	* PLL M, P, S
a35c5051	86	*/
9d0554ff JC	87	APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
	88	APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
	89	APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
	90	APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
	91	APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
	92	APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
	93	APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
	94	APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
	95	APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
	96	APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
	97	APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
	98	APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
	99	APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
	100	APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
a35c5051 JL	101	};
	102
	103	static void exynos4x12_set_clkdiv(unsigned int div_index)
	104	{
	105	unsigned int tmp;
a35c5051 JL	106
	107	/* Change Divider - CPU0 */
	108
9d0554ff	109	tmp = apll_freq_4x12[div_index].clk_div_cpu0;
a35c5051	110
4c8d8193	111	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
a35c5051	112
4c8d8193 TF	113	while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
4c8d8193 TF	114	& 0x11111111)
a35c5051 JL	115	cpu_relax();
	116
	117	/* Change Divider - CPU1 */
9d0554ff	118	tmp = apll_freq_4x12[div_index].clk_div_cpu1;
a35c5051	119
4c8d8193	120	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
a35c5051	121
be1f7c8d	122	do {
a35c5051	123	cpu_relax();
4c8d8193	124	tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
be1f7c8d	125	} while (tmp != 0x0);
a35c5051 JL	126	}
	127
	128	static void exynos4x12_set_apll(unsigned int index)
	129	{
cf467155	130	unsigned int tmp, freq = apll_freq_4x12[index].freq;
a35c5051	131
cf467155	132	/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
a35c5051 JL	133	clk_set_parent(moutcore, mout_mpll);
	134
	135	do {
	136	cpu_relax();
4c8d8193	137	tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
a35c5051 JL	138	>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
	139	tmp &= 0x7;
	140	} while (tmp != 0x2);
	141
cf467155	142	clk_set_rate(mout_apll, freq * 1000);
a35c5051	143
cf467155	144	/* MUX_CORE_SEL = APLL */
a35c5051 JL	145	clk_set_parent(moutcore, mout_apll);
	146
	147	do {
	148	cpu_relax();
4c8d8193	149	tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
a35c5051 JL	150	tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
	151	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
	152	}
	153
a35c5051 JL	154	static void exynos4x12_set_frequency(unsigned int old_index,
	155	unsigned int new_index)
	156	{
a35c5051	157	if (old_index > new_index) {
cf467155 LM	158	exynos4x12_set_clkdiv(new_index);
cf467155 LM	159	exynos4x12_set_apll(new_index);
a35c5051	160	} else if (old_index < new_index) {
cf467155 LM	161	exynos4x12_set_apll(new_index);
cf467155 LM	162	exynos4x12_set_clkdiv(new_index);
a35c5051 JL	163	}
	164	}
	165
a35c5051 JL	166	int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
a35c5051 JL	167	{
4c8d8193	168	struct device_node *np;
a35c5051 JL	169	unsigned long rate;
a35c5051 JL	170
4c8d8193 TF	171	/*
	172	* HACK: This is a temporary workaround to get access to clock
	173	* controller registers directly and remove static mappings and
	174	* dependencies on platform headers. It is necessary to enable
	175	* Exynos multi-platform support and will be removed together with
	176	* this whole driver as soon as Exynos gets migrated to use
bbcf0719	177	* cpufreq-dt driver.
4c8d8193 TF	178	*/
	179	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
	180	if (!np) {
	181	pr_err("%s: failed to find clock controller DT node\n",
	182	__func__);
	183	return -ENODEV;
	184	}
	185
	186	info->cmu_regs = of_iomap(np, 0);
	187	if (!info->cmu_regs) {
	188	pr_err("%s: failed to map CMU registers\n", __func__);
	189	return -EFAULT;
	190	}
	191
a35c5051 JL	192	cpu_clk = clk_get(NULL, "armclk");
	193	if (IS_ERR(cpu_clk))
	194	return PTR_ERR(cpu_clk);
	195
	196	moutcore = clk_get(NULL, "moutcore");
	197	if (IS_ERR(moutcore))
	198	goto err_moutcore;
	199
	200	mout_mpll = clk_get(NULL, "mout_mpll");
	201	if (IS_ERR(mout_mpll))
	202	goto err_mout_mpll;
	203
	204	rate = clk_get_rate(mout_mpll) / 1000;
	205
	206	mout_apll = clk_get(NULL, "mout_apll");
	207	if (IS_ERR(mout_apll))
	208	goto err_mout_apll;
	209
be1f7c8d	210	if (info->type == EXYNOS_SOC_4212)
9d0554ff JC	211	apll_freq_4x12 = apll_freq_4212;
	212	else
	213	apll_freq_4x12 = apll_freq_4412;
a35c5051 JL	214
a35c5051 JL	215	info->mpll_freq_khz = rate;
9d0554ff	216	/* 800Mhz */
a35c5051	217	info->pll_safe_idx = L7;
a35c5051 JL	218	info->cpu_clk = cpu_clk;
	219	info->volt_table = exynos4x12_volt_table;
	220	info->freq_table = exynos4x12_freq_table;
	221	info->set_freq = exynos4x12_set_frequency;
a35c5051	222
4c8d8193 TF	223	cpufreq = info;
4c8d8193 TF	224
a35c5051 JL	225	return 0;
	226
	227	err_mout_apll:
	228	clk_put(mout_mpll);
	229	err_mout_mpll:
	230	clk_put(moutcore);
	231	err_moutcore:
	232	clk_put(cpu_clk);
	233
	234	pr_debug("%s: failed initialization\n", __func__);
	235	return -EINVAL;
	236	}