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562a6cbe JL |
1 | /* |
2 | * Copyright (c) 2010-20122Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * EXYNOS5250 - CPU frequency scaling support | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/cpufreq.h> | |
19 | ||
20 | #include <mach/map.h> | |
21 | #include <mach/regs-clock.h> | |
c4aaa295 KK |
22 | |
23 | #include "exynos-cpufreq.h" | |
562a6cbe | 24 | |
562a6cbe JL |
25 | static struct clk *cpu_clk; |
26 | static struct clk *moutcore; | |
27 | static struct clk *mout_mpll; | |
28 | static struct clk *mout_apll; | |
29 | ||
9d0554ff JC |
30 | static unsigned int exynos5250_volt_table[] = { |
31 | 1300000, 1250000, 1225000, 1200000, 1150000, | |
32 | 1125000, 1100000, 1075000, 1050000, 1025000, | |
33 | 1012500, 1000000, 975000, 950000, 937500, | |
34 | 925000 | |
562a6cbe JL |
35 | }; |
36 | ||
562a6cbe JL |
37 | static struct cpufreq_frequency_table exynos5250_freq_table[] = { |
38 | {L0, 1700 * 1000}, | |
39 | {L1, 1600 * 1000}, | |
40 | {L2, 1500 * 1000}, | |
41 | {L3, 1400 * 1000}, | |
42 | {L4, 1300 * 1000}, | |
43 | {L5, 1200 * 1000}, | |
44 | {L6, 1100 * 1000}, | |
45 | {L7, 1000 * 1000}, | |
9d0554ff JC |
46 | {L8, 900 * 1000}, |
47 | {L9, 800 * 1000}, | |
562a6cbe JL |
48 | {L10, 700 * 1000}, |
49 | {L11, 600 * 1000}, | |
50 | {L12, 500 * 1000}, | |
51 | {L13, 400 * 1000}, | |
52 | {L14, 300 * 1000}, | |
53 | {L15, 200 * 1000}, | |
54 | {0, CPUFREQ_TABLE_END}, | |
55 | }; | |
56 | ||
9d0554ff | 57 | static struct apll_freq apll_freq_5250[] = { |
562a6cbe | 58 | /* |
9d0554ff JC |
59 | * values: |
60 | * freq | |
61 | * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 | |
62 | * clock divider for COPY, HPM, RESERVED | |
63 | * PLL M, P, S | |
562a6cbe | 64 | */ |
9d0554ff JC |
65 | APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0), |
66 | APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0), | |
67 | APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0), | |
68 | APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0), | |
69 | APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0), | |
70 | APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0), | |
71 | APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0), | |
72 | APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0), | |
73 | APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0), | |
74 | APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0), | |
75 | APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1), | |
76 | APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1), | |
77 | APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1), | |
78 | APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1), | |
79 | APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2), | |
80 | APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2), | |
562a6cbe JL |
81 | }; |
82 | ||
83 | static void set_clkdiv(unsigned int div_index) | |
84 | { | |
85 | unsigned int tmp; | |
86 | ||
87 | /* Change Divider - CPU0 */ | |
88 | ||
9d0554ff | 89 | tmp = apll_freq_5250[div_index].clk_div_cpu0; |
562a6cbe JL |
90 | |
91 | __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0); | |
92 | ||
93 | while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111) | |
94 | cpu_relax(); | |
95 | ||
96 | /* Change Divider - CPU1 */ | |
9d0554ff | 97 | tmp = apll_freq_5250[div_index].clk_div_cpu1; |
562a6cbe JL |
98 | |
99 | __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1); | |
100 | ||
101 | while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11) | |
102 | cpu_relax(); | |
103 | } | |
104 | ||
105 | static void set_apll(unsigned int new_index, | |
106 | unsigned int old_index) | |
107 | { | |
108 | unsigned int tmp, pdiv; | |
109 | ||
110 | /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ | |
111 | clk_set_parent(moutcore, mout_mpll); | |
112 | ||
113 | do { | |
114 | cpu_relax(); | |
115 | tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16); | |
116 | tmp &= 0x7; | |
117 | } while (tmp != 0x2); | |
118 | ||
119 | /* 2. Set APLL Lock time */ | |
9d0554ff | 120 | pdiv = ((apll_freq_5250[new_index].mps >> 8) & 0x3f); |
562a6cbe JL |
121 | |
122 | __raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK); | |
123 | ||
124 | /* 3. Change PLL PMS values */ | |
125 | tmp = __raw_readl(EXYNOS5_APLL_CON0); | |
126 | tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); | |
9d0554ff | 127 | tmp |= apll_freq_5250[new_index].mps; |
562a6cbe JL |
128 | __raw_writel(tmp, EXYNOS5_APLL_CON0); |
129 | ||
130 | /* 4. wait_lock_time */ | |
131 | do { | |
132 | cpu_relax(); | |
133 | tmp = __raw_readl(EXYNOS5_APLL_CON0); | |
134 | } while (!(tmp & (0x1 << 29))); | |
135 | ||
136 | /* 5. MUX_CORE_SEL = APLL */ | |
137 | clk_set_parent(moutcore, mout_apll); | |
138 | ||
139 | do { | |
140 | cpu_relax(); | |
141 | tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU); | |
142 | tmp &= (0x7 << 16); | |
143 | } while (tmp != (0x1 << 16)); | |
144 | ||
145 | } | |
146 | ||
94aa4409 | 147 | static bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index) |
562a6cbe | 148 | { |
9d0554ff JC |
149 | unsigned int old_pm = apll_freq_5250[old_index].mps >> 8; |
150 | unsigned int new_pm = apll_freq_5250[new_index].mps >> 8; | |
562a6cbe JL |
151 | |
152 | return (old_pm == new_pm) ? 0 : 1; | |
153 | } | |
154 | ||
155 | static void exynos5250_set_frequency(unsigned int old_index, | |
156 | unsigned int new_index) | |
157 | { | |
158 | unsigned int tmp; | |
159 | ||
160 | if (old_index > new_index) { | |
161 | if (!exynos5250_pms_change(old_index, new_index)) { | |
162 | /* 1. Change the system clock divider values */ | |
163 | set_clkdiv(new_index); | |
164 | /* 2. Change just s value in apll m,p,s value */ | |
165 | tmp = __raw_readl(EXYNOS5_APLL_CON0); | |
166 | tmp &= ~(0x7 << 0); | |
9d0554ff | 167 | tmp |= apll_freq_5250[new_index].mps & 0x7; |
562a6cbe JL |
168 | __raw_writel(tmp, EXYNOS5_APLL_CON0); |
169 | ||
170 | } else { | |
171 | /* Clock Configuration Procedure */ | |
172 | /* 1. Change the system clock divider values */ | |
173 | set_clkdiv(new_index); | |
174 | /* 2. Change the apll m,p,s value */ | |
175 | set_apll(new_index, old_index); | |
176 | } | |
177 | } else if (old_index < new_index) { | |
178 | if (!exynos5250_pms_change(old_index, new_index)) { | |
179 | /* 1. Change just s value in apll m,p,s value */ | |
180 | tmp = __raw_readl(EXYNOS5_APLL_CON0); | |
181 | tmp &= ~(0x7 << 0); | |
9d0554ff | 182 | tmp |= apll_freq_5250[new_index].mps & 0x7; |
562a6cbe JL |
183 | __raw_writel(tmp, EXYNOS5_APLL_CON0); |
184 | /* 2. Change the system clock divider values */ | |
185 | set_clkdiv(new_index); | |
186 | } else { | |
187 | /* Clock Configuration Procedure */ | |
188 | /* 1. Change the apll m,p,s value */ | |
189 | set_apll(new_index, old_index); | |
190 | /* 2. Change the system clock divider values */ | |
191 | set_clkdiv(new_index); | |
192 | } | |
193 | } | |
194 | } | |
195 | ||
562a6cbe JL |
196 | int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) |
197 | { | |
562a6cbe JL |
198 | unsigned long rate; |
199 | ||
562a6cbe JL |
200 | cpu_clk = clk_get(NULL, "armclk"); |
201 | if (IS_ERR(cpu_clk)) | |
202 | return PTR_ERR(cpu_clk); | |
203 | ||
204 | moutcore = clk_get(NULL, "mout_cpu"); | |
205 | if (IS_ERR(moutcore)) | |
206 | goto err_moutcore; | |
207 | ||
208 | mout_mpll = clk_get(NULL, "mout_mpll"); | |
209 | if (IS_ERR(mout_mpll)) | |
210 | goto err_mout_mpll; | |
211 | ||
212 | rate = clk_get_rate(mout_mpll) / 1000; | |
213 | ||
214 | mout_apll = clk_get(NULL, "mout_apll"); | |
215 | if (IS_ERR(mout_apll)) | |
216 | goto err_mout_apll; | |
217 | ||
562a6cbe | 218 | info->mpll_freq_khz = rate; |
562a6cbe JL |
219 | /* 800Mhz */ |
220 | info->pll_safe_idx = L9; | |
562a6cbe JL |
221 | info->cpu_clk = cpu_clk; |
222 | info->volt_table = exynos5250_volt_table; | |
223 | info->freq_table = exynos5250_freq_table; | |
224 | info->set_freq = exynos5250_set_frequency; | |
225 | info->need_apll_change = exynos5250_pms_change; | |
226 | ||
227 | return 0; | |
228 | ||
229 | err_mout_apll: | |
230 | clk_put(mout_mpll); | |
231 | err_mout_mpll: | |
232 | clk_put(moutcore); | |
233 | err_moutcore: | |
234 | clk_put(cpu_clk); | |
235 | ||
236 | pr_err("%s: failed initialization\n", __func__); | |
237 | return -EINVAL; | |
238 | } |