[deliverable/linux.git] / drivers / cpufreq / gx-suspmod.c

/*
 *	Cyrix MediaGX and NatSemi Geode Suspend Modulation
 *	(C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
 *	(C) 2002 Hiroshi Miura   <miura@da-cha.org>
 *	All Rights Reserved
 *
 *	This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      version 2 as published by the Free Software Foundation
 *
 *      The author(s) of this software shall not be held liable for damages
 *      of any nature resulting due to the use of this software. This
 *      software is provided AS-IS with no warranties.
 *
 * Theoretical note:
 *
 *	(see Geode(tm) CS5530 manual (rev.4.1) page.56)
 *
 *	CPU frequency control on NatSemi Geode GX1/GXLV processor and CS55x0
 *	are based on Suspend Modulation.
 *
 *	Suspend Modulation works by asserting and de-asserting the SUSP# pin
 *	to CPU(GX1/GXLV) for configurable durations. When asserting SUSP#
 *	the CPU enters an idle state. GX1 stops its core clock when SUSP# is
 *	asserted then power consumption is reduced.
 *
 *	Suspend Modulation's OFF/ON duration are configurable
 *	with 'Suspend Modulation OFF Count Register'
 *	and 'Suspend Modulation ON Count Register'.
 *	These registers are 8bit counters that represent the number of
 *	32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF)
 *	to the processor.
 *
 *	These counters define a ratio which is the effective frequency
 *	of operation of the system.
 *
 *			       OFF Count
 *	F_eff = Fgx * ----------------------
 *	                OFF Count + ON Count
 *
 *	0 <= On Count, Off Count <= 255
 *
 *	From these limits, we can get register values
 *
 *	off_duration + on_duration <= MAX_DURATION
 *	on_duration = off_duration * (stock_freq - freq) / freq
 *
 *      off_duration  =  (freq * DURATION) / stock_freq
 *      on_duration = DURATION - off_duration
 *
 *
 *---------------------------------------------------------------------------
 *
 * ChangeLog:
 *	Dec. 12, 2003	Hiroshi Miura <miura@da-cha.org>
 *		- fix on/off register mistake
 *		- fix cpu_khz calc when it stops cpu modulation.
 *
 *	Dec. 11, 2002	Hiroshi Miura <miura@da-cha.org>
 *		- rewrite for Cyrix MediaGX Cx5510/5520 and
 *		  NatSemi Geode Cs5530(A).
 *
 *	Jul. ??, 2002  Zwane Mwaikambo <zwane@commfireservices.com>
 *		- cs5530_mod patch for 2.4.19-rc1.
 *
 *---------------------------------------------------------------------------
 *
 * Todo
 *	Test on machines with 5510, 5530, 5530A
 */

/************************************************************************
 *			Suspend Modulation - Definitions		*
 ************************************************************************/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/cpufreq.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/slab.h>

#include <asm/cpu_device_id.h>
#include <asm/processor-cyrix.h>

/* PCI config registers, all at F0 */
#define PCI_PMER1	0x80	/* power management enable register 1 */
#define PCI_PMER2	0x81	/* power management enable register 2 */
#define PCI_PMER3	0x82	/* power management enable register 3 */
#define PCI_IRQTC	0x8c	/* irq speedup timer counter register:typical 2 to 4ms */
#define PCI_VIDTC	0x8d	/* video speedup timer counter register: typical 50 to 100ms */
#define PCI_MODOFF	0x94	/* suspend modulation OFF counter register, 1 = 32us */
#define PCI_MODON	0x95	/* suspend modulation ON counter register */
#define PCI_SUSCFG	0x96	/* suspend configuration register */

/* PMER1 bits */
#define GPM		(1<<0)	/* global power management */
#define GIT		(1<<1)	/* globally enable PM device idle timers */
#define GTR		(1<<2)	/* globally enable IO traps */
#define IRQ_SPDUP	(1<<3)	/* disable clock throttle during interrupt handling */
#define VID_SPDUP	(1<<4)	/* disable clock throttle during vga video handling */

/* SUSCFG bits */
#define SUSMOD		(1<<0)	/* enable/disable suspend modulation */
/* the below is supported only with cs5530 (after rev.1.2)/cs5530A */
#define SMISPDUP	(1<<1)	/* select how SMI re-enable suspend modulation: */
				/* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */
#define SUSCFG		(1<<2)	/* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */
/* the below is supported only with cs5530A */
#define PWRSVE_ISA	(1<<3)	/* stop ISA clock  */
#define PWRSVE		(1<<4)	/* active idle */

struct gxfreq_params {
	u8 on_duration;
	u8 off_duration;
	u8 pci_suscfg;
	u8 pci_pmer1;
	u8 pci_pmer2;
	struct pci_dev *cs55x0;
};

static struct gxfreq_params *gx_params;
static int stock_freq;

/* PCI bus clock - defaults to 30.000 if cpu_khz is not available */
static int pci_busclk;
module_param(pci_busclk, int, 0444);

/* maximum duration for which the cpu may be suspended
 * (32us * MAX_DURATION). If no parameter is given, this defaults
 * to 255.
 * Note that this leads to a maximum of 8 ms(!) where the CPU clock
 * is suspended -- processing power is just 0.39% of what it used to be,
 * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
static int max_duration = 255;
module_param(max_duration, int, 0444);

/* For the default policy, we want at least some processing power
 * - let's say 5%. (min = maxfreq / POLICY_MIN_DIV)
 */
#define POLICY_MIN_DIV 20


/**
 * we can detect a core multipiler from dir0_lsb
 * from GX1 datasheet p.56,
 *	MULT[3:0]:
 *	0000 = SYSCLK multiplied by 4 (test only)
 *	0001 = SYSCLK multiplied by 10
 *	0010 = SYSCLK multiplied by 4
 *	0011 = SYSCLK multiplied by 6
 *	0100 = SYSCLK multiplied by 9
 *	0101 = SYSCLK multiplied by 5
 *	0110 = SYSCLK multiplied by 7
 *	0111 = SYSCLK multiplied by 8
 *              of 33.3MHz
 **/
static int gx_freq_mult[16] = {
		4, 10, 4, 6, 9, 5, 7, 8,
		0, 0, 0, 0, 0, 0, 0, 0
};


/****************************************************************
 *	Low Level chipset interface				*
 ****************************************************************/
static struct pci_device_id gx_chipset_tbl[] __initdata = {
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY), },
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, gx_chipset_tbl);

static void gx_write_byte(int reg, int value)
{
	pci_write_config_byte(gx_params->cs55x0, reg, value);
}

/**
 * gx_detect_chipset:
 *
 **/
static __init struct pci_dev *gx_detect_chipset(void)
{
	struct pci_dev *gx_pci = NULL;

	/* detect which companion chip is used */
	for_each_pci_dev(gx_pci) {
		if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL)
			return gx_pci;
	}

	pr_debug("error: no supported chipset found!\n");
	return NULL;
}

/**
 * gx_get_cpuspeed:
 *
 * Finds out at which efficient frequency the Cyrix MediaGX/NatSemi
 * Geode CPU runs.
 */
static unsigned int gx_get_cpuspeed(unsigned int cpu)
{
	if ((gx_params->pci_suscfg & SUSMOD) == 0)
		return stock_freq;

	return (stock_freq * gx_params->off_duration)
		/ (gx_params->on_duration + gx_params->off_duration);
}

/**
 *      gx_validate_speed:
 *      determine current cpu speed
 *
 **/

static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration,
		u8 *off_duration)
{
	unsigned int i;
	u8 tmp_on, tmp_off;
	int old_tmp_freq = stock_freq;
	int tmp_freq;

	*off_duration = 1;
	*on_duration = 0;

	for (i = max_duration; i > 0; i--) {
		tmp_off = ((khz * i) / stock_freq) & 0xff;
		tmp_on = i - tmp_off;
		tmp_freq = (stock_freq * tmp_off) / i;
		/* if this relation is closer to khz, use this. If it's equal,
		 * prefer it, too - lower latency */
		if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) {
			*on_duration = tmp_on;
			*off_duration = tmp_off;
			old_tmp_freq = tmp_freq;
		}
	}

	return old_tmp_freq;
}


/**
 * gx_set_cpuspeed:
 * set cpu speed in khz.
 **/

static void gx_set_cpuspeed(unsigned int khz)
{
	u8 suscfg, pmer1;
	unsigned int new_khz;
	unsigned long flags;
	struct cpufreq_freqs freqs;

	freqs.cpu = 0;
	freqs.old = gx_get_cpuspeed(0);

	new_khz = gx_validate_speed(khz, &gx_params->on_duration,
			&gx_params->off_duration);

	freqs.new = new_khz;

	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	local_irq_save(flags);


	if (new_khz != stock_freq) {
		/* if new khz == 100% of CPU speed, it is special case */
		switch (gx_params->cs55x0->device) {
		case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
			pmer1 = gx_params->pci_pmer1 | IRQ_SPDUP | VID_SPDUP;
			/* FIXME: need to test other values -- Zwane,Miura */
			/* typical 2 to 4ms */
			gx_write_byte(PCI_IRQTC, 4);
			/* typical 50 to 100ms */
			gx_write_byte(PCI_VIDTC, 100);
			gx_write_byte(PCI_PMER1, pmer1);

			if (gx_params->cs55x0->revision < 0x10) {
				/* CS5530(rev 1.2, 1.3) */
				suscfg = gx_params->pci_suscfg|SUSMOD;
			} else {
				/* CS5530A,B.. */
				suscfg = gx_params->pci_suscfg|SUSMOD|PWRSVE;
			}
			break;
		case PCI_DEVICE_ID_CYRIX_5520:
		case PCI_DEVICE_ID_CYRIX_5510:
			suscfg = gx_params->pci_suscfg | SUSMOD;
			break;
		default:
			local_irq_restore(flags);
			pr_debug("fatal: try to set unknown chipset.\n");
			return;
		}
	} else {
		suscfg = gx_params->pci_suscfg & ~(SUSMOD);
		gx_params->off_duration = 0;
		gx_params->on_duration = 0;
		pr_debug("suspend modulation disabled: cpu runs 100%% speed.\n");
	}

	gx_write_byte(PCI_MODOFF, gx_params->off_duration);
	gx_write_byte(PCI_MODON, gx_params->on_duration);

	gx_write_byte(PCI_SUSCFG, suscfg);
	pci_read_config_byte(gx_params->cs55x0, PCI_SUSCFG, &suscfg);

	local_irq_restore(flags);

	gx_params->pci_suscfg = suscfg;

	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);

	pr_debug("suspend modulation w/ duration of ON:%d us, OFF:%d us\n",
		gx_params->on_duration * 32, gx_params->off_duration * 32);
	pr_debug("suspend modulation w/ clock speed: %d kHz.\n", freqs.new);
}

/****************************************************************
 *             High level functions                             *
 ****************************************************************/

/*
 *	cpufreq_gx_verify: test if frequency range is valid
 *
 *	This function checks if a given frequency range in kHz is valid
 *      for the hardware supported by the driver.
 */

static int cpufreq_gx_verify(struct cpufreq_policy *policy)
{
	unsigned int tmp_freq = 0;
	u8 tmp1, tmp2;

	if (!stock_freq || !policy)
		return -EINVAL;

	policy->cpu = 0;
	cpufreq_verify_within_limits(policy, (stock_freq / max_duration),
			stock_freq);

	/* it needs to be assured that at least one supported frequency is
	 * within policy->min and policy->max. If it is not, policy->max
	 * needs to be increased until one freuqency is supported.
	 * policy->min may not be decreased, though. This way we guarantee a
	 * specific processing capacity.
	 */
	tmp_freq = gx_validate_speed(policy->min, &tmp1, &tmp2);
	if (tmp_freq < policy->min)
		tmp_freq += stock_freq / max_duration;
	policy->min = tmp_freq;
	if (policy->min > policy->max)
		policy->max = tmp_freq;
	tmp_freq = gx_validate_speed(policy->max, &tmp1, &tmp2);
	if (tmp_freq > policy->max)
		tmp_freq -= stock_freq / max_duration;
	policy->max = tmp_freq;
	if (policy->max < policy->min)
		policy->max = policy->min;
	cpufreq_verify_within_limits(policy, (stock_freq / max_duration),
			stock_freq);

	return 0;
}

/*
 *      cpufreq_gx_target:
 *
 */
static int cpufreq_gx_target(struct cpufreq_policy *policy,
			     unsigned int target_freq,
			     unsigned int relation)
{
	u8 tmp1, tmp2;
	unsigned int tmp_freq;

	if (!stock_freq || !policy)
		return -EINVAL;

	policy->cpu = 0;

	tmp_freq = gx_validate_speed(target_freq, &tmp1, &tmp2);
	while (tmp_freq < policy->min) {
		tmp_freq += stock_freq / max_duration;
		tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2);
	}
	while (tmp_freq > policy->max) {
		tmp_freq -= stock_freq / max_duration;
		tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2);
	}

	gx_set_cpuspeed(tmp_freq);

	return 0;
}

static int cpufreq_gx_cpu_init(struct cpufreq_policy *policy)
{
	unsigned int maxfreq, curfreq;

	if (!policy || policy->cpu != 0)
		return -ENODEV;

	/* determine maximum frequency */
	if (pci_busclk)
		maxfreq = pci_busclk * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f];
	else if (cpu_khz)
		maxfreq = cpu_khz;
	else
		maxfreq = 30000 * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f];

	stock_freq = maxfreq;
	curfreq = gx_get_cpuspeed(0);

	pr_debug("cpu max frequency is %d.\n", maxfreq);
	pr_debug("cpu current frequency is %dkHz.\n", curfreq);

	/* setup basic struct for cpufreq API */
	policy->cpu = 0;

	if (max_duration < POLICY_MIN_DIV)
		policy->min = maxfreq / max_duration;
	else
		policy->min = maxfreq / POLICY_MIN_DIV;
	policy->max = maxfreq;
	policy->cur = curfreq;
	policy->cpuinfo.min_freq = maxfreq / max_duration;
	policy->cpuinfo.max_freq = maxfreq;
	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;

	return 0;
}

/*
 * cpufreq_gx_init:
 *   MediaGX/Geode GX initialize cpufreq driver
 */
static struct cpufreq_driver gx_suspmod_driver = {
	.get		= gx_get_cpuspeed,
	.verify		= cpufreq_gx_verify,
	.target		= cpufreq_gx_target,
	.init		= cpufreq_gx_cpu_init,
	.name		= "gx-suspmod",
	.owner		= THIS_MODULE,
};

static int __init cpufreq_gx_init(void)
{
	int ret;
	struct gxfreq_params *params;
	struct pci_dev *gx_pci;

	/* Test if we have the right hardware */
	gx_pci = gx_detect_chipset();
	if (gx_pci == NULL)
		return -ENODEV;

	/* check whether module parameters are sane */
	if (max_duration > 0xff)
		max_duration = 0xff;

	pr_debug("geode suspend modulation available.\n");

	params = kzalloc(sizeof(struct gxfreq_params), GFP_KERNEL);
	if (params == NULL)
		return -ENOMEM;

	params->cs55x0 = gx_pci;
	gx_params = params;

	/* keep cs55x0 configurations */
	pci_read_config_byte(params->cs55x0, PCI_SUSCFG, &(params->pci_suscfg));
	pci_read_config_byte(params->cs55x0, PCI_PMER1, &(params->pci_pmer1));
	pci_read_config_byte(params->cs55x0, PCI_PMER2, &(params->pci_pmer2));
	pci_read_config_byte(params->cs55x0, PCI_MODON, &(params->on_duration));
	pci_read_config_byte(params->cs55x0, PCI_MODOFF,
			&(params->off_duration));

	ret = cpufreq_register_driver(&gx_suspmod_driver);
	if (ret) {
		kfree(params);
		return ret;                   /* register error! */
	}

	return 0;
}

static void __exit cpufreq_gx_exit(void)
{
	cpufreq_unregister_driver(&gx_suspmod_driver);
	pci_dev_put(gx_params->cs55x0);
	kfree(gx_params);
}

MODULE_AUTHOR("Hiroshi Miura <miura@da-cha.org>");
MODULE_DESCRIPTION("Cpufreq driver for Cyrix MediaGX and NatSemi Geode");
MODULE_LICENSE("GPL");

module_init(cpufreq_gx_init);
module_exit(cpufreq_gx_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Cyrix MediaGX and NatSemi Geode Suspend Modulation
	3	* (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
	4	* (C) 2002 Hiroshi Miura <miura@da-cha.org>
	5	* All Rights Reserved
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
32ee8c3e	9	* version 2 as published by the Free Software Foundation
1da177e4 LT	10	*
	11	* The author(s) of this software shall not be held liable for damages
	12	* of any nature resulting due to the use of this software. This
	13	* software is provided AS-IS with no warranties.
32ee8c3e	14	*
27b46d76	15	* Theoretical note:
1da177e4 LT	16	*
	17	* (see Geode(tm) CS5530 manual (rev.4.1) page.56)
	18	*
	19	* CPU frequency control on NatSemi Geode GX1/GXLV processor and CS55x0
27b46d76	20	* are based on Suspend Modulation.
1da177e4 LT	21	*
	22	* Suspend Modulation works by asserting and de-asserting the SUSP# pin
	23	* to CPU(GX1/GXLV) for configurable durations. When asserting SUSP#
32ee8c3e	24	* the CPU enters an idle state. GX1 stops its core clock when SUSP# is
1da177e4 LT	25	* asserted then power consumption is reduced.
1da177e4 LT	26	*
32ee8c3e	27	* Suspend Modulation's OFF/ON duration are configurable
1da177e4 LT	28	* with 'Suspend Modulation OFF Count Register'
1da177e4 LT	29	* and 'Suspend Modulation ON Count Register'.
32ee8c3e	30	* These registers are 8bit counters that represent the number of
1da177e4 LT	31	* 32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF)
	32	* to the processor.
	33	*
32ee8c3e DJ	34	* These counters define a ratio which is the effective frequency
32ee8c3e DJ	35	* of operation of the system.
1da177e4 LT	36	*
	37	* OFF Count
	38	* F_eff = Fgx * ----------------------
	39	* OFF Count + ON Count
	40	*
	41	* 0 <= On Count, Off Count <= 255
	42	*
32ee8c3e	43	* From these limits, we can get register values
1da177e4 LT	44	*
	45	* off_duration + on_duration <= MAX_DURATION
	46	* on_duration = off_duration * (stock_freq - freq) / freq
	47	*
32ee8c3e DJ	48	* off_duration = (freq * DURATION) / stock_freq
32ee8c3e DJ	49	* on_duration = DURATION - off_duration
1da177e4 LT	50	*
	51	*
	52	*---------------------------------------------------------------------------
	53	*
	54	* ChangeLog:
32ee8c3e DJ	55	* Dec. 12, 2003 Hiroshi Miura <miura@da-cha.org>
	56	* - fix on/off register mistake
	57	* - fix cpu_khz calc when it stops cpu modulation.
1da177e4	58	*
32ee8c3e DJ	59	* Dec. 11, 2002 Hiroshi Miura <miura@da-cha.org>
32ee8c3e DJ	60	* - rewrite for Cyrix MediaGX Cx5510/5520 and
1da177e4 LT	61	* NatSemi Geode Cs5530(A).
	62	*
	63	* Jul. ??, 2002 Zwane Mwaikambo <zwane@commfireservices.com>
	64	* - cs5530_mod patch for 2.4.19-rc1.
	65	*
	66	*---------------------------------------------------------------------------
	67	*
	68	* Todo
	69	* Test on machines with 5510, 5530, 5530A
	70	*/
	71
	72	/************************************************************************
	73	* Suspend Modulation - Definitions *
	74	************************************************************************/
	75
	76	#include <linux/kernel.h>
32ee8c3e	77	#include <linux/module.h>
1da177e4 LT	78	#include <linux/init.h>
	79	#include <linux/smp.h>
	80	#include <linux/cpufreq.h>
	81	#include <linux/pci.h>
00f6a235	82	#include <linux/errno.h>
5a0e3ad6	83	#include <linux/slab.h>
00f6a235	84
fa8031ae	85	#include <asm/cpu_device_id.h>
f25f64ed	86	#include <asm/processor-cyrix.h>
1da177e4 LT	87
1da177e4 LT	88	/* PCI config registers, all at F0 */
32ee8c3e DJ	89	#define PCI_PMER1 0x80 /* power management enable register 1 */
	90	#define PCI_PMER2 0x81 /* power management enable register 2 */
	91	#define PCI_PMER3 0x82 /* power management enable register 3 */
	92	#define PCI_IRQTC 0x8c /* irq speedup timer counter register:typical 2 to 4ms */
	93	#define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
	94	#define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */
	95	#define PCI_MODON 0x95 /* suspend modulation ON counter register */
	96	#define PCI_SUSCFG 0x96 /* suspend configuration register */
1da177e4 LT	97
1da177e4 LT	98	/* PMER1 bits */
32ee8c3e DJ	99	#define GPM (1<<0) /* global power management */
	100	#define GIT (1<<1) /* globally enable PM device idle timers */
	101	#define GTR (1<<2) /* globally enable IO traps */
	102	#define IRQ_SPDUP (1<<3) /* disable clock throttle during interrupt handling */
	103	#define VID_SPDUP (1<<4) /* disable clock throttle during vga video handling */
1da177e4 LT	104
1da177e4 LT	105	/* SUSCFG bits */
32ee8c3e	106	#define SUSMOD (1<<0) /* enable/disable suspend modulation */
27b46d76	107	/* the below is supported only with cs5530 (after rev.1.2)/cs5530A */
32ee8c3e DJ	108	#define SMISPDUP (1<<1) /* select how SMI re-enable suspend modulation: */
	109	/* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */
	110	#define SUSCFG (1<<2) /* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */
27b46d76	111	/* the below is supported only with cs5530A */
32ee8c3e DJ	112	#define PWRSVE_ISA (1<<3) /* stop ISA clock */
32ee8c3e DJ	113	#define PWRSVE (1<<4) /* active idle */
1da177e4 LT	114
	115	struct gxfreq_params {
	116	u8 on_duration;
	117	u8 off_duration;
	118	u8 pci_suscfg;
	119	u8 pci_pmer1;
	120	u8 pci_pmer2;
1da177e4 LT	121	struct pci_dev *cs55x0;
	122	};
	123
	124	static struct gxfreq_params *gx_params;
	125	static int stock_freq;
	126
	127	/* PCI bus clock - defaults to 30.000 if cpu_khz is not available */
00f6a235 DJ	128	static int pci_busclk;
00f6a235 DJ	129	module_param(pci_busclk, int, 0444);
1da177e4 LT	130
	131	/* maximum duration for which the cpu may be suspended
	132	* (32us * MAX_DURATION). If no parameter is given, this defaults
32ee8c3e	133	* to 255.
1da177e4 LT	134	* Note that this leads to a maximum of 8 ms(!) where the CPU clock
	135	* is suspended -- processing power is just 0.39% of what it used to be,
	136	* though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
	137	static int max_duration = 255;
00f6a235	138	module_param(max_duration, int, 0444);
1da177e4 LT	139
	140	/* For the default policy, we want at least some processing power
	141	* - let's say 5%. (min = maxfreq / POLICY_MIN_DIV)
	142	*/
	143	#define POLICY_MIN_DIV 20
	144
	145
1da177e4	146	/**
32ee8c3e DJ	147	* we can detect a core multipiler from dir0_lsb
	148	* from GX1 datasheet p.56,
	149	* MULT[3:0]:
	150	* 0000 = SYSCLK multiplied by 4 (test only)
	151	* 0001 = SYSCLK multiplied by 10
	152	* 0010 = SYSCLK multiplied by 4
	153	* 0011 = SYSCLK multiplied by 6
	154	* 0100 = SYSCLK multiplied by 9
	155	* 0101 = SYSCLK multiplied by 5
	156	* 0110 = SYSCLK multiplied by 7
	157	* 0111 = SYSCLK multiplied by 8
1da177e4 LT	158	* of 33.3MHz
	159	**/
	160	static int gx_freq_mult[16] = {
	161	4, 10, 4, 6, 9, 5, 7, 8,
	162	0, 0, 0, 0, 0, 0, 0, 0
	163	};
	164
	165
	166	/****************************************************************
32ee8c3e	167	* Low Level chipset interface *
1da177e4 LT	168	****************************************************************/
1da177e4 LT	169	static struct pci_device_id gx_chipset_tbl[] __initdata = {
55c789bb PH	170	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY), },
	171	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
	172	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
32ee8c3e	173	{ 0, },
1da177e4	174	};
b3012e12	175	MODULE_DEVICE_TABLE(pci, gx_chipset_tbl);
1da177e4	176
00f6a235 DJ	177	static void gx_write_byte(int reg, int value)
	178	{
	179	pci_write_config_byte(gx_params->cs55x0, reg, value);
	180	}
	181
1da177e4	182	/**
32ee8c3e	183	* gx_detect_chipset:
1da177e4 LT	184	*
	185	**/
	186	static __init struct pci_dev *gx_detect_chipset(void)
	187	{
	188	struct pci_dev *gx_pci = NULL;
	189
1da177e4	190	/* detect which companion chip is used */
ccc5638a	191	for_each_pci_dev(gx_pci) {
32ee8c3e	192	if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL)
1da177e4	193	return gx_pci;
1da177e4 LT	194	}
1da177e4 LT	195
2d06d8c4	196	pr_debug("error: no supported chipset found!\n");
1da177e4 LT	197	return NULL;
	198	}
	199
	200	/**
32ee8c3e	201	* gx_get_cpuspeed:
1da177e4	202	*
00f6a235 DJ	203	* Finds out at which efficient frequency the Cyrix MediaGX/NatSemi
00f6a235 DJ	204	* Geode CPU runs.
1da177e4 LT	205	*/
	206	static unsigned int gx_get_cpuspeed(unsigned int cpu)
	207	{
32ee8c3e	208	if ((gx_params->pci_suscfg & SUSMOD) == 0)
1da177e4 LT	209	return stock_freq;
1da177e4 LT	210
32ee8c3e	211	return (stock_freq * gx_params->off_duration)
1da177e4 LT	212	/ (gx_params->on_duration + gx_params->off_duration);
	213	}
	214
	215	/**
	216	* gx_validate_speed:
	217	* determine current cpu speed
32ee8c3e DJ	218	*
32ee8c3e DJ	219	**/
1da177e4	220
00f6a235 DJ	221	static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration,
00f6a235 DJ	222	u8 *off_duration)
1da177e4 LT	223	{
	224	unsigned int i;
	225	u8 tmp_on, tmp_off;
	226	int old_tmp_freq = stock_freq;
	227	int tmp_freq;
	228
00f6a235 DJ	229	*off_duration = 1;
00f6a235 DJ	230	*on_duration = 0;
1da177e4	231
00f6a235	232	for (i = max_duration; i > 0; i--) {
32ee8c3e	233	tmp_off = ((khz * i) / stock_freq) & 0xff;
1da177e4 LT	234	tmp_on = i - tmp_off;
	235	tmp_freq = (stock_freq * tmp_off) / i;
	236	/* if this relation is closer to khz, use this. If it's equal,
	237	* prefer it, too - lower latency */
	238	if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) {
	239	*on_duration = tmp_on;
	240	*off_duration = tmp_off;
	241	old_tmp_freq = tmp_freq;
	242	}
	243	}
	244
	245	return old_tmp_freq;
	246	}
	247
	248
	249	/**
32ee8c3e DJ	250	* gx_set_cpuspeed:
32ee8c3e DJ	251	* set cpu speed in khz.
1da177e4 LT	252	**/
	253
	254	static void gx_set_cpuspeed(unsigned int khz)
	255	{
32ee8c3e	256	u8 suscfg, pmer1;
1da177e4 LT	257	unsigned int new_khz;
	258	unsigned long flags;
	259	struct cpufreq_freqs freqs;
	260
1da177e4 LT	261	freqs.cpu = 0;
	262	freqs.old = gx_get_cpuspeed(0);
	263
00f6a235 DJ	264	new_khz = gx_validate_speed(khz, &gx_params->on_duration,
00f6a235 DJ	265	&gx_params->off_duration);
1da177e4 LT	266
	267	freqs.new = new_khz;
	268
	269	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	270	local_irq_save(flags);
	271
00f6a235 DJ	272
	273
	274	if (new_khz != stock_freq) {
	275	/* if new khz == 100% of CPU speed, it is special case */
1da177e4 LT	276	switch (gx_params->cs55x0->device) {
	277	case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
	278	pmer1 = gx_params->pci_pmer1 \| IRQ_SPDUP \| VID_SPDUP;
	279	/* FIXME: need to test other values -- Zwane,Miura */
00f6a235 DJ	280	/* typical 2 to 4ms */
	281	gx_write_byte(PCI_IRQTC, 4);
	282	/* typical 50 to 100ms */
	283	gx_write_byte(PCI_VIDTC, 100);
	284	gx_write_byte(PCI_PMER1, pmer1);
	285
	286	if (gx_params->cs55x0->revision < 0x10) {
	287	/* CS5530(rev 1.2, 1.3) */
	288	suscfg = gx_params->pci_suscfg\|SUSMOD;
	289	} else {
	290	/* CS5530A,B.. */
	291	suscfg = gx_params->pci_suscfg\|SUSMOD\|PWRSVE;
1da177e4 LT	292	}
	293	break;
	294	case PCI_DEVICE_ID_CYRIX_5520:
	295	case PCI_DEVICE_ID_CYRIX_5510:
	296	suscfg = gx_params->pci_suscfg \| SUSMOD;
	297	break;
	298	default:
	299	local_irq_restore(flags);
2d06d8c4	300	pr_debug("fatal: try to set unknown chipset.\n");
1da177e4 LT	301	return;
	302	}
	303	} else {
	304	suscfg = gx_params->pci_suscfg & ~(SUSMOD);
	305	gx_params->off_duration = 0;
	306	gx_params->on_duration = 0;
2d06d8c4	307	pr_debug("suspend modulation disabled: cpu runs 100%% speed.\n");
1da177e4 LT	308	}
1da177e4 LT	309
00f6a235 DJ	310	gx_write_byte(PCI_MODOFF, gx_params->off_duration);
00f6a235 DJ	311	gx_write_byte(PCI_MODON, gx_params->on_duration);
1da177e4	312
00f6a235	313	gx_write_byte(PCI_SUSCFG, suscfg);
32ee8c3e	314	pci_read_config_byte(gx_params->cs55x0, PCI_SUSCFG, &suscfg);
1da177e4	315
32ee8c3e	316	local_irq_restore(flags);
1da177e4 LT	317
	318	gx_params->pci_suscfg = suscfg;
	319
	320	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	321
2d06d8c4	322	pr_debug("suspend modulation w/ duration of ON:%d us, OFF:%d us\n",
32ee8c3e	323	gx_params->on_duration * 32, gx_params->off_duration * 32);
2d06d8c4	324	pr_debug("suspend modulation w/ clock speed: %d kHz.\n", freqs.new);
1da177e4 LT	325	}
	326
	327	/****************************************************************
	328	* High level functions *
	329	****************************************************************/
	330
	331	/*
32ee8c3e	332	* cpufreq_gx_verify: test if frequency range is valid
1da177e4	333	*
32ee8c3e DJ	334	* This function checks if a given frequency range in kHz is valid
32ee8c3e DJ	335	* for the hardware supported by the driver.
1da177e4 LT	336	*/
	337
	338	static int cpufreq_gx_verify(struct cpufreq_policy *policy)
	339	{
	340	unsigned int tmp_freq = 0;
	341	u8 tmp1, tmp2;
	342
32ee8c3e DJ	343	if (!stock_freq \|\| !policy)
32ee8c3e DJ	344	return -EINVAL;
1da177e4 LT	345
1da177e4 LT	346	policy->cpu = 0;
00f6a235 DJ	347	cpufreq_verify_within_limits(policy, (stock_freq / max_duration),
00f6a235 DJ	348	stock_freq);
1da177e4 LT	349
	350	/* it needs to be assured that at least one supported frequency is
	351	* within policy->min and policy->max. If it is not, policy->max
	352	* needs to be increased until one freuqency is supported.
32ee8c3e	353	* policy->min may not be decreased, though. This way we guarantee a
1da177e4 LT	354	* specific processing capacity.
	355	*/
	356	tmp_freq = gx_validate_speed(policy->min, &tmp1, &tmp2);
32ee8c3e	357	if (tmp_freq < policy->min)
1da177e4 LT	358	tmp_freq += stock_freq / max_duration;
1da177e4 LT	359	policy->min = tmp_freq;
32ee8c3e	360	if (policy->min > policy->max)
1da177e4 LT	361	policy->max = tmp_freq;
	362	tmp_freq = gx_validate_speed(policy->max, &tmp1, &tmp2);
	363	if (tmp_freq > policy->max)
	364	tmp_freq -= stock_freq / max_duration;
	365	policy->max = tmp_freq;
	366	if (policy->max < policy->min)
	367	policy->max = policy->min;
00f6a235 DJ	368	cpufreq_verify_within_limits(policy, (stock_freq / max_duration),
00f6a235 DJ	369	stock_freq);
32ee8c3e	370
1da177e4 LT	371	return 0;
	372	}
	373
	374	/*
32ee8c3e	375	* cpufreq_gx_target:
1da177e4 LT	376	*
	377	*/
	378	static int cpufreq_gx_target(struct cpufreq_policy *policy,
	379	unsigned int target_freq,
	380	unsigned int relation)
	381	{
	382	u8 tmp1, tmp2;
	383	unsigned int tmp_freq;
	384
32ee8c3e DJ	385	if (!stock_freq \|\| !policy)
32ee8c3e DJ	386	return -EINVAL;
1da177e4 LT	387
	388	policy->cpu = 0;
	389
	390	tmp_freq = gx_validate_speed(target_freq, &tmp1, &tmp2);
	391	while (tmp_freq < policy->min) {
	392	tmp_freq += stock_freq / max_duration;
	393	tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2);
	394	}
	395	while (tmp_freq > policy->max) {
	396	tmp_freq -= stock_freq / max_duration;
	397	tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2);
	398	}
	399
	400	gx_set_cpuspeed(tmp_freq);
	401
	402	return 0;
	403	}
	404
	405	static int cpufreq_gx_cpu_init(struct cpufreq_policy *policy)
	406	{
	407	unsigned int maxfreq, curfreq;
	408
	409	if (!policy \|\| policy->cpu != 0)
	410	return -ENODEV;
	411
	412	/* determine maximum frequency */
00f6a235	413	if (pci_busclk)
1da177e4	414	maxfreq = pci_busclk * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f];
00f6a235	415	else if (cpu_khz)
1da177e4	416	maxfreq = cpu_khz;
00f6a235	417	else
1da177e4	418	maxfreq = 30000 * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f];
00f6a235	419
1da177e4 LT	420	stock_freq = maxfreq;
	421	curfreq = gx_get_cpuspeed(0);
	422
2d06d8c4 DB	423	pr_debug("cpu max frequency is %d.\n", maxfreq);
2d06d8c4 DB	424	pr_debug("cpu current frequency is %dkHz.\n", curfreq);
1da177e4 LT	425
	426	/* setup basic struct for cpufreq API */
	427	policy->cpu = 0;
	428
	429	if (max_duration < POLICY_MIN_DIV)
	430	policy->min = maxfreq / max_duration;
	431	else
	432	policy->min = maxfreq / POLICY_MIN_DIV;
	433	policy->max = maxfreq;
	434	policy->cur = curfreq;
1da177e4 LT	435	policy->cpuinfo.min_freq = maxfreq / max_duration;
	436	policy->cpuinfo.max_freq = maxfreq;
	437	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
	438
	439	return 0;
	440	}
	441
32ee8c3e	442	/*
1da177e4 LT	443	* cpufreq_gx_init:
	444	* MediaGX/Geode GX initialize cpufreq driver
	445	*/
221dee28	446	static struct cpufreq_driver gx_suspmod_driver = {
1da177e4 LT	447	.get = gx_get_cpuspeed,
	448	.verify = cpufreq_gx_verify,
	449	.target = cpufreq_gx_target,
	450	.init = cpufreq_gx_cpu_init,
	451	.name = "gx-suspmod",
	452	.owner = THIS_MODULE,
	453	};
	454
	455	static int __init cpufreq_gx_init(void)
	456	{
	457	int ret;
	458	struct gxfreq_params *params;
	459	struct pci_dev *gx_pci;
1da177e4 LT	460
1da177e4 LT	461	/* Test if we have the right hardware */
00f6a235 DJ	462	gx_pci = gx_detect_chipset();
00f6a235 DJ	463	if (gx_pci == NULL)
1da177e4 LT	464	return -ENODEV;
	465
	466	/* check whether module parameters are sane */
	467	if (max_duration > 0xff)
	468	max_duration = 0xff;
	469
2d06d8c4	470	pr_debug("geode suspend modulation available.\n");
1da177e4	471
84f0b1ef	472	params = kzalloc(sizeof(struct gxfreq_params), GFP_KERNEL);
1da177e4 LT	473	if (params == NULL)
1da177e4 LT	474	return -ENOMEM;
1da177e4 LT	475
	476	params->cs55x0 = gx_pci;
	477	gx_params = params;
	478
	479	/* keep cs55x0 configurations */
	480	pci_read_config_byte(params->cs55x0, PCI_SUSCFG, &(params->pci_suscfg));
	481	pci_read_config_byte(params->cs55x0, PCI_PMER1, &(params->pci_pmer1));
	482	pci_read_config_byte(params->cs55x0, PCI_PMER2, &(params->pci_pmer2));
	483	pci_read_config_byte(params->cs55x0, PCI_MODON, &(params->on_duration));
00f6a235 DJ	484	pci_read_config_byte(params->cs55x0, PCI_MODOFF,
00f6a235 DJ	485	&(params->off_duration));
1da177e4	486
00f6a235 DJ	487	ret = cpufreq_register_driver(&gx_suspmod_driver);
00f6a235 DJ	488	if (ret) {
1da177e4 LT	489	kfree(params);
	490	return ret; /* register error! */
	491	}
	492
	493	return 0;
	494	}
	495
	496	static void __exit cpufreq_gx_exit(void)
	497	{
	498	cpufreq_unregister_driver(&gx_suspmod_driver);
	499	pci_dev_put(gx_params->cs55x0);
	500	kfree(gx_params);
	501	}
	502
00f6a235 DJ	503	MODULE_AUTHOR("Hiroshi Miura <miura@da-cha.org>");
	504	MODULE_DESCRIPTION("Cpufreq driver for Cyrix MediaGX and NatSemi Geode");
	505	MODULE_LICENSE("GPL");
1da177e4 LT	506
	507	module_init(cpufreq_gx_init);
	508	module_exit(cpufreq_gx_exit);
	509