[deliverable/linux.git] / drivers / cpufreq / imx6q-cpufreq.c

/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#define PU_SOC_VOLTAGE_NORMAL	1250000
#define PU_SOC_VOLTAGE_HIGH	1275000
#define FREQ_1P2_GHZ		1200000000

static struct regulator *arm_reg;
static struct regulator *pu_reg;
static struct regulator *soc_reg;

static struct clk *arm_clk;
static struct clk *pll1_sys_clk;
static struct clk *pll1_sw_clk;
static struct clk *step_clk;
static struct clk *pll2_pfd2_396m_clk;

static struct device *cpu_dev;
static struct cpufreq_frequency_table *freq_table;
static unsigned int transition_latency;

static unsigned int imx6q_get_speed(unsigned int cpu)
{
	return clk_get_rate(arm_clk) / 1000;
}

static int imx6q_set_target(struct cpufreq_policy *policy,
			    unsigned int target_freq, unsigned int relation)
{
	struct cpufreq_freqs freqs;
	struct opp *opp;
	unsigned long freq_hz, volt, volt_old;
	unsigned int index;
	int ret;

	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
					     relation, &index);
	if (ret) {
		dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
			target_freq, ret);
		return ret;
	}

	freqs.new = freq_table[index].frequency;
	freq_hz = freqs.new * 1000;
	freqs.old = clk_get_rate(arm_clk) / 1000;

	if (freqs.old == freqs.new)
		return 0;

	rcu_read_lock();
	opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
	if (IS_ERR(opp)) {
		rcu_read_unlock();
		dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
		return PTR_ERR(opp);
	}

	volt = opp_get_voltage(opp);
	rcu_read_unlock();
	volt_old = regulator_get_voltage(arm_reg);

	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
		freqs.old / 1000, volt_old / 1000,
		freqs.new / 1000, volt / 1000);

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);

	/* scaling up?  scale voltage before frequency */
	if (freqs.new > freqs.old) {
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_err(cpu_dev,
				"failed to scale vddarm up: %d\n", ret);
			freqs.new = freqs.old;
			goto post_notify;
		}

		/*
		 * Need to increase vddpu and vddsoc for safety
		 * if we are about to run at 1.2 GHz.
		 */
		if (freqs.new == FREQ_1P2_GHZ / 1000) {
			regulator_set_voltage_tol(pu_reg,
					PU_SOC_VOLTAGE_HIGH, 0);
			regulator_set_voltage_tol(soc_reg,
					PU_SOC_VOLTAGE_HIGH, 0);
		}
	}

	/*
	 * The setpoints are selected per PLL/PDF frequencies, so we need to
	 * reprogram PLL for frequency scaling.  The procedure of reprogramming
	 * PLL1 is as below.
	 *
	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	 *  - Disable pll2_pfd2_396m_clk
	 */
	clk_set_parent(step_clk, pll2_pfd2_396m_clk);
	clk_set_parent(pll1_sw_clk, step_clk);
	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
		clk_set_rate(pll1_sys_clk, freqs.new * 1000);
		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
	}

	/* Ensure the arm clock divider is what we expect */
	ret = clk_set_rate(arm_clk, freqs.new * 1000);
	if (ret) {
		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
		regulator_set_voltage_tol(arm_reg, volt_old, 0);
		freqs.new = freqs.old;
		goto post_notify;
	}

	/* scaling down?  scale voltage after frequency */
	if (freqs.new < freqs.old) {
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_warn(cpu_dev,
				 "failed to scale vddarm down: %d\n", ret);
			ret = 0;
		}

		if (freqs.old == FREQ_1P2_GHZ / 1000) {
			regulator_set_voltage_tol(pu_reg,
					PU_SOC_VOLTAGE_NORMAL, 0);
			regulator_set_voltage_tol(soc_reg,
					PU_SOC_VOLTAGE_NORMAL, 0);
		}
	}

post_notify:
	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);

	return ret;
}

static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
{
	int ret;

	ret = cpufreq_table_validate_and_show(policy, freq_table);
	if (ret) {
		dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
		return ret;
	}

	policy->cpuinfo.transition_latency = transition_latency;
	cpumask_setall(policy->cpus);

	return 0;
}

static struct cpufreq_driver imx6q_cpufreq_driver = {
	.verify = cpufreq_generic_frequency_table_verify,
	.target = imx6q_set_target,
	.get = imx6q_get_speed,
	.init = imx6q_cpufreq_init,
	.exit = cpufreq_generic_exit,
	.name = "imx6q-cpufreq",
	.attr = cpufreq_generic_attr,
};

static int imx6q_cpufreq_probe(struct platform_device *pdev)
{
	struct device_node *np;
	struct opp *opp;
	unsigned long min_volt, max_volt;
	int num, ret;

	cpu_dev = get_cpu_device(0);
	if (!cpu_dev) {
		pr_err("failed to get cpu0 device\n");
		return -ENODEV;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		dev_err(cpu_dev, "failed to find cpu0 node\n");
		return -ENOENT;
	}

	arm_clk = devm_clk_get(cpu_dev, "arm");
	pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
	pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
	step_clk = devm_clk_get(cpu_dev, "step");
	pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
	if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
	    IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
		dev_err(cpu_dev, "failed to get clocks\n");
		ret = -ENOENT;
		goto put_node;
	}

	arm_reg = devm_regulator_get(cpu_dev, "arm");
	pu_reg = devm_regulator_get(cpu_dev, "pu");
	soc_reg = devm_regulator_get(cpu_dev, "soc");
	if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
		dev_err(cpu_dev, "failed to get regulators\n");
		ret = -ENOENT;
		goto put_node;
	}

	/* We expect an OPP table supplied by platform */
	num = opp_get_opp_count(cpu_dev);
	if (num < 0) {
		ret = num;
		dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
		goto put_node;
	}

	ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
		goto put_node;
	}

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	/*
	 * OPP is maintained in order of increasing frequency, and
	 * freq_table initialised from OPP is therefore sorted in the
	 * same order.
	 */
	rcu_read_lock();
	opp = opp_find_freq_exact(cpu_dev,
				  freq_table[0].frequency * 1000, true);
	min_volt = opp_get_voltage(opp);
	opp = opp_find_freq_exact(cpu_dev,
				  freq_table[--num].frequency * 1000, true);
	max_volt = opp_get_voltage(opp);
	rcu_read_unlock();
	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	if (ret > 0)
		transition_latency += ret * 1000;

	/* Count vddpu and vddsoc latency in for 1.2 GHz support */
	if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
		ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
						 PU_SOC_VOLTAGE_HIGH);
		if (ret > 0)
			transition_latency += ret * 1000;
		ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
						 PU_SOC_VOLTAGE_HIGH);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	if (ret) {
		dev_err(cpu_dev, "failed register driver: %d\n", ret);
		goto free_freq_table;
	}

	of_node_put(np);
	return 0;

free_freq_table:
	opp_free_cpufreq_table(cpu_dev, &freq_table);
put_node:
	of_node_put(np);
	return ret;
}

static int imx6q_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
	opp_free_cpufreq_table(cpu_dev, &freq_table);

	return 0;
}

static struct platform_driver imx6q_cpufreq_platdrv = {
	.driver = {
		.name	= "imx6q-cpufreq",
		.owner	= THIS_MODULE,
	},
	.probe		= imx6q_cpufreq_probe,
	.remove		= imx6q_cpufreq_remove,
};
module_platform_driver(imx6q_cpufreq_platdrv);

MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1dd538f0 SG	1	/*
	2	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/clk.h>
b494b48d	10	#include <linux/cpu.h>
1dd538f0 SG	11	#include <linux/cpufreq.h>
	12	#include <linux/delay.h>
	13	#include <linux/err.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/opp.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/regulator/consumer.h>
	19
	20	#define PU_SOC_VOLTAGE_NORMAL 1250000
	21	#define PU_SOC_VOLTAGE_HIGH 1275000
	22	#define FREQ_1P2_GHZ 1200000000
	23
	24	static struct regulator *arm_reg;
	25	static struct regulator *pu_reg;
	26	static struct regulator *soc_reg;
	27
	28	static struct clk *arm_clk;
	29	static struct clk *pll1_sys_clk;
	30	static struct clk *pll1_sw_clk;
	31	static struct clk *step_clk;
	32	static struct clk *pll2_pfd2_396m_clk;
	33
	34	static struct device *cpu_dev;
	35	static struct cpufreq_frequency_table *freq_table;
	36	static unsigned int transition_latency;
	37
1dd538f0 SG	38	static unsigned int imx6q_get_speed(unsigned int cpu)
	39	{
	40	return clk_get_rate(arm_clk) / 1000;
	41	}
	42
	43	static int imx6q_set_target(struct cpufreq_policy *policy,
	44	unsigned int target_freq, unsigned int relation)
	45	{
	46	struct cpufreq_freqs freqs;
	47	struct opp *opp;
	48	unsigned long freq_hz, volt, volt_old;
b43a7ffb	49	unsigned int index;
1dd538f0 SG	50	int ret;
	51
	52	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
	53	relation, &index);
	54	if (ret) {
	55	dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
	56	target_freq, ret);
	57	return ret;
	58	}
	59
	60	freqs.new = freq_table[index].frequency;
	61	freq_hz = freqs.new * 1000;
	62	freqs.old = clk_get_rate(arm_clk) / 1000;
	63
	64	if (freqs.old == freqs.new)
	65	return 0;
	66
1dd538f0 SG	67	rcu_read_lock();
	68	opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
	69	if (IS_ERR(opp)) {
	70	rcu_read_unlock();
	71	dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
	72	return PTR_ERR(opp);
	73	}
	74
	75	volt = opp_get_voltage(opp);
	76	rcu_read_unlock();
	77	volt_old = regulator_get_voltage(arm_reg);
	78
	79	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
	80	freqs.old / 1000, volt_old / 1000,
	81	freqs.new / 1000, volt / 1000);
	82
5a571c35 VK	83	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
5a571c35 VK	84
1dd538f0 SG	85	/* scaling up? scale voltage before frequency */
	86	if (freqs.new > freqs.old) {
	87	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
	88	if (ret) {
	89	dev_err(cpu_dev,
	90	"failed to scale vddarm up: %d\n", ret);
5a571c35 VK	91	freqs.new = freqs.old;
5a571c35 VK	92	goto post_notify;
1dd538f0 SG	93	}
	94
	95	/*
	96	* Need to increase vddpu and vddsoc for safety
	97	* if we are about to run at 1.2 GHz.
	98	*/
	99	if (freqs.new == FREQ_1P2_GHZ / 1000) {
	100	regulator_set_voltage_tol(pu_reg,
	101	PU_SOC_VOLTAGE_HIGH, 0);
	102	regulator_set_voltage_tol(soc_reg,
	103	PU_SOC_VOLTAGE_HIGH, 0);
	104	}
	105	}
	106
	107	/*
	108	* The setpoints are selected per PLL/PDF frequencies, so we need to
	109	* reprogram PLL for frequency scaling. The procedure of reprogramming
	110	* PLL1 is as below.
	111	*
	112	* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	113	* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	114	* - Disable pll2_pfd2_396m_clk
	115	*/
1dd538f0 SG	116	clk_set_parent(step_clk, pll2_pfd2_396m_clk);
	117	clk_set_parent(pll1_sw_clk, step_clk);
	118	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
	119	clk_set_rate(pll1_sys_clk, freqs.new * 1000);
1dd538f0	120	clk_set_parent(pll1_sw_clk, pll1_sys_clk);
1dd538f0 SG	121	}
	122
	123	/* Ensure the arm clock divider is what we expect */
	124	ret = clk_set_rate(arm_clk, freqs.new * 1000);
	125	if (ret) {
	126	dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
	127	regulator_set_voltage_tol(arm_reg, volt_old, 0);
5a571c35 VK	128	freqs.new = freqs.old;
5a571c35 VK	129	goto post_notify;
1dd538f0 SG	130	}
	131
	132	/* scaling down? scale voltage after frequency */
	133	if (freqs.new < freqs.old) {
	134	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
5a571c35	135	if (ret) {
1dd538f0 SG	136	dev_warn(cpu_dev,
1dd538f0 SG	137	"failed to scale vddarm down: %d\n", ret);
5a571c35 VK	138	ret = 0;
5a571c35 VK	139	}
1dd538f0 SG	140
	141	if (freqs.old == FREQ_1P2_GHZ / 1000) {
	142	regulator_set_voltage_tol(pu_reg,
	143	PU_SOC_VOLTAGE_NORMAL, 0);
	144	regulator_set_voltage_tol(soc_reg,
	145	PU_SOC_VOLTAGE_NORMAL, 0);
	146	}
	147	}
	148
5a571c35	149	post_notify:
b43a7ffb	150	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
1dd538f0	151
5a571c35	152	return ret;
1dd538f0 SG	153	}
	154
	155	static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
	156	{
	157	int ret;
	158
9ff4a80b	159	ret = cpufreq_table_validate_and_show(policy, freq_table);
1dd538f0 SG	160	if (ret) {
	161	dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
	162	return ret;
	163	}
	164
	165	policy->cpuinfo.transition_latency = transition_latency;
1dd538f0	166	cpumask_setall(policy->cpus);
1dd538f0 SG	167
	168	return 0;
	169	}
	170
1dd538f0	171	static struct cpufreq_driver imx6q_cpufreq_driver = {
4f6ba385	172	.verify = cpufreq_generic_frequency_table_verify,
1dd538f0 SG	173	.target = imx6q_set_target,
	174	.get = imx6q_get_speed,
	175	.init = imx6q_cpufreq_init,
4f6ba385	176	.exit = cpufreq_generic_exit,
1dd538f0	177	.name = "imx6q-cpufreq",
4f6ba385	178	.attr = cpufreq_generic_attr,
1dd538f0 SG	179	};
	180
	181	static int imx6q_cpufreq_probe(struct platform_device *pdev)
	182	{
	183	struct device_node *np;
	184	struct opp *opp;
	185	unsigned long min_volt, max_volt;
	186	int num, ret;
	187
b494b48d SK	188	cpu_dev = get_cpu_device(0);
	189	if (!cpu_dev) {
	190	pr_err("failed to get cpu0 device\n");
	191	return -ENODEV;
	192	}
1dd538f0	193
cdc58d60	194	np = of_node_get(cpu_dev->of_node);
1dd538f0 SG	195	if (!np) {
	196	dev_err(cpu_dev, "failed to find cpu0 node\n");
	197	return -ENOENT;
	198	}
	199
1dd538f0 SG	200	arm_clk = devm_clk_get(cpu_dev, "arm");
	201	pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
	202	pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
	203	step_clk = devm_clk_get(cpu_dev, "step");
	204	pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
	205	if (IS_ERR(arm_clk) \|\| IS_ERR(pll1_sys_clk) \|\| IS_ERR(pll1_sw_clk) \|\|
	206	IS_ERR(step_clk) \|\| IS_ERR(pll2_pfd2_396m_clk)) {
	207	dev_err(cpu_dev, "failed to get clocks\n");
	208	ret = -ENOENT;
	209	goto put_node;
	210	}
	211
	212	arm_reg = devm_regulator_get(cpu_dev, "arm");
	213	pu_reg = devm_regulator_get(cpu_dev, "pu");
	214	soc_reg = devm_regulator_get(cpu_dev, "soc");
3a3656d4	215	if (IS_ERR(arm_reg) \|\| IS_ERR(pu_reg) \|\| IS_ERR(soc_reg)) {
1dd538f0 SG	216	dev_err(cpu_dev, "failed to get regulators\n");
	217	ret = -ENOENT;
	218	goto put_node;
	219	}
	220
	221	/* We expect an OPP table supplied by platform */
	222	num = opp_get_opp_count(cpu_dev);
	223	if (num < 0) {
	224	ret = num;
	225	dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
	226	goto put_node;
	227	}
	228
	229	ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
	230	if (ret) {
	231	dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
	232	goto put_node;
	233	}
	234
	235	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	236	transition_latency = CPUFREQ_ETERNAL;
	237
	238	/*
	239	* OPP is maintained in order of increasing frequency, and
	240	* freq_table initialised from OPP is therefore sorted in the
	241	* same order.
	242	*/
	243	rcu_read_lock();
	244	opp = opp_find_freq_exact(cpu_dev,
	245	freq_table[0].frequency * 1000, true);
	246	min_volt = opp_get_voltage(opp);
	247	opp = opp_find_freq_exact(cpu_dev,
	248	freq_table[--num].frequency * 1000, true);
	249	max_volt = opp_get_voltage(opp);
	250	rcu_read_unlock();
	251	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	252	if (ret > 0)
	253	transition_latency += ret * 1000;
	254
	255	/* Count vddpu and vddsoc latency in for 1.2 GHz support */
	256	if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
	257	ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
	258	PU_SOC_VOLTAGE_HIGH);
	259	if (ret > 0)
	260	transition_latency += ret * 1000;
	261	ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
	262	PU_SOC_VOLTAGE_HIGH);
	263	if (ret > 0)
	264	transition_latency += ret * 1000;
	265	}
	266
	267	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	268	if (ret) {
	269	dev_err(cpu_dev, "failed register driver: %d\n", ret);
	270	goto free_freq_table;
	271	}
	272
	273	of_node_put(np);
	274	return 0;
	275
	276	free_freq_table:
	277	opp_free_cpufreq_table(cpu_dev, &freq_table);
	278	put_node:
	279	of_node_put(np);
280	return ret;
281	}
282
283	static int imx6q_cpufreq_remove(struct platform_device *pdev)
284	{
285	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
286	opp_free_cpufreq_table(cpu_dev, &freq_table);
287
288	return 0;
289	}
290
291	static struct platform_driver imx6q_cpufreq_platdrv = {
292	.driver = {
293	.name = "imx6q-cpufreq",
294	.owner = THIS_MODULE,
295	},
296	.probe = imx6q_cpufreq_probe,
297	.remove = imx6q_cpufreq_remove,
298	};
299	module_platform_driver(imx6q_cpufreq_platdrv);
300
301	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
302	MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
303	MODULE_LICENSE("GPL");