intel_pstate: Set turbo VID for BayTrail
[deliverable/linux.git] / drivers / cpufreq / intel_pstate.c
CommitLineData
93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13#include <linux/kernel.h>
14#include <linux/kernel_stat.h>
15#include <linux/module.h>
16#include <linux/ktime.h>
17#include <linux/hrtimer.h>
18#include <linux/tick.h>
19#include <linux/slab.h>
20#include <linux/sched.h>
21#include <linux/list.h>
22#include <linux/cpu.h>
23#include <linux/cpufreq.h>
24#include <linux/sysfs.h>
25#include <linux/types.h>
26#include <linux/fs.h>
27#include <linux/debugfs.h>
fbbcdc07 28#include <linux/acpi.h>
93f0822d
DB
29#include <trace/events/power.h>
30
31#include <asm/div64.h>
32#include <asm/msr.h>
33#include <asm/cpu_device_id.h>
34
35#define SAMPLE_COUNT 3
36
61d8d2ab
DB
37#define BYT_RATIOS 0x66a
38#define BYT_VIDS 0x66b
39#define BYT_TURBO_RATIOS 0x66c
21855ff5 40#define BYT_TURBO_VIDS 0x66d
61d8d2ab 41
19e77c28 42
e66c1768 43#define FRAC_BITS 6
93f0822d
DB
44#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
45#define fp_toint(X) ((X) >> FRAC_BITS)
e66c1768 46#define FP_ROUNDUP(X) ((X) += 1 << FRAC_BITS)
93f0822d
DB
47
48static inline int32_t mul_fp(int32_t x, int32_t y)
49{
50 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
51}
52
53static inline int32_t div_fp(int32_t x, int32_t y)
54{
55 return div_s64((int64_t)x << FRAC_BITS, (int64_t)y);
56}
57
58struct sample {
d253d2a5 59 int32_t core_pct_busy;
93f0822d
DB
60 u64 aperf;
61 u64 mperf;
fcb6a15c 62 unsigned long long tsc;
93f0822d
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63 int freq;
64};
65
66struct pstate_data {
67 int current_pstate;
68 int min_pstate;
69 int max_pstate;
70 int turbo_pstate;
71};
72
007bea09 73struct vid_data {
21855ff5
DB
74 int min;
75 int max;
76 int turbo;
007bea09
DB
77 int32_t ratio;
78};
79
93f0822d
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80struct _pid {
81 int setpoint;
82 int32_t integral;
83 int32_t p_gain;
84 int32_t i_gain;
85 int32_t d_gain;
86 int deadband;
d253d2a5 87 int32_t last_err;
93f0822d
DB
88};
89
90struct cpudata {
91 int cpu;
92
93 char name[64];
94
95 struct timer_list timer;
96
93f0822d 97 struct pstate_data pstate;
007bea09 98 struct vid_data vid;
93f0822d 99 struct _pid pid;
93f0822d 100
93f0822d
DB
101 u64 prev_aperf;
102 u64 prev_mperf;
fcb6a15c 103 unsigned long long prev_tsc;
d37e2b76 104 struct sample sample;
93f0822d
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105};
106
107static struct cpudata **all_cpu_data;
108struct pstate_adjust_policy {
109 int sample_rate_ms;
110 int deadband;
111 int setpoint;
112 int p_gain_pct;
113 int d_gain_pct;
114 int i_gain_pct;
115};
116
016c8150
DB
117struct pstate_funcs {
118 int (*get_max)(void);
119 int (*get_min)(void);
120 int (*get_turbo)(void);
007bea09
DB
121 void (*set)(struct cpudata*, int pstate);
122 void (*get_vid)(struct cpudata *);
93f0822d
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123};
124
016c8150
DB
125struct cpu_defaults {
126 struct pstate_adjust_policy pid_policy;
127 struct pstate_funcs funcs;
93f0822d
DB
128};
129
016c8150
DB
130static struct pstate_adjust_policy pid_params;
131static struct pstate_funcs pstate_funcs;
132
93f0822d
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133struct perf_limits {
134 int no_turbo;
135 int max_perf_pct;
136 int min_perf_pct;
137 int32_t max_perf;
138 int32_t min_perf;
d8f469e9
DB
139 int max_policy_pct;
140 int max_sysfs_pct;
93f0822d
DB
141};
142
143static struct perf_limits limits = {
144 .no_turbo = 0,
145 .max_perf_pct = 100,
146 .max_perf = int_tofp(1),
147 .min_perf_pct = 0,
148 .min_perf = 0,
d8f469e9
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149 .max_policy_pct = 100,
150 .max_sysfs_pct = 100,
93f0822d
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151};
152
153static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
154 int deadband, int integral) {
155 pid->setpoint = setpoint;
156 pid->deadband = deadband;
157 pid->integral = int_tofp(integral);
d98d099b 158 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
93f0822d
DB
159}
160
161static inline void pid_p_gain_set(struct _pid *pid, int percent)
162{
163 pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));
164}
165
166static inline void pid_i_gain_set(struct _pid *pid, int percent)
167{
168 pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));
169}
170
171static inline void pid_d_gain_set(struct _pid *pid, int percent)
172{
173
174 pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
175}
176
d253d2a5 177static signed int pid_calc(struct _pid *pid, int32_t busy)
93f0822d 178{
d253d2a5 179 signed int result;
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180 int32_t pterm, dterm, fp_error;
181 int32_t integral_limit;
182
d253d2a5 183 fp_error = int_tofp(pid->setpoint) - busy;
93f0822d 184
d253d2a5 185 if (abs(fp_error) <= int_tofp(pid->deadband))
93f0822d
DB
186 return 0;
187
188 pterm = mul_fp(pid->p_gain, fp_error);
189
190 pid->integral += fp_error;
191
192 /* limit the integral term */
193 integral_limit = int_tofp(30);
194 if (pid->integral > integral_limit)
195 pid->integral = integral_limit;
196 if (pid->integral < -integral_limit)
197 pid->integral = -integral_limit;
198
d253d2a5
BS
199 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
200 pid->last_err = fp_error;
93f0822d
DB
201
202 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
203
204 return (signed int)fp_toint(result);
205}
206
207static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
208{
016c8150
DB
209 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
210 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
211 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
93f0822d
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212
213 pid_reset(&cpu->pid,
016c8150 214 pid_params.setpoint,
93f0822d 215 100,
016c8150 216 pid_params.deadband,
93f0822d
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217 0);
218}
219
93f0822d
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220static inline void intel_pstate_reset_all_pid(void)
221{
222 unsigned int cpu;
223 for_each_online_cpu(cpu) {
224 if (all_cpu_data[cpu])
225 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
226 }
227}
228
229/************************** debugfs begin ************************/
230static int pid_param_set(void *data, u64 val)
231{
232 *(u32 *)data = val;
233 intel_pstate_reset_all_pid();
234 return 0;
235}
236static int pid_param_get(void *data, u64 *val)
237{
238 *val = *(u32 *)data;
239 return 0;
240}
241DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get,
242 pid_param_set, "%llu\n");
243
244struct pid_param {
245 char *name;
246 void *value;
247};
248
249static struct pid_param pid_files[] = {
016c8150
DB
250 {"sample_rate_ms", &pid_params.sample_rate_ms},
251 {"d_gain_pct", &pid_params.d_gain_pct},
252 {"i_gain_pct", &pid_params.i_gain_pct},
253 {"deadband", &pid_params.deadband},
254 {"setpoint", &pid_params.setpoint},
255 {"p_gain_pct", &pid_params.p_gain_pct},
93f0822d
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256 {NULL, NULL}
257};
258
259static struct dentry *debugfs_parent;
260static void intel_pstate_debug_expose_params(void)
261{
262 int i = 0;
263
264 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
265 if (IS_ERR_OR_NULL(debugfs_parent))
266 return;
267 while (pid_files[i].name) {
268 debugfs_create_file(pid_files[i].name, 0660,
269 debugfs_parent, pid_files[i].value,
270 &fops_pid_param);
271 i++;
272 }
273}
274
275/************************** debugfs end ************************/
276
277/************************** sysfs begin ************************/
278#define show_one(file_name, object) \
279 static ssize_t show_##file_name \
280 (struct kobject *kobj, struct attribute *attr, char *buf) \
281 { \
282 return sprintf(buf, "%u\n", limits.object); \
283 }
284
285static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
286 const char *buf, size_t count)
287{
288 unsigned int input;
289 int ret;
290 ret = sscanf(buf, "%u", &input);
291 if (ret != 1)
292 return -EINVAL;
293 limits.no_turbo = clamp_t(int, input, 0 , 1);
294
295 return count;
296}
297
298static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
299 const char *buf, size_t count)
300{
301 unsigned int input;
302 int ret;
303 ret = sscanf(buf, "%u", &input);
304 if (ret != 1)
305 return -EINVAL;
306
d8f469e9
DB
307 limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);
308 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
93f0822d
DB
309 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
310 return count;
311}
312
313static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
314 const char *buf, size_t count)
315{
316 unsigned int input;
317 int ret;
318 ret = sscanf(buf, "%u", &input);
319 if (ret != 1)
320 return -EINVAL;
321 limits.min_perf_pct = clamp_t(int, input, 0 , 100);
322 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
323
324 return count;
325}
326
327show_one(no_turbo, no_turbo);
328show_one(max_perf_pct, max_perf_pct);
329show_one(min_perf_pct, min_perf_pct);
330
331define_one_global_rw(no_turbo);
332define_one_global_rw(max_perf_pct);
333define_one_global_rw(min_perf_pct);
334
335static struct attribute *intel_pstate_attributes[] = {
336 &no_turbo.attr,
337 &max_perf_pct.attr,
338 &min_perf_pct.attr,
339 NULL
340};
341
342static struct attribute_group intel_pstate_attr_group = {
343 .attrs = intel_pstate_attributes,
344};
345static struct kobject *intel_pstate_kobject;
346
347static void intel_pstate_sysfs_expose_params(void)
348{
349 int rc;
350
351 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
352 &cpu_subsys.dev_root->kobj);
353 BUG_ON(!intel_pstate_kobject);
354 rc = sysfs_create_group(intel_pstate_kobject,
355 &intel_pstate_attr_group);
356 BUG_ON(rc);
357}
358
359/************************** sysfs end ************************/
19e77c28
DB
360static int byt_get_min_pstate(void)
361{
362 u64 value;
363 rdmsrl(BYT_RATIOS, value);
21855ff5 364 return (value >> 8) & 0x3F;
19e77c28
DB
365}
366
367static int byt_get_max_pstate(void)
368{
369 u64 value;
370 rdmsrl(BYT_RATIOS, value);
21855ff5 371 return (value >> 16) & 0x3F;
19e77c28 372}
93f0822d 373
61d8d2ab
DB
374static int byt_get_turbo_pstate(void)
375{
376 u64 value;
377 rdmsrl(BYT_TURBO_RATIOS, value);
378 return value & 0x3F;
379}
380
007bea09
DB
381static void byt_set_pstate(struct cpudata *cpudata, int pstate)
382{
383 u64 val;
384 int32_t vid_fp;
385 u32 vid;
386
387 val = pstate << 8;
388 if (limits.no_turbo)
389 val |= (u64)1 << 32;
390
391 vid_fp = cpudata->vid.min + mul_fp(
392 int_tofp(pstate - cpudata->pstate.min_pstate),
393 cpudata->vid.ratio);
394
395 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
396 vid = fp_toint(vid_fp);
397
21855ff5
DB
398 if (pstate > cpudata->pstate.max_pstate)
399 vid = cpudata->vid.turbo;
400
007bea09
DB
401 val |= vid;
402
403 wrmsrl(MSR_IA32_PERF_CTL, val);
404}
405
406static void byt_get_vid(struct cpudata *cpudata)
407{
408 u64 value;
409
21855ff5 410
007bea09 411 rdmsrl(BYT_VIDS, value);
21855ff5
DB
412 cpudata->vid.min = int_tofp((value >> 8) & 0x3f);
413 cpudata->vid.max = int_tofp((value >> 16) & 0x3f);
007bea09
DB
414 cpudata->vid.ratio = div_fp(
415 cpudata->vid.max - cpudata->vid.min,
416 int_tofp(cpudata->pstate.max_pstate -
417 cpudata->pstate.min_pstate));
21855ff5
DB
418
419 rdmsrl(BYT_TURBO_VIDS, value);
420 cpudata->vid.turbo = value & 0x7f;
007bea09
DB
421}
422
423
016c8150 424static int core_get_min_pstate(void)
93f0822d
DB
425{
426 u64 value;
05e99c8c 427 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB
428 return (value >> 40) & 0xFF;
429}
430
016c8150 431static int core_get_max_pstate(void)
93f0822d
DB
432{
433 u64 value;
05e99c8c 434 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB
435 return (value >> 8) & 0xFF;
436}
437
016c8150 438static int core_get_turbo_pstate(void)
93f0822d
DB
439{
440 u64 value;
441 int nont, ret;
05e99c8c 442 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
016c8150 443 nont = core_get_max_pstate();
93f0822d
DB
444 ret = ((value) & 255);
445 if (ret <= nont)
446 ret = nont;
447 return ret;
448}
449
007bea09 450static void core_set_pstate(struct cpudata *cpudata, int pstate)
016c8150
DB
451{
452 u64 val;
453
454 val = pstate << 8;
455 if (limits.no_turbo)
456 val |= (u64)1 << 32;
457
bb18008f 458 wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
016c8150
DB
459}
460
461static struct cpu_defaults core_params = {
462 .pid_policy = {
463 .sample_rate_ms = 10,
464 .deadband = 0,
465 .setpoint = 97,
466 .p_gain_pct = 20,
467 .d_gain_pct = 0,
468 .i_gain_pct = 0,
469 },
470 .funcs = {
471 .get_max = core_get_max_pstate,
472 .get_min = core_get_min_pstate,
473 .get_turbo = core_get_turbo_pstate,
474 .set = core_set_pstate,
475 },
476};
477
19e77c28
DB
478static struct cpu_defaults byt_params = {
479 .pid_policy = {
480 .sample_rate_ms = 10,
481 .deadband = 0,
482 .setpoint = 97,
483 .p_gain_pct = 14,
484 .d_gain_pct = 0,
485 .i_gain_pct = 4,
486 },
487 .funcs = {
488 .get_max = byt_get_max_pstate,
489 .get_min = byt_get_min_pstate,
61d8d2ab 490 .get_turbo = byt_get_turbo_pstate,
007bea09
DB
491 .set = byt_set_pstate,
492 .get_vid = byt_get_vid,
19e77c28
DB
493 },
494};
495
496
93f0822d
DB
497static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
498{
499 int max_perf = cpu->pstate.turbo_pstate;
7244cb62 500 int max_perf_adj;
93f0822d
DB
501 int min_perf;
502 if (limits.no_turbo)
503 max_perf = cpu->pstate.max_pstate;
504
7244cb62
DB
505 max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
506 *max = clamp_t(int, max_perf_adj,
93f0822d
DB
507 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
508
509 min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
510 *min = clamp_t(int, min_perf,
511 cpu->pstate.min_pstate, max_perf);
512}
513
514static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
515{
516 int max_perf, min_perf;
517
518 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
519
520 pstate = clamp_t(int, pstate, min_perf, max_perf);
521
522 if (pstate == cpu->pstate.current_pstate)
523 return;
524
93f0822d 525 trace_cpu_frequency(pstate * 100000, cpu->cpu);
35363e94 526
93f0822d 527 cpu->pstate.current_pstate = pstate;
93f0822d 528
007bea09 529 pstate_funcs.set(cpu, pstate);
93f0822d
DB
530}
531
532static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps)
533{
534 int target;
535 target = cpu->pstate.current_pstate + steps;
536
537 intel_pstate_set_pstate(cpu, target);
538}
539
540static inline void intel_pstate_pstate_decrease(struct cpudata *cpu, int steps)
541{
542 int target;
543 target = cpu->pstate.current_pstate - steps;
544 intel_pstate_set_pstate(cpu, target);
545}
546
547static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
548{
549 sprintf(cpu->name, "Intel 2nd generation core");
550
016c8150
DB
551 cpu->pstate.min_pstate = pstate_funcs.get_min();
552 cpu->pstate.max_pstate = pstate_funcs.get_max();
553 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
93f0822d 554
007bea09
DB
555 if (pstate_funcs.get_vid)
556 pstate_funcs.get_vid(cpu);
557
93f0822d
DB
558 /*
559 * goto max pstate so we don't slow up boot if we are built-in if we are
560 * a module we will take care of it during normal operation
561 */
562 intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate);
563}
564
565static inline void intel_pstate_calc_busy(struct cpudata *cpu,
566 struct sample *sample)
567{
e66c1768
DB
568 int32_t core_pct;
569 int32_t c0_pct;
93f0822d 570
e66c1768
DB
571 core_pct = div_fp(int_tofp((sample->aperf)),
572 int_tofp((sample->mperf)));
573 core_pct = mul_fp(core_pct, int_tofp(100));
574 FP_ROUNDUP(core_pct);
575
576 c0_pct = div_fp(int_tofp(sample->mperf), int_tofp(sample->tsc));
fcb6a15c 577
fcb6a15c 578 sample->freq = fp_toint(
e66c1768 579 mul_fp(int_tofp(cpu->pstate.max_pstate * 1000), core_pct));
fcb6a15c 580
e66c1768 581 sample->core_pct_busy = mul_fp(core_pct, c0_pct);
93f0822d
DB
582}
583
584static inline void intel_pstate_sample(struct cpudata *cpu)
585{
93f0822d 586 u64 aperf, mperf;
fcb6a15c 587 unsigned long long tsc;
93f0822d 588
93f0822d
DB
589 rdmsrl(MSR_IA32_APERF, aperf);
590 rdmsrl(MSR_IA32_MPERF, mperf);
fcb6a15c 591 tsc = native_read_tsc();
b69880f9 592
e66c1768
DB
593 aperf = aperf >> FRAC_BITS;
594 mperf = mperf >> FRAC_BITS;
595 tsc = tsc >> FRAC_BITS;
596
d37e2b76
DB
597 cpu->sample.aperf = aperf;
598 cpu->sample.mperf = mperf;
599 cpu->sample.tsc = tsc;
600 cpu->sample.aperf -= cpu->prev_aperf;
601 cpu->sample.mperf -= cpu->prev_mperf;
602 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 603
d37e2b76 604 intel_pstate_calc_busy(cpu, &cpu->sample);
93f0822d 605
93f0822d
DB
606 cpu->prev_aperf = aperf;
607 cpu->prev_mperf = mperf;
fcb6a15c 608 cpu->prev_tsc = tsc;
93f0822d
DB
609}
610
611static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
612{
613 int sample_time, delay;
614
016c8150 615 sample_time = pid_params.sample_rate_ms;
93f0822d 616 delay = msecs_to_jiffies(sample_time);
93f0822d
DB
617 mod_timer_pinned(&cpu->timer, jiffies + delay);
618}
619
d253d2a5 620static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
93f0822d 621{
2134ed4d 622 int32_t core_busy, max_pstate, current_pstate;
93f0822d 623
d37e2b76 624 core_busy = cpu->sample.core_pct_busy;
2134ed4d 625 max_pstate = int_tofp(cpu->pstate.max_pstate);
93f0822d 626 current_pstate = int_tofp(cpu->pstate.current_pstate);
e66c1768
DB
627 core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
628 return FP_ROUNDUP(core_busy);
93f0822d
DB
629}
630
631static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
632{
d253d2a5 633 int32_t busy_scaled;
93f0822d
DB
634 struct _pid *pid;
635 signed int ctl = 0;
636 int steps;
637
638 pid = &cpu->pid;
639 busy_scaled = intel_pstate_get_scaled_busy(cpu);
640
641 ctl = pid_calc(pid, busy_scaled);
642
643 steps = abs(ctl);
b69880f9 644
93f0822d
DB
645 if (ctl < 0)
646 intel_pstate_pstate_increase(cpu, steps);
647 else
648 intel_pstate_pstate_decrease(cpu, steps);
649}
650
93f0822d
DB
651static void intel_pstate_timer_func(unsigned long __data)
652{
653 struct cpudata *cpu = (struct cpudata *) __data;
b69880f9 654 struct sample *sample;
93f0822d
DB
655
656 intel_pstate_sample(cpu);
b69880f9 657
d37e2b76 658 sample = &cpu->sample;
b69880f9 659
ca182aee 660 intel_pstate_adjust_busy_pstate(cpu);
b69880f9
DB
661
662 trace_pstate_sample(fp_toint(sample->core_pct_busy),
663 fp_toint(intel_pstate_get_scaled_busy(cpu)),
664 cpu->pstate.current_pstate,
665 sample->mperf,
666 sample->aperf,
b69880f9
DB
667 sample->freq);
668
93f0822d
DB
669 intel_pstate_set_sample_time(cpu);
670}
671
672#define ICPU(model, policy) \
6cbd7ee1
DB
673 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
674 (unsigned long)&policy }
93f0822d
DB
675
676static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
016c8150
DB
677 ICPU(0x2a, core_params),
678 ICPU(0x2d, core_params),
19e77c28 679 ICPU(0x37, byt_params),
016c8150
DB
680 ICPU(0x3a, core_params),
681 ICPU(0x3c, core_params),
682 ICPU(0x3e, core_params),
683 ICPU(0x3f, core_params),
684 ICPU(0x45, core_params),
685 ICPU(0x46, core_params),
93f0822d
DB
686 {}
687};
688MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
689
690static int intel_pstate_init_cpu(unsigned int cpunum)
691{
692
693 const struct x86_cpu_id *id;
694 struct cpudata *cpu;
695
696 id = x86_match_cpu(intel_pstate_cpu_ids);
697 if (!id)
698 return -ENODEV;
699
700 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL);
701 if (!all_cpu_data[cpunum])
702 return -ENOMEM;
703
704 cpu = all_cpu_data[cpunum];
705
706 intel_pstate_get_cpu_pstates(cpu);
98a947ab
RW
707 if (!cpu->pstate.current_pstate) {
708 all_cpu_data[cpunum] = NULL;
709 kfree(cpu);
710 return -ENODATA;
711 }
93f0822d
DB
712
713 cpu->cpu = cpunum;
016c8150 714
93f0822d
DB
715 init_timer_deferrable(&cpu->timer);
716 cpu->timer.function = intel_pstate_timer_func;
717 cpu->timer.data =
718 (unsigned long)cpu;
719 cpu->timer.expires = jiffies + HZ/100;
720 intel_pstate_busy_pid_reset(cpu);
93f0822d
DB
721 intel_pstate_sample(cpu);
722 intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate);
723
724 add_timer_on(&cpu->timer, cpunum);
725
726 pr_info("Intel pstate controlling: cpu %d\n", cpunum);
727
728 return 0;
729}
730
731static unsigned int intel_pstate_get(unsigned int cpu_num)
732{
733 struct sample *sample;
734 struct cpudata *cpu;
735
736 cpu = all_cpu_data[cpu_num];
737 if (!cpu)
738 return 0;
d37e2b76 739 sample = &cpu->sample;
93f0822d
DB
740 return sample->freq;
741}
742
743static int intel_pstate_set_policy(struct cpufreq_policy *policy)
744{
745 struct cpudata *cpu;
93f0822d
DB
746
747 cpu = all_cpu_data[policy->cpu];
748
d3929b83
DB
749 if (!policy->cpuinfo.max_freq)
750 return -ENODEV;
751
93f0822d
DB
752 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
753 limits.min_perf_pct = 100;
754 limits.min_perf = int_tofp(1);
755 limits.max_perf_pct = 100;
756 limits.max_perf = int_tofp(1);
757 limits.no_turbo = 0;
d1b68485 758 return 0;
93f0822d 759 }
d1b68485
SP
760 limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
761 limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100);
762 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
763
d8f469e9
DB
764 limits.max_policy_pct = policy->max * 100 / policy->cpuinfo.max_freq;
765 limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);
766 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
d1b68485 767 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
93f0822d
DB
768
769 return 0;
770}
771
772static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
773{
be49e346 774 cpufreq_verify_within_cpu_limits(policy);
93f0822d
DB
775
776 if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) &&
777 (policy->policy != CPUFREQ_POLICY_PERFORMANCE))
778 return -EINVAL;
779
780 return 0;
781}
782
bb18008f 783static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 784{
bb18008f
DB
785 int cpu_num = policy->cpu;
786 struct cpudata *cpu = all_cpu_data[cpu_num];
93f0822d 787
bb18008f
DB
788 pr_info("intel_pstate CPU %d exiting\n", cpu_num);
789
c2294a2f 790 del_timer_sync(&all_cpu_data[cpu_num]->timer);
bb18008f
DB
791 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
792 kfree(all_cpu_data[cpu_num]);
793 all_cpu_data[cpu_num] = NULL;
93f0822d
DB
794}
795
2760984f 796static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 797{
93f0822d 798 struct cpudata *cpu;
52e0a509 799 int rc;
93f0822d
DB
800
801 rc = intel_pstate_init_cpu(policy->cpu);
802 if (rc)
803 return rc;
804
805 cpu = all_cpu_data[policy->cpu];
806
807 if (!limits.no_turbo &&
808 limits.min_perf_pct == 100 && limits.max_perf_pct == 100)
809 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
810 else
811 policy->policy = CPUFREQ_POLICY_POWERSAVE;
812
52e0a509
DB
813 policy->min = cpu->pstate.min_pstate * 100000;
814 policy->max = cpu->pstate.turbo_pstate * 100000;
93f0822d
DB
815
816 /* cpuinfo and default policy values */
817 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000;
818 policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000;
819 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
820 cpumask_set_cpu(policy->cpu, policy->cpus);
821
822 return 0;
823}
824
825static struct cpufreq_driver intel_pstate_driver = {
826 .flags = CPUFREQ_CONST_LOOPS,
827 .verify = intel_pstate_verify_policy,
828 .setpolicy = intel_pstate_set_policy,
829 .get = intel_pstate_get,
830 .init = intel_pstate_cpu_init,
bb18008f 831 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 832 .name = "intel_pstate",
93f0822d
DB
833};
834
6be26498
DB
835static int __initdata no_load;
836
b563b4e3
DB
837static int intel_pstate_msrs_not_valid(void)
838{
839 /* Check that all the msr's we are using are valid. */
840 u64 aperf, mperf, tmp;
841
842 rdmsrl(MSR_IA32_APERF, aperf);
843 rdmsrl(MSR_IA32_MPERF, mperf);
844
016c8150
DB
845 if (!pstate_funcs.get_max() ||
846 !pstate_funcs.get_min() ||
847 !pstate_funcs.get_turbo())
b563b4e3
DB
848 return -ENODEV;
849
850 rdmsrl(MSR_IA32_APERF, tmp);
851 if (!(tmp - aperf))
852 return -ENODEV;
853
854 rdmsrl(MSR_IA32_MPERF, tmp);
855 if (!(tmp - mperf))
856 return -ENODEV;
857
858 return 0;
859}
016c8150 860
e0a261a2 861static void copy_pid_params(struct pstate_adjust_policy *policy)
016c8150
DB
862{
863 pid_params.sample_rate_ms = policy->sample_rate_ms;
864 pid_params.p_gain_pct = policy->p_gain_pct;
865 pid_params.i_gain_pct = policy->i_gain_pct;
866 pid_params.d_gain_pct = policy->d_gain_pct;
867 pid_params.deadband = policy->deadband;
868 pid_params.setpoint = policy->setpoint;
869}
870
e0a261a2 871static void copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB
872{
873 pstate_funcs.get_max = funcs->get_max;
874 pstate_funcs.get_min = funcs->get_min;
875 pstate_funcs.get_turbo = funcs->get_turbo;
876 pstate_funcs.set = funcs->set;
007bea09 877 pstate_funcs.get_vid = funcs->get_vid;
016c8150
DB
878}
879
fbbcdc07
AH
880#if IS_ENABLED(CONFIG_ACPI)
881#include <acpi/processor.h>
882
883static bool intel_pstate_no_acpi_pss(void)
884{
885 int i;
886
887 for_each_possible_cpu(i) {
888 acpi_status status;
889 union acpi_object *pss;
890 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
891 struct acpi_processor *pr = per_cpu(processors, i);
892
893 if (!pr)
894 continue;
895
896 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
897 if (ACPI_FAILURE(status))
898 continue;
899
900 pss = buffer.pointer;
901 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
902 kfree(pss);
903 return false;
904 }
905
906 kfree(pss);
907 }
908
909 return true;
910}
911
912struct hw_vendor_info {
913 u16 valid;
914 char oem_id[ACPI_OEM_ID_SIZE];
915 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
916};
917
918/* Hardware vendor-specific info that has its own power management modes */
919static struct hw_vendor_info vendor_info[] = {
920 {1, "HP ", "ProLiant"},
921 {0, "", ""},
922};
923
924static bool intel_pstate_platform_pwr_mgmt_exists(void)
925{
926 struct acpi_table_header hdr;
927 struct hw_vendor_info *v_info;
928
929 if (acpi_disabled
930 || ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
931 return false;
932
933 for (v_info = vendor_info; v_info->valid; v_info++) {
934 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE)
935 && !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE)
936 && intel_pstate_no_acpi_pss())
937 return true;
938 }
939
940 return false;
941}
942#else /* CONFIG_ACPI not enabled */
943static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
944#endif /* CONFIG_ACPI */
945
93f0822d
DB
946static int __init intel_pstate_init(void)
947{
907cc908 948 int cpu, rc = 0;
93f0822d 949 const struct x86_cpu_id *id;
016c8150 950 struct cpu_defaults *cpu_info;
93f0822d 951
6be26498
DB
952 if (no_load)
953 return -ENODEV;
954
93f0822d
DB
955 id = x86_match_cpu(intel_pstate_cpu_ids);
956 if (!id)
957 return -ENODEV;
958
fbbcdc07
AH
959 /*
960 * The Intel pstate driver will be ignored if the platform
961 * firmware has its own power management modes.
962 */
963 if (intel_pstate_platform_pwr_mgmt_exists())
964 return -ENODEV;
965
016c8150
DB
966 cpu_info = (struct cpu_defaults *)id->driver_data;
967
968 copy_pid_params(&cpu_info->pid_policy);
969 copy_cpu_funcs(&cpu_info->funcs);
970
b563b4e3
DB
971 if (intel_pstate_msrs_not_valid())
972 return -ENODEV;
973
93f0822d
DB
974 pr_info("Intel P-state driver initializing.\n");
975
b57ffac5 976 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
93f0822d
DB
977 if (!all_cpu_data)
978 return -ENOMEM;
93f0822d
DB
979
980 rc = cpufreq_register_driver(&intel_pstate_driver);
981 if (rc)
982 goto out;
983
984 intel_pstate_debug_expose_params();
985 intel_pstate_sysfs_expose_params();
b69880f9 986
93f0822d
DB
987 return rc;
988out:
907cc908
DB
989 get_online_cpus();
990 for_each_online_cpu(cpu) {
991 if (all_cpu_data[cpu]) {
992 del_timer_sync(&all_cpu_data[cpu]->timer);
993 kfree(all_cpu_data[cpu]);
994 }
995 }
996
997 put_online_cpus();
998 vfree(all_cpu_data);
93f0822d
DB
999 return -ENODEV;
1000}
1001device_initcall(intel_pstate_init);
1002
6be26498
DB
1003static int __init intel_pstate_setup(char *str)
1004{
1005 if (!str)
1006 return -EINVAL;
1007
1008 if (!strcmp(str, "disable"))
1009 no_load = 1;
1010 return 0;
1011}
1012early_param("intel_pstate", intel_pstate_setup);
1013
93f0822d
DB
1014MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1015MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1016MODULE_LICENSE("GPL");
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