cpufreq: Kconfig: Fix spelling errors
[deliverable/linux.git] / drivers / cpufreq / intel_pstate.c
CommitLineData
93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13#include <linux/kernel.h>
14#include <linux/kernel_stat.h>
15#include <linux/module.h>
16#include <linux/ktime.h>
17#include <linux/hrtimer.h>
18#include <linux/tick.h>
19#include <linux/slab.h>
20#include <linux/sched.h>
21#include <linux/list.h>
22#include <linux/cpu.h>
23#include <linux/cpufreq.h>
24#include <linux/sysfs.h>
25#include <linux/types.h>
26#include <linux/fs.h>
27#include <linux/debugfs.h>
fbbcdc07 28#include <linux/acpi.h>
93f0822d
DB
29#include <trace/events/power.h>
30
31#include <asm/div64.h>
32#include <asm/msr.h>
33#include <asm/cpu_device_id.h>
34
35#define SAMPLE_COUNT 3
36
61d8d2ab
DB
37#define BYT_RATIOS 0x66a
38#define BYT_VIDS 0x66b
39#define BYT_TURBO_RATIOS 0x66c
40
19e77c28 41
e66c1768 42#define FRAC_BITS 6
93f0822d
DB
43#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
44#define fp_toint(X) ((X) >> FRAC_BITS)
e66c1768 45#define FP_ROUNDUP(X) ((X) += 1 << FRAC_BITS)
93f0822d
DB
46
47static inline int32_t mul_fp(int32_t x, int32_t y)
48{
49 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
50}
51
52static inline int32_t div_fp(int32_t x, int32_t y)
53{
54 return div_s64((int64_t)x << FRAC_BITS, (int64_t)y);
55}
56
57struct sample {
d253d2a5 58 int32_t core_pct_busy;
93f0822d
DB
59 u64 aperf;
60 u64 mperf;
fcb6a15c 61 unsigned long long tsc;
93f0822d
DB
62 int freq;
63};
64
65struct pstate_data {
66 int current_pstate;
67 int min_pstate;
68 int max_pstate;
69 int turbo_pstate;
70};
71
007bea09
DB
72struct vid_data {
73 int32_t min;
74 int32_t max;
75 int32_t ratio;
76};
77
93f0822d
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78struct _pid {
79 int setpoint;
80 int32_t integral;
81 int32_t p_gain;
82 int32_t i_gain;
83 int32_t d_gain;
84 int deadband;
d253d2a5 85 int32_t last_err;
93f0822d
DB
86};
87
88struct cpudata {
89 int cpu;
90
91 char name[64];
92
93 struct timer_list timer;
94
93f0822d 95 struct pstate_data pstate;
007bea09 96 struct vid_data vid;
93f0822d 97 struct _pid pid;
93f0822d 98
93f0822d
DB
99 u64 prev_aperf;
100 u64 prev_mperf;
fcb6a15c 101 unsigned long long prev_tsc;
d37e2b76 102 struct sample sample;
93f0822d
DB
103};
104
105static struct cpudata **all_cpu_data;
106struct pstate_adjust_policy {
107 int sample_rate_ms;
108 int deadband;
109 int setpoint;
110 int p_gain_pct;
111 int d_gain_pct;
112 int i_gain_pct;
113};
114
016c8150
DB
115struct pstate_funcs {
116 int (*get_max)(void);
117 int (*get_min)(void);
118 int (*get_turbo)(void);
007bea09
DB
119 void (*set)(struct cpudata*, int pstate);
120 void (*get_vid)(struct cpudata *);
93f0822d
DB
121};
122
016c8150
DB
123struct cpu_defaults {
124 struct pstate_adjust_policy pid_policy;
125 struct pstate_funcs funcs;
93f0822d
DB
126};
127
016c8150
DB
128static struct pstate_adjust_policy pid_params;
129static struct pstate_funcs pstate_funcs;
130
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DB
131struct perf_limits {
132 int no_turbo;
133 int max_perf_pct;
134 int min_perf_pct;
135 int32_t max_perf;
136 int32_t min_perf;
d8f469e9
DB
137 int max_policy_pct;
138 int max_sysfs_pct;
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DB
139};
140
141static struct perf_limits limits = {
142 .no_turbo = 0,
143 .max_perf_pct = 100,
144 .max_perf = int_tofp(1),
145 .min_perf_pct = 0,
146 .min_perf = 0,
d8f469e9
DB
147 .max_policy_pct = 100,
148 .max_sysfs_pct = 100,
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149};
150
151static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
152 int deadband, int integral) {
153 pid->setpoint = setpoint;
154 pid->deadband = deadband;
155 pid->integral = int_tofp(integral);
d98d099b 156 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
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DB
157}
158
159static inline void pid_p_gain_set(struct _pid *pid, int percent)
160{
161 pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));
162}
163
164static inline void pid_i_gain_set(struct _pid *pid, int percent)
165{
166 pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));
167}
168
169static inline void pid_d_gain_set(struct _pid *pid, int percent)
170{
171
172 pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
173}
174
d253d2a5 175static signed int pid_calc(struct _pid *pid, int32_t busy)
93f0822d 176{
d253d2a5 177 signed int result;
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DB
178 int32_t pterm, dterm, fp_error;
179 int32_t integral_limit;
180
d253d2a5 181 fp_error = int_tofp(pid->setpoint) - busy;
93f0822d 182
d253d2a5 183 if (abs(fp_error) <= int_tofp(pid->deadband))
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DB
184 return 0;
185
186 pterm = mul_fp(pid->p_gain, fp_error);
187
188 pid->integral += fp_error;
189
190 /* limit the integral term */
191 integral_limit = int_tofp(30);
192 if (pid->integral > integral_limit)
193 pid->integral = integral_limit;
194 if (pid->integral < -integral_limit)
195 pid->integral = -integral_limit;
196
d253d2a5
BS
197 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
198 pid->last_err = fp_error;
93f0822d
DB
199
200 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
201
202 return (signed int)fp_toint(result);
203}
204
205static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
206{
016c8150
DB
207 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
208 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
209 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
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210
211 pid_reset(&cpu->pid,
016c8150 212 pid_params.setpoint,
93f0822d 213 100,
016c8150 214 pid_params.deadband,
93f0822d
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215 0);
216}
217
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218static inline void intel_pstate_reset_all_pid(void)
219{
220 unsigned int cpu;
221 for_each_online_cpu(cpu) {
222 if (all_cpu_data[cpu])
223 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
224 }
225}
226
227/************************** debugfs begin ************************/
228static int pid_param_set(void *data, u64 val)
229{
230 *(u32 *)data = val;
231 intel_pstate_reset_all_pid();
232 return 0;
233}
234static int pid_param_get(void *data, u64 *val)
235{
236 *val = *(u32 *)data;
237 return 0;
238}
239DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get,
240 pid_param_set, "%llu\n");
241
242struct pid_param {
243 char *name;
244 void *value;
245};
246
247static struct pid_param pid_files[] = {
016c8150
DB
248 {"sample_rate_ms", &pid_params.sample_rate_ms},
249 {"d_gain_pct", &pid_params.d_gain_pct},
250 {"i_gain_pct", &pid_params.i_gain_pct},
251 {"deadband", &pid_params.deadband},
252 {"setpoint", &pid_params.setpoint},
253 {"p_gain_pct", &pid_params.p_gain_pct},
93f0822d
DB
254 {NULL, NULL}
255};
256
257static struct dentry *debugfs_parent;
258static void intel_pstate_debug_expose_params(void)
259{
260 int i = 0;
261
262 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
263 if (IS_ERR_OR_NULL(debugfs_parent))
264 return;
265 while (pid_files[i].name) {
266 debugfs_create_file(pid_files[i].name, 0660,
267 debugfs_parent, pid_files[i].value,
268 &fops_pid_param);
269 i++;
270 }
271}
272
273/************************** debugfs end ************************/
274
275/************************** sysfs begin ************************/
276#define show_one(file_name, object) \
277 static ssize_t show_##file_name \
278 (struct kobject *kobj, struct attribute *attr, char *buf) \
279 { \
280 return sprintf(buf, "%u\n", limits.object); \
281 }
282
283static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
284 const char *buf, size_t count)
285{
286 unsigned int input;
287 int ret;
288 ret = sscanf(buf, "%u", &input);
289 if (ret != 1)
290 return -EINVAL;
291 limits.no_turbo = clamp_t(int, input, 0 , 1);
292
293 return count;
294}
295
296static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
297 const char *buf, size_t count)
298{
299 unsigned int input;
300 int ret;
301 ret = sscanf(buf, "%u", &input);
302 if (ret != 1)
303 return -EINVAL;
304
d8f469e9
DB
305 limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);
306 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
93f0822d
DB
307 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
308 return count;
309}
310
311static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
312 const char *buf, size_t count)
313{
314 unsigned int input;
315 int ret;
316 ret = sscanf(buf, "%u", &input);
317 if (ret != 1)
318 return -EINVAL;
319 limits.min_perf_pct = clamp_t(int, input, 0 , 100);
320 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
321
322 return count;
323}
324
325show_one(no_turbo, no_turbo);
326show_one(max_perf_pct, max_perf_pct);
327show_one(min_perf_pct, min_perf_pct);
328
329define_one_global_rw(no_turbo);
330define_one_global_rw(max_perf_pct);
331define_one_global_rw(min_perf_pct);
332
333static struct attribute *intel_pstate_attributes[] = {
334 &no_turbo.attr,
335 &max_perf_pct.attr,
336 &min_perf_pct.attr,
337 NULL
338};
339
340static struct attribute_group intel_pstate_attr_group = {
341 .attrs = intel_pstate_attributes,
342};
343static struct kobject *intel_pstate_kobject;
344
345static void intel_pstate_sysfs_expose_params(void)
346{
347 int rc;
348
349 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
350 &cpu_subsys.dev_root->kobj);
351 BUG_ON(!intel_pstate_kobject);
352 rc = sysfs_create_group(intel_pstate_kobject,
353 &intel_pstate_attr_group);
354 BUG_ON(rc);
355}
356
357/************************** sysfs end ************************/
19e77c28
DB
358static int byt_get_min_pstate(void)
359{
360 u64 value;
361 rdmsrl(BYT_RATIOS, value);
4042e757 362 return (value >> 8) & 0xFF;
19e77c28
DB
363}
364
365static int byt_get_max_pstate(void)
366{
367 u64 value;
368 rdmsrl(BYT_RATIOS, value);
369 return (value >> 16) & 0xFF;
370}
93f0822d 371
61d8d2ab
DB
372static int byt_get_turbo_pstate(void)
373{
374 u64 value;
375 rdmsrl(BYT_TURBO_RATIOS, value);
376 return value & 0x3F;
377}
378
007bea09
DB
379static void byt_set_pstate(struct cpudata *cpudata, int pstate)
380{
381 u64 val;
382 int32_t vid_fp;
383 u32 vid;
384
385 val = pstate << 8;
386 if (limits.no_turbo)
387 val |= (u64)1 << 32;
388
389 vid_fp = cpudata->vid.min + mul_fp(
390 int_tofp(pstate - cpudata->pstate.min_pstate),
391 cpudata->vid.ratio);
392
393 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
394 vid = fp_toint(vid_fp);
395
396 val |= vid;
397
398 wrmsrl(MSR_IA32_PERF_CTL, val);
399}
400
401static void byt_get_vid(struct cpudata *cpudata)
402{
403 u64 value;
404
405 rdmsrl(BYT_VIDS, value);
406 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
407 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
408 cpudata->vid.ratio = div_fp(
409 cpudata->vid.max - cpudata->vid.min,
410 int_tofp(cpudata->pstate.max_pstate -
411 cpudata->pstate.min_pstate));
412}
413
414
016c8150 415static int core_get_min_pstate(void)
93f0822d
DB
416{
417 u64 value;
05e99c8c 418 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB
419 return (value >> 40) & 0xFF;
420}
421
016c8150 422static int core_get_max_pstate(void)
93f0822d
DB
423{
424 u64 value;
05e99c8c 425 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB
426 return (value >> 8) & 0xFF;
427}
428
016c8150 429static int core_get_turbo_pstate(void)
93f0822d
DB
430{
431 u64 value;
432 int nont, ret;
05e99c8c 433 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
016c8150 434 nont = core_get_max_pstate();
93f0822d
DB
435 ret = ((value) & 255);
436 if (ret <= nont)
437 ret = nont;
438 return ret;
439}
440
007bea09 441static void core_set_pstate(struct cpudata *cpudata, int pstate)
016c8150
DB
442{
443 u64 val;
444
445 val = pstate << 8;
446 if (limits.no_turbo)
447 val |= (u64)1 << 32;
448
bb18008f 449 wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
016c8150
DB
450}
451
452static struct cpu_defaults core_params = {
453 .pid_policy = {
454 .sample_rate_ms = 10,
455 .deadband = 0,
456 .setpoint = 97,
457 .p_gain_pct = 20,
458 .d_gain_pct = 0,
459 .i_gain_pct = 0,
460 },
461 .funcs = {
462 .get_max = core_get_max_pstate,
463 .get_min = core_get_min_pstate,
464 .get_turbo = core_get_turbo_pstate,
465 .set = core_set_pstate,
466 },
467};
468
19e77c28
DB
469static struct cpu_defaults byt_params = {
470 .pid_policy = {
471 .sample_rate_ms = 10,
472 .deadband = 0,
473 .setpoint = 97,
474 .p_gain_pct = 14,
475 .d_gain_pct = 0,
476 .i_gain_pct = 4,
477 },
478 .funcs = {
479 .get_max = byt_get_max_pstate,
480 .get_min = byt_get_min_pstate,
61d8d2ab 481 .get_turbo = byt_get_turbo_pstate,
007bea09
DB
482 .set = byt_set_pstate,
483 .get_vid = byt_get_vid,
19e77c28
DB
484 },
485};
486
487
93f0822d
DB
488static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
489{
490 int max_perf = cpu->pstate.turbo_pstate;
7244cb62 491 int max_perf_adj;
93f0822d
DB
492 int min_perf;
493 if (limits.no_turbo)
494 max_perf = cpu->pstate.max_pstate;
495
7244cb62
DB
496 max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
497 *max = clamp_t(int, max_perf_adj,
93f0822d
DB
498 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
499
500 min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
501 *min = clamp_t(int, min_perf,
502 cpu->pstate.min_pstate, max_perf);
503}
504
505static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
506{
507 int max_perf, min_perf;
508
509 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
510
511 pstate = clamp_t(int, pstate, min_perf, max_perf);
512
513 if (pstate == cpu->pstate.current_pstate)
514 return;
515
93f0822d 516 trace_cpu_frequency(pstate * 100000, cpu->cpu);
35363e94 517
93f0822d 518 cpu->pstate.current_pstate = pstate;
93f0822d 519
007bea09 520 pstate_funcs.set(cpu, pstate);
93f0822d
DB
521}
522
523static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps)
524{
525 int target;
526 target = cpu->pstate.current_pstate + steps;
527
528 intel_pstate_set_pstate(cpu, target);
529}
530
531static inline void intel_pstate_pstate_decrease(struct cpudata *cpu, int steps)
532{
533 int target;
534 target = cpu->pstate.current_pstate - steps;
535 intel_pstate_set_pstate(cpu, target);
536}
537
538static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
539{
540 sprintf(cpu->name, "Intel 2nd generation core");
541
016c8150
DB
542 cpu->pstate.min_pstate = pstate_funcs.get_min();
543 cpu->pstate.max_pstate = pstate_funcs.get_max();
544 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
93f0822d 545
007bea09
DB
546 if (pstate_funcs.get_vid)
547 pstate_funcs.get_vid(cpu);
548
93f0822d
DB
549 /*
550 * goto max pstate so we don't slow up boot if we are built-in if we are
551 * a module we will take care of it during normal operation
552 */
553 intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate);
554}
555
556static inline void intel_pstate_calc_busy(struct cpudata *cpu,
557 struct sample *sample)
558{
e66c1768
DB
559 int32_t core_pct;
560 int32_t c0_pct;
93f0822d 561
e66c1768
DB
562 core_pct = div_fp(int_tofp((sample->aperf)),
563 int_tofp((sample->mperf)));
564 core_pct = mul_fp(core_pct, int_tofp(100));
565 FP_ROUNDUP(core_pct);
566
567 c0_pct = div_fp(int_tofp(sample->mperf), int_tofp(sample->tsc));
fcb6a15c 568
fcb6a15c 569 sample->freq = fp_toint(
e66c1768 570 mul_fp(int_tofp(cpu->pstate.max_pstate * 1000), core_pct));
fcb6a15c 571
e66c1768 572 sample->core_pct_busy = mul_fp(core_pct, c0_pct);
93f0822d
DB
573}
574
575static inline void intel_pstate_sample(struct cpudata *cpu)
576{
93f0822d 577 u64 aperf, mperf;
fcb6a15c 578 unsigned long long tsc;
93f0822d 579
93f0822d
DB
580 rdmsrl(MSR_IA32_APERF, aperf);
581 rdmsrl(MSR_IA32_MPERF, mperf);
fcb6a15c 582 tsc = native_read_tsc();
b69880f9 583
e66c1768
DB
584 aperf = aperf >> FRAC_BITS;
585 mperf = mperf >> FRAC_BITS;
586 tsc = tsc >> FRAC_BITS;
587
d37e2b76
DB
588 cpu->sample.aperf = aperf;
589 cpu->sample.mperf = mperf;
590 cpu->sample.tsc = tsc;
591 cpu->sample.aperf -= cpu->prev_aperf;
592 cpu->sample.mperf -= cpu->prev_mperf;
593 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 594
d37e2b76 595 intel_pstate_calc_busy(cpu, &cpu->sample);
93f0822d 596
93f0822d
DB
597 cpu->prev_aperf = aperf;
598 cpu->prev_mperf = mperf;
fcb6a15c 599 cpu->prev_tsc = tsc;
93f0822d
DB
600}
601
602static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
603{
604 int sample_time, delay;
605
016c8150 606 sample_time = pid_params.sample_rate_ms;
93f0822d 607 delay = msecs_to_jiffies(sample_time);
93f0822d
DB
608 mod_timer_pinned(&cpu->timer, jiffies + delay);
609}
610
d253d2a5 611static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
93f0822d 612{
2134ed4d 613 int32_t core_busy, max_pstate, current_pstate;
93f0822d 614
d37e2b76 615 core_busy = cpu->sample.core_pct_busy;
2134ed4d 616 max_pstate = int_tofp(cpu->pstate.max_pstate);
93f0822d 617 current_pstate = int_tofp(cpu->pstate.current_pstate);
e66c1768
DB
618 core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
619 return FP_ROUNDUP(core_busy);
93f0822d
DB
620}
621
622static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
623{
d253d2a5 624 int32_t busy_scaled;
93f0822d
DB
625 struct _pid *pid;
626 signed int ctl = 0;
627 int steps;
628
629 pid = &cpu->pid;
630 busy_scaled = intel_pstate_get_scaled_busy(cpu);
631
632 ctl = pid_calc(pid, busy_scaled);
633
634 steps = abs(ctl);
b69880f9 635
93f0822d
DB
636 if (ctl < 0)
637 intel_pstate_pstate_increase(cpu, steps);
638 else
639 intel_pstate_pstate_decrease(cpu, steps);
640}
641
93f0822d
DB
642static void intel_pstate_timer_func(unsigned long __data)
643{
644 struct cpudata *cpu = (struct cpudata *) __data;
b69880f9 645 struct sample *sample;
93f0822d
DB
646
647 intel_pstate_sample(cpu);
b69880f9 648
d37e2b76 649 sample = &cpu->sample;
b69880f9 650
ca182aee 651 intel_pstate_adjust_busy_pstate(cpu);
b69880f9
DB
652
653 trace_pstate_sample(fp_toint(sample->core_pct_busy),
654 fp_toint(intel_pstate_get_scaled_busy(cpu)),
655 cpu->pstate.current_pstate,
656 sample->mperf,
657 sample->aperf,
b69880f9
DB
658 sample->freq);
659
93f0822d
DB
660 intel_pstate_set_sample_time(cpu);
661}
662
663#define ICPU(model, policy) \
6cbd7ee1
DB
664 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
665 (unsigned long)&policy }
93f0822d
DB
666
667static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
016c8150
DB
668 ICPU(0x2a, core_params),
669 ICPU(0x2d, core_params),
19e77c28 670 ICPU(0x37, byt_params),
016c8150
DB
671 ICPU(0x3a, core_params),
672 ICPU(0x3c, core_params),
673 ICPU(0x3e, core_params),
674 ICPU(0x3f, core_params),
675 ICPU(0x45, core_params),
676 ICPU(0x46, core_params),
93f0822d
DB
677 {}
678};
679MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
680
681static int intel_pstate_init_cpu(unsigned int cpunum)
682{
683
684 const struct x86_cpu_id *id;
685 struct cpudata *cpu;
686
687 id = x86_match_cpu(intel_pstate_cpu_ids);
688 if (!id)
689 return -ENODEV;
690
691 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL);
692 if (!all_cpu_data[cpunum])
693 return -ENOMEM;
694
695 cpu = all_cpu_data[cpunum];
696
697 intel_pstate_get_cpu_pstates(cpu);
98a947ab
RW
698 if (!cpu->pstate.current_pstate) {
699 all_cpu_data[cpunum] = NULL;
700 kfree(cpu);
701 return -ENODATA;
702 }
93f0822d
DB
703
704 cpu->cpu = cpunum;
016c8150 705
93f0822d
DB
706 init_timer_deferrable(&cpu->timer);
707 cpu->timer.function = intel_pstate_timer_func;
708 cpu->timer.data =
709 (unsigned long)cpu;
710 cpu->timer.expires = jiffies + HZ/100;
711 intel_pstate_busy_pid_reset(cpu);
93f0822d
DB
712 intel_pstate_sample(cpu);
713 intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate);
714
715 add_timer_on(&cpu->timer, cpunum);
716
717 pr_info("Intel pstate controlling: cpu %d\n", cpunum);
718
719 return 0;
720}
721
722static unsigned int intel_pstate_get(unsigned int cpu_num)
723{
724 struct sample *sample;
725 struct cpudata *cpu;
726
727 cpu = all_cpu_data[cpu_num];
728 if (!cpu)
729 return 0;
d37e2b76 730 sample = &cpu->sample;
93f0822d
DB
731 return sample->freq;
732}
733
734static int intel_pstate_set_policy(struct cpufreq_policy *policy)
735{
736 struct cpudata *cpu;
93f0822d
DB
737
738 cpu = all_cpu_data[policy->cpu];
739
d3929b83
DB
740 if (!policy->cpuinfo.max_freq)
741 return -ENODEV;
742
93f0822d
DB
743 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
744 limits.min_perf_pct = 100;
745 limits.min_perf = int_tofp(1);
746 limits.max_perf_pct = 100;
747 limits.max_perf = int_tofp(1);
748 limits.no_turbo = 0;
d1b68485 749 return 0;
93f0822d 750 }
d1b68485
SP
751 limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
752 limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100);
753 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
754
d8f469e9
DB
755 limits.max_policy_pct = policy->max * 100 / policy->cpuinfo.max_freq;
756 limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);
757 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
d1b68485 758 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
93f0822d
DB
759
760 return 0;
761}
762
763static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
764{
be49e346 765 cpufreq_verify_within_cpu_limits(policy);
93f0822d
DB
766
767 if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) &&
768 (policy->policy != CPUFREQ_POLICY_PERFORMANCE))
769 return -EINVAL;
770
771 return 0;
772}
773
bb18008f 774static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 775{
bb18008f
DB
776 int cpu_num = policy->cpu;
777 struct cpudata *cpu = all_cpu_data[cpu_num];
93f0822d 778
bb18008f
DB
779 pr_info("intel_pstate CPU %d exiting\n", cpu_num);
780
c2294a2f 781 del_timer_sync(&all_cpu_data[cpu_num]->timer);
bb18008f
DB
782 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
783 kfree(all_cpu_data[cpu_num]);
784 all_cpu_data[cpu_num] = NULL;
93f0822d
DB
785}
786
2760984f 787static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 788{
93f0822d 789 struct cpudata *cpu;
52e0a509 790 int rc;
93f0822d
DB
791
792 rc = intel_pstate_init_cpu(policy->cpu);
793 if (rc)
794 return rc;
795
796 cpu = all_cpu_data[policy->cpu];
797
798 if (!limits.no_turbo &&
799 limits.min_perf_pct == 100 && limits.max_perf_pct == 100)
800 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
801 else
802 policy->policy = CPUFREQ_POLICY_POWERSAVE;
803
52e0a509
DB
804 policy->min = cpu->pstate.min_pstate * 100000;
805 policy->max = cpu->pstate.turbo_pstate * 100000;
93f0822d
DB
806
807 /* cpuinfo and default policy values */
808 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000;
809 policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000;
810 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
811 cpumask_set_cpu(policy->cpu, policy->cpus);
812
813 return 0;
814}
815
816static struct cpufreq_driver intel_pstate_driver = {
817 .flags = CPUFREQ_CONST_LOOPS,
818 .verify = intel_pstate_verify_policy,
819 .setpolicy = intel_pstate_set_policy,
820 .get = intel_pstate_get,
821 .init = intel_pstate_cpu_init,
bb18008f 822 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 823 .name = "intel_pstate",
93f0822d
DB
824};
825
6be26498
DB
826static int __initdata no_load;
827
b563b4e3
DB
828static int intel_pstate_msrs_not_valid(void)
829{
830 /* Check that all the msr's we are using are valid. */
831 u64 aperf, mperf, tmp;
832
833 rdmsrl(MSR_IA32_APERF, aperf);
834 rdmsrl(MSR_IA32_MPERF, mperf);
835
016c8150
DB
836 if (!pstate_funcs.get_max() ||
837 !pstate_funcs.get_min() ||
838 !pstate_funcs.get_turbo())
b563b4e3
DB
839 return -ENODEV;
840
841 rdmsrl(MSR_IA32_APERF, tmp);
842 if (!(tmp - aperf))
843 return -ENODEV;
844
845 rdmsrl(MSR_IA32_MPERF, tmp);
846 if (!(tmp - mperf))
847 return -ENODEV;
848
849 return 0;
850}
016c8150 851
e0a261a2 852static void copy_pid_params(struct pstate_adjust_policy *policy)
016c8150
DB
853{
854 pid_params.sample_rate_ms = policy->sample_rate_ms;
855 pid_params.p_gain_pct = policy->p_gain_pct;
856 pid_params.i_gain_pct = policy->i_gain_pct;
857 pid_params.d_gain_pct = policy->d_gain_pct;
858 pid_params.deadband = policy->deadband;
859 pid_params.setpoint = policy->setpoint;
860}
861
e0a261a2 862static void copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB
863{
864 pstate_funcs.get_max = funcs->get_max;
865 pstate_funcs.get_min = funcs->get_min;
866 pstate_funcs.get_turbo = funcs->get_turbo;
867 pstate_funcs.set = funcs->set;
007bea09 868 pstate_funcs.get_vid = funcs->get_vid;
016c8150
DB
869}
870
fbbcdc07
AH
871#if IS_ENABLED(CONFIG_ACPI)
872#include <acpi/processor.h>
873
874static bool intel_pstate_no_acpi_pss(void)
875{
876 int i;
877
878 for_each_possible_cpu(i) {
879 acpi_status status;
880 union acpi_object *pss;
881 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
882 struct acpi_processor *pr = per_cpu(processors, i);
883
884 if (!pr)
885 continue;
886
887 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
888 if (ACPI_FAILURE(status))
889 continue;
890
891 pss = buffer.pointer;
892 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
893 kfree(pss);
894 return false;
895 }
896
897 kfree(pss);
898 }
899
900 return true;
901}
902
903struct hw_vendor_info {
904 u16 valid;
905 char oem_id[ACPI_OEM_ID_SIZE];
906 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
907};
908
909/* Hardware vendor-specific info that has its own power management modes */
910static struct hw_vendor_info vendor_info[] = {
911 {1, "HP ", "ProLiant"},
912 {0, "", ""},
913};
914
915static bool intel_pstate_platform_pwr_mgmt_exists(void)
916{
917 struct acpi_table_header hdr;
918 struct hw_vendor_info *v_info;
919
920 if (acpi_disabled
921 || ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
922 return false;
923
924 for (v_info = vendor_info; v_info->valid; v_info++) {
925 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE)
926 && !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE)
927 && intel_pstate_no_acpi_pss())
928 return true;
929 }
930
931 return false;
932}
933#else /* CONFIG_ACPI not enabled */
934static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
935#endif /* CONFIG_ACPI */
936
93f0822d
DB
937static int __init intel_pstate_init(void)
938{
907cc908 939 int cpu, rc = 0;
93f0822d 940 const struct x86_cpu_id *id;
016c8150 941 struct cpu_defaults *cpu_info;
93f0822d 942
6be26498
DB
943 if (no_load)
944 return -ENODEV;
945
93f0822d
DB
946 id = x86_match_cpu(intel_pstate_cpu_ids);
947 if (!id)
948 return -ENODEV;
949
fbbcdc07
AH
950 /*
951 * The Intel pstate driver will be ignored if the platform
952 * firmware has its own power management modes.
953 */
954 if (intel_pstate_platform_pwr_mgmt_exists())
955 return -ENODEV;
956
016c8150
DB
957 cpu_info = (struct cpu_defaults *)id->driver_data;
958
959 copy_pid_params(&cpu_info->pid_policy);
960 copy_cpu_funcs(&cpu_info->funcs);
961
b563b4e3
DB
962 if (intel_pstate_msrs_not_valid())
963 return -ENODEV;
964
93f0822d
DB
965 pr_info("Intel P-state driver initializing.\n");
966
b57ffac5 967 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
93f0822d
DB
968 if (!all_cpu_data)
969 return -ENOMEM;
93f0822d
DB
970
971 rc = cpufreq_register_driver(&intel_pstate_driver);
972 if (rc)
973 goto out;
974
975 intel_pstate_debug_expose_params();
976 intel_pstate_sysfs_expose_params();
b69880f9 977
93f0822d
DB
978 return rc;
979out:
907cc908
DB
980 get_online_cpus();
981 for_each_online_cpu(cpu) {
982 if (all_cpu_data[cpu]) {
983 del_timer_sync(&all_cpu_data[cpu]->timer);
984 kfree(all_cpu_data[cpu]);
985 }
986 }
987
988 put_online_cpus();
989 vfree(all_cpu_data);
93f0822d
DB
990 return -ENODEV;
991}
992device_initcall(intel_pstate_init);
993
6be26498
DB
994static int __init intel_pstate_setup(char *str)
995{
996 if (!str)
997 return -EINVAL;
998
999 if (!strcmp(str, "disable"))
1000 no_load = 1;
1001 return 0;
1002}
1003early_param("intel_pstate", intel_pstate_setup);
1004
93f0822d
DB
1005MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1006MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1007MODULE_LICENSE("GPL");
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