cpufreq: expose scaling_cur_freq sysfs file for set_policy() drivers
[deliverable/linux.git] / drivers / cpufreq / intel_pstate.c
CommitLineData
93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13#include <linux/kernel.h>
14#include <linux/kernel_stat.h>
15#include <linux/module.h>
16#include <linux/ktime.h>
17#include <linux/hrtimer.h>
18#include <linux/tick.h>
19#include <linux/slab.h>
20#include <linux/sched.h>
21#include <linux/list.h>
22#include <linux/cpu.h>
23#include <linux/cpufreq.h>
24#include <linux/sysfs.h>
25#include <linux/types.h>
26#include <linux/fs.h>
27#include <linux/debugfs.h>
fbbcdc07 28#include <linux/acpi.h>
93f0822d
DB
29#include <trace/events/power.h>
30
31#include <asm/div64.h>
32#include <asm/msr.h>
33#include <asm/cpu_device_id.h>
34
61d8d2ab
DB
35#define BYT_RATIOS 0x66a
36#define BYT_VIDS 0x66b
37#define BYT_TURBO_RATIOS 0x66c
21855ff5 38#define BYT_TURBO_VIDS 0x66d
61d8d2ab 39
f0fe3cd7 40#define FRAC_BITS 8
93f0822d
DB
41#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
42#define fp_toint(X) ((X) >> FRAC_BITS)
f0fe3cd7 43
93f0822d
DB
44
45static inline int32_t mul_fp(int32_t x, int32_t y)
46{
47 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
48}
49
50static inline int32_t div_fp(int32_t x, int32_t y)
51{
fa30dff9 52 return div_s64((int64_t)x << FRAC_BITS, y);
93f0822d
DB
53}
54
55struct sample {
d253d2a5 56 int32_t core_pct_busy;
93f0822d
DB
57 u64 aperf;
58 u64 mperf;
59 int freq;
c4ee841f 60 ktime_t time;
93f0822d
DB
61};
62
63struct pstate_data {
64 int current_pstate;
65 int min_pstate;
66 int max_pstate;
67 int turbo_pstate;
68};
69
007bea09 70struct vid_data {
21855ff5
DB
71 int min;
72 int max;
73 int turbo;
007bea09
DB
74 int32_t ratio;
75};
76
93f0822d
DB
77struct _pid {
78 int setpoint;
79 int32_t integral;
80 int32_t p_gain;
81 int32_t i_gain;
82 int32_t d_gain;
83 int deadband;
d253d2a5 84 int32_t last_err;
93f0822d
DB
85};
86
87struct cpudata {
88 int cpu;
89
93f0822d
DB
90 struct timer_list timer;
91
93f0822d 92 struct pstate_data pstate;
007bea09 93 struct vid_data vid;
93f0822d 94 struct _pid pid;
93f0822d 95
c4ee841f 96 ktime_t last_sample_time;
93f0822d
DB
97 u64 prev_aperf;
98 u64 prev_mperf;
d37e2b76 99 struct sample sample;
93f0822d
DB
100};
101
102static struct cpudata **all_cpu_data;
103struct pstate_adjust_policy {
104 int sample_rate_ms;
105 int deadband;
106 int setpoint;
107 int p_gain_pct;
108 int d_gain_pct;
109 int i_gain_pct;
110};
111
016c8150
DB
112struct pstate_funcs {
113 int (*get_max)(void);
114 int (*get_min)(void);
115 int (*get_turbo)(void);
007bea09
DB
116 void (*set)(struct cpudata*, int pstate);
117 void (*get_vid)(struct cpudata *);
93f0822d
DB
118};
119
016c8150
DB
120struct cpu_defaults {
121 struct pstate_adjust_policy pid_policy;
122 struct pstate_funcs funcs;
93f0822d
DB
123};
124
016c8150
DB
125static struct pstate_adjust_policy pid_params;
126static struct pstate_funcs pstate_funcs;
127
93f0822d
DB
128struct perf_limits {
129 int no_turbo;
dd5fbf70 130 int turbo_disabled;
93f0822d
DB
131 int max_perf_pct;
132 int min_perf_pct;
133 int32_t max_perf;
134 int32_t min_perf;
d8f469e9
DB
135 int max_policy_pct;
136 int max_sysfs_pct;
93f0822d
DB
137};
138
139static struct perf_limits limits = {
140 .no_turbo = 0,
141 .max_perf_pct = 100,
142 .max_perf = int_tofp(1),
143 .min_perf_pct = 0,
144 .min_perf = 0,
d8f469e9
DB
145 .max_policy_pct = 100,
146 .max_sysfs_pct = 100,
93f0822d
DB
147};
148
149static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
c410833a 150 int deadband, int integral) {
93f0822d
DB
151 pid->setpoint = setpoint;
152 pid->deadband = deadband;
153 pid->integral = int_tofp(integral);
d98d099b 154 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
93f0822d
DB
155}
156
157static inline void pid_p_gain_set(struct _pid *pid, int percent)
158{
159 pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));
160}
161
162static inline void pid_i_gain_set(struct _pid *pid, int percent)
163{
164 pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));
165}
166
167static inline void pid_d_gain_set(struct _pid *pid, int percent)
168{
93f0822d
DB
169 pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
170}
171
d253d2a5 172static signed int pid_calc(struct _pid *pid, int32_t busy)
93f0822d 173{
d253d2a5 174 signed int result;
93f0822d
DB
175 int32_t pterm, dterm, fp_error;
176 int32_t integral_limit;
177
d253d2a5 178 fp_error = int_tofp(pid->setpoint) - busy;
93f0822d 179
d253d2a5 180 if (abs(fp_error) <= int_tofp(pid->deadband))
93f0822d
DB
181 return 0;
182
183 pterm = mul_fp(pid->p_gain, fp_error);
184
185 pid->integral += fp_error;
186
187 /* limit the integral term */
188 integral_limit = int_tofp(30);
189 if (pid->integral > integral_limit)
190 pid->integral = integral_limit;
191 if (pid->integral < -integral_limit)
192 pid->integral = -integral_limit;
193
d253d2a5
BS
194 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
195 pid->last_err = fp_error;
93f0822d
DB
196
197 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
51d211e9 198 result = result + (1 << (FRAC_BITS-1));
93f0822d
DB
199 return (signed int)fp_toint(result);
200}
201
202static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
203{
016c8150
DB
204 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
205 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
206 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
93f0822d 207
2d8d1f18 208 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
93f0822d
DB
209}
210
93f0822d
DB
211static inline void intel_pstate_reset_all_pid(void)
212{
213 unsigned int cpu;
845c1cbe 214
93f0822d
DB
215 for_each_online_cpu(cpu) {
216 if (all_cpu_data[cpu])
217 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
218 }
219}
220
221/************************** debugfs begin ************************/
222static int pid_param_set(void *data, u64 val)
223{
224 *(u32 *)data = val;
225 intel_pstate_reset_all_pid();
226 return 0;
227}
845c1cbe 228
93f0822d
DB
229static int pid_param_get(void *data, u64 *val)
230{
231 *val = *(u32 *)data;
232 return 0;
233}
2d8d1f18 234DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
93f0822d
DB
235
236struct pid_param {
237 char *name;
238 void *value;
239};
240
241static struct pid_param pid_files[] = {
016c8150
DB
242 {"sample_rate_ms", &pid_params.sample_rate_ms},
243 {"d_gain_pct", &pid_params.d_gain_pct},
244 {"i_gain_pct", &pid_params.i_gain_pct},
245 {"deadband", &pid_params.deadband},
246 {"setpoint", &pid_params.setpoint},
247 {"p_gain_pct", &pid_params.p_gain_pct},
93f0822d
DB
248 {NULL, NULL}
249};
250
317dd50e 251static void __init intel_pstate_debug_expose_params(void)
93f0822d 252{
317dd50e 253 struct dentry *debugfs_parent;
93f0822d
DB
254 int i = 0;
255
256 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
257 if (IS_ERR_OR_NULL(debugfs_parent))
258 return;
259 while (pid_files[i].name) {
260 debugfs_create_file(pid_files[i].name, 0660,
c410833a
SK
261 debugfs_parent, pid_files[i].value,
262 &fops_pid_param);
93f0822d
DB
263 i++;
264 }
265}
266
267/************************** debugfs end ************************/
268
269/************************** sysfs begin ************************/
270#define show_one(file_name, object) \
271 static ssize_t show_##file_name \
272 (struct kobject *kobj, struct attribute *attr, char *buf) \
273 { \
274 return sprintf(buf, "%u\n", limits.object); \
275 }
276
277static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
c410833a 278 const char *buf, size_t count)
93f0822d
DB
279{
280 unsigned int input;
281 int ret;
845c1cbe 282
93f0822d
DB
283 ret = sscanf(buf, "%u", &input);
284 if (ret != 1)
285 return -EINVAL;
286 limits.no_turbo = clamp_t(int, input, 0 , 1);
dd5fbf70
DB
287 if (limits.turbo_disabled) {
288 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
289 limits.no_turbo = limits.turbo_disabled;
290 }
93f0822d
DB
291 return count;
292}
293
294static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
c410833a 295 const char *buf, size_t count)
93f0822d
DB
296{
297 unsigned int input;
298 int ret;
845c1cbe 299
93f0822d
DB
300 ret = sscanf(buf, "%u", &input);
301 if (ret != 1)
302 return -EINVAL;
303
d8f469e9
DB
304 limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);
305 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
93f0822d 306 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
845c1cbe 307
93f0822d
DB
308 return count;
309}
310
311static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
c410833a 312 const char *buf, size_t count)
93f0822d
DB
313{
314 unsigned int input;
315 int ret;
845c1cbe 316
93f0822d
DB
317 ret = sscanf(buf, "%u", &input);
318 if (ret != 1)
319 return -EINVAL;
320 limits.min_perf_pct = clamp_t(int, input, 0 , 100);
321 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
322
323 return count;
324}
325
326show_one(no_turbo, no_turbo);
327show_one(max_perf_pct, max_perf_pct);
328show_one(min_perf_pct, min_perf_pct);
329
330define_one_global_rw(no_turbo);
331define_one_global_rw(max_perf_pct);
332define_one_global_rw(min_perf_pct);
333
334static struct attribute *intel_pstate_attributes[] = {
335 &no_turbo.attr,
336 &max_perf_pct.attr,
337 &min_perf_pct.attr,
338 NULL
339};
340
341static struct attribute_group intel_pstate_attr_group = {
342 .attrs = intel_pstate_attributes,
343};
93f0822d 344
317dd50e 345static void __init intel_pstate_sysfs_expose_params(void)
93f0822d 346{
317dd50e 347 struct kobject *intel_pstate_kobject;
93f0822d
DB
348 int rc;
349
350 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
351 &cpu_subsys.dev_root->kobj);
352 BUG_ON(!intel_pstate_kobject);
2d8d1f18 353 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
93f0822d
DB
354 BUG_ON(rc);
355}
356
357/************************** sysfs end ************************/
19e77c28
DB
358static int byt_get_min_pstate(void)
359{
360 u64 value;
845c1cbe 361
19e77c28 362 rdmsrl(BYT_RATIOS, value);
c16ed060 363 return (value >> 8) & 0x7F;
19e77c28
DB
364}
365
366static int byt_get_max_pstate(void)
367{
368 u64 value;
845c1cbe 369
19e77c28 370 rdmsrl(BYT_RATIOS, value);
c16ed060 371 return (value >> 16) & 0x7F;
19e77c28 372}
93f0822d 373
61d8d2ab
DB
374static int byt_get_turbo_pstate(void)
375{
376 u64 value;
845c1cbe 377
61d8d2ab 378 rdmsrl(BYT_TURBO_RATIOS, value);
c16ed060 379 return value & 0x7F;
61d8d2ab
DB
380}
381
007bea09
DB
382static void byt_set_pstate(struct cpudata *cpudata, int pstate)
383{
384 u64 val;
385 int32_t vid_fp;
386 u32 vid;
387
388 val = pstate << 8;
dd5fbf70 389 if (limits.no_turbo && !limits.turbo_disabled)
007bea09
DB
390 val |= (u64)1 << 32;
391
392 vid_fp = cpudata->vid.min + mul_fp(
393 int_tofp(pstate - cpudata->pstate.min_pstate),
394 cpudata->vid.ratio);
395
396 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
397 vid = fp_toint(vid_fp);
398
21855ff5
DB
399 if (pstate > cpudata->pstate.max_pstate)
400 vid = cpudata->vid.turbo;
401
007bea09
DB
402 val |= vid;
403
404 wrmsrl(MSR_IA32_PERF_CTL, val);
405}
406
407static void byt_get_vid(struct cpudata *cpudata)
408{
409 u64 value;
410
411 rdmsrl(BYT_VIDS, value);
c16ed060
DB
412 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
413 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
007bea09
DB
414 cpudata->vid.ratio = div_fp(
415 cpudata->vid.max - cpudata->vid.min,
416 int_tofp(cpudata->pstate.max_pstate -
417 cpudata->pstate.min_pstate));
21855ff5
DB
418
419 rdmsrl(BYT_TURBO_VIDS, value);
420 cpudata->vid.turbo = value & 0x7f;
007bea09
DB
421}
422
016c8150 423static int core_get_min_pstate(void)
93f0822d
DB
424{
425 u64 value;
845c1cbe 426
05e99c8c 427 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB
428 return (value >> 40) & 0xFF;
429}
430
016c8150 431static int core_get_max_pstate(void)
93f0822d
DB
432{
433 u64 value;
845c1cbe 434
05e99c8c 435 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB
436 return (value >> 8) & 0xFF;
437}
438
016c8150 439static int core_get_turbo_pstate(void)
93f0822d
DB
440{
441 u64 value;
442 int nont, ret;
845c1cbe 443
05e99c8c 444 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
016c8150 445 nont = core_get_max_pstate();
285cb990 446 ret = (value) & 255;
93f0822d
DB
447 if (ret <= nont)
448 ret = nont;
449 return ret;
450}
451
007bea09 452static void core_set_pstate(struct cpudata *cpudata, int pstate)
016c8150
DB
453{
454 u64 val;
455
456 val = pstate << 8;
dd5fbf70 457 if (limits.no_turbo && !limits.turbo_disabled)
016c8150
DB
458 val |= (u64)1 << 32;
459
bb18008f 460 wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
016c8150
DB
461}
462
463static struct cpu_defaults core_params = {
464 .pid_policy = {
465 .sample_rate_ms = 10,
466 .deadband = 0,
467 .setpoint = 97,
468 .p_gain_pct = 20,
469 .d_gain_pct = 0,
470 .i_gain_pct = 0,
471 },
472 .funcs = {
473 .get_max = core_get_max_pstate,
474 .get_min = core_get_min_pstate,
475 .get_turbo = core_get_turbo_pstate,
476 .set = core_set_pstate,
477 },
478};
479
19e77c28
DB
480static struct cpu_defaults byt_params = {
481 .pid_policy = {
482 .sample_rate_ms = 10,
483 .deadband = 0,
484 .setpoint = 97,
485 .p_gain_pct = 14,
486 .d_gain_pct = 0,
487 .i_gain_pct = 4,
488 },
489 .funcs = {
490 .get_max = byt_get_max_pstate,
491 .get_min = byt_get_min_pstate,
61d8d2ab 492 .get_turbo = byt_get_turbo_pstate,
007bea09
DB
493 .set = byt_set_pstate,
494 .get_vid = byt_get_vid,
19e77c28
DB
495 },
496};
497
93f0822d
DB
498static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
499{
500 int max_perf = cpu->pstate.turbo_pstate;
7244cb62 501 int max_perf_adj;
93f0822d 502 int min_perf;
845c1cbe 503
93f0822d
DB
504 if (limits.no_turbo)
505 max_perf = cpu->pstate.max_pstate;
506
7244cb62
DB
507 max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
508 *max = clamp_t(int, max_perf_adj,
93f0822d
DB
509 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
510
511 min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
2d8d1f18 512 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
93f0822d
DB
513}
514
515static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
516{
517 int max_perf, min_perf;
518
519 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
520
521 pstate = clamp_t(int, pstate, min_perf, max_perf);
522
523 if (pstate == cpu->pstate.current_pstate)
524 return;
525
93f0822d 526 trace_cpu_frequency(pstate * 100000, cpu->cpu);
35363e94 527
93f0822d 528 cpu->pstate.current_pstate = pstate;
93f0822d 529
007bea09 530 pstate_funcs.set(cpu, pstate);
93f0822d
DB
531}
532
93f0822d
DB
533static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
534{
016c8150
DB
535 cpu->pstate.min_pstate = pstate_funcs.get_min();
536 cpu->pstate.max_pstate = pstate_funcs.get_max();
537 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
93f0822d 538
007bea09
DB
539 if (pstate_funcs.get_vid)
540 pstate_funcs.get_vid(cpu);
d40a63c4 541 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
93f0822d
DB
542}
543
6b17ddb2 544static inline void intel_pstate_calc_busy(struct cpudata *cpu)
93f0822d 545{
6b17ddb2 546 struct sample *sample = &cpu->sample;
bf810222 547 int64_t core_pct;
93f0822d 548
bf810222 549 core_pct = int_tofp(sample->aperf) * int_tofp(100);
78e27086 550 core_pct = div64_u64(core_pct, int_tofp(sample->mperf));
e66c1768 551
fcb6a15c 552 sample->freq = fp_toint(
e66c1768 553 mul_fp(int_tofp(cpu->pstate.max_pstate * 1000), core_pct));
fcb6a15c 554
bf810222 555 sample->core_pct_busy = (int32_t)core_pct;
93f0822d
DB
556}
557
558static inline void intel_pstate_sample(struct cpudata *cpu)
559{
93f0822d 560 u64 aperf, mperf;
4ab60c3f 561 unsigned long flags;
93f0822d 562
4ab60c3f 563 local_irq_save(flags);
93f0822d
DB
564 rdmsrl(MSR_IA32_APERF, aperf);
565 rdmsrl(MSR_IA32_MPERF, mperf);
4ab60c3f 566 local_irq_restore(flags);
b69880f9 567
c4ee841f
DB
568 cpu->last_sample_time = cpu->sample.time;
569 cpu->sample.time = ktime_get();
d37e2b76
DB
570 cpu->sample.aperf = aperf;
571 cpu->sample.mperf = mperf;
d37e2b76
DB
572 cpu->sample.aperf -= cpu->prev_aperf;
573 cpu->sample.mperf -= cpu->prev_mperf;
1abc4b20 574
6b17ddb2 575 intel_pstate_calc_busy(cpu);
93f0822d 576
93f0822d
DB
577 cpu->prev_aperf = aperf;
578 cpu->prev_mperf = mperf;
579}
580
581static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
582{
abf013bf 583 int delay;
93f0822d 584
abf013bf 585 delay = msecs_to_jiffies(pid_params.sample_rate_ms);
93f0822d
DB
586 mod_timer_pinned(&cpu->timer, jiffies + delay);
587}
588
d253d2a5 589static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
93f0822d 590{
c4ee841f
DB
591 int32_t core_busy, max_pstate, current_pstate, sample_ratio;
592 u32 duration_us;
593 u32 sample_time;
93f0822d 594
d37e2b76 595 core_busy = cpu->sample.core_pct_busy;
2134ed4d 596 max_pstate = int_tofp(cpu->pstate.max_pstate);
93f0822d 597 current_pstate = int_tofp(cpu->pstate.current_pstate);
e66c1768 598 core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
c4ee841f 599
285cb990 600 sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC;
c4ee841f 601 duration_us = (u32) ktime_us_delta(cpu->sample.time,
c410833a 602 cpu->last_sample_time);
c4ee841f
DB
603 if (duration_us > sample_time * 3) {
604 sample_ratio = div_fp(int_tofp(sample_time),
c410833a 605 int_tofp(duration_us));
c4ee841f
DB
606 core_busy = mul_fp(core_busy, sample_ratio);
607 }
608
f0fe3cd7 609 return core_busy;
93f0822d
DB
610}
611
612static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
613{
d253d2a5 614 int32_t busy_scaled;
93f0822d 615 struct _pid *pid;
4b707c89 616 signed int ctl;
93f0822d
DB
617
618 pid = &cpu->pid;
619 busy_scaled = intel_pstate_get_scaled_busy(cpu);
620
621 ctl = pid_calc(pid, busy_scaled);
622
4b707c89
SK
623 /* Negative values of ctl increase the pstate and vice versa */
624 intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl);
93f0822d
DB
625}
626
93f0822d
DB
627static void intel_pstate_timer_func(unsigned long __data)
628{
629 struct cpudata *cpu = (struct cpudata *) __data;
b69880f9 630 struct sample *sample;
93f0822d
DB
631
632 intel_pstate_sample(cpu);
b69880f9 633
d37e2b76 634 sample = &cpu->sample;
b69880f9 635
ca182aee 636 intel_pstate_adjust_busy_pstate(cpu);
b69880f9
DB
637
638 trace_pstate_sample(fp_toint(sample->core_pct_busy),
639 fp_toint(intel_pstate_get_scaled_busy(cpu)),
640 cpu->pstate.current_pstate,
641 sample->mperf,
642 sample->aperf,
b69880f9
DB
643 sample->freq);
644
93f0822d
DB
645 intel_pstate_set_sample_time(cpu);
646}
647
648#define ICPU(model, policy) \
6cbd7ee1
DB
649 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
650 (unsigned long)&policy }
93f0822d
DB
651
652static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
016c8150
DB
653 ICPU(0x2a, core_params),
654 ICPU(0x2d, core_params),
19e77c28 655 ICPU(0x37, byt_params),
016c8150
DB
656 ICPU(0x3a, core_params),
657 ICPU(0x3c, core_params),
c7e241df 658 ICPU(0x3d, core_params),
016c8150
DB
659 ICPU(0x3e, core_params),
660 ICPU(0x3f, core_params),
661 ICPU(0x45, core_params),
662 ICPU(0x46, core_params),
16405f98 663 ICPU(0x4c, byt_params),
c7e241df
DB
664 ICPU(0x4f, core_params),
665 ICPU(0x56, core_params),
93f0822d
DB
666 {}
667};
668MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
669
670static int intel_pstate_init_cpu(unsigned int cpunum)
671{
93f0822d
DB
672 struct cpudata *cpu;
673
93f0822d
DB
674 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL);
675 if (!all_cpu_data[cpunum])
676 return -ENOMEM;
677
678 cpu = all_cpu_data[cpunum];
679
93f0822d 680 cpu->cpu = cpunum;
179e8471 681 intel_pstate_get_cpu_pstates(cpu);
016c8150 682
93f0822d
DB
683 init_timer_deferrable(&cpu->timer);
684 cpu->timer.function = intel_pstate_timer_func;
2d8d1f18 685 cpu->timer.data = (unsigned long)cpu;
93f0822d
DB
686 cpu->timer.expires = jiffies + HZ/100;
687 intel_pstate_busy_pid_reset(cpu);
93f0822d 688 intel_pstate_sample(cpu);
93f0822d
DB
689
690 add_timer_on(&cpu->timer, cpunum);
691
ce717613 692 pr_debug("Intel pstate controlling: cpu %d\n", cpunum);
93f0822d
DB
693
694 return 0;
695}
696
697static unsigned int intel_pstate_get(unsigned int cpu_num)
698{
699 struct sample *sample;
700 struct cpudata *cpu;
701
702 cpu = all_cpu_data[cpu_num];
703 if (!cpu)
704 return 0;
d37e2b76 705 sample = &cpu->sample;
93f0822d
DB
706 return sample->freq;
707}
708
709static int intel_pstate_set_policy(struct cpufreq_policy *policy)
710{
d3929b83
DB
711 if (!policy->cpuinfo.max_freq)
712 return -ENODEV;
713
93f0822d
DB
714 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
715 limits.min_perf_pct = 100;
716 limits.min_perf = int_tofp(1);
36b4bed5 717 limits.max_policy_pct = 100;
93f0822d
DB
718 limits.max_perf_pct = 100;
719 limits.max_perf = int_tofp(1);
dd5fbf70 720 limits.no_turbo = limits.turbo_disabled;
d1b68485 721 return 0;
93f0822d 722 }
d1b68485
SP
723 limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
724 limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100);
725 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
726
285cb990 727 limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq;
d8f469e9
DB
728 limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);
729 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
d1b68485 730 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
93f0822d
DB
731
732 return 0;
733}
734
735static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
736{
be49e346 737 cpufreq_verify_within_cpu_limits(policy);
93f0822d 738
285cb990 739 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
c410833a 740 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
93f0822d
DB
741 return -EINVAL;
742
743 return 0;
744}
745
bb18008f 746static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 747{
bb18008f
DB
748 int cpu_num = policy->cpu;
749 struct cpudata *cpu = all_cpu_data[cpu_num];
93f0822d 750
bb18008f
DB
751 pr_info("intel_pstate CPU %d exiting\n", cpu_num);
752
c2294a2f 753 del_timer_sync(&all_cpu_data[cpu_num]->timer);
bb18008f
DB
754 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
755 kfree(all_cpu_data[cpu_num]);
756 all_cpu_data[cpu_num] = NULL;
93f0822d
DB
757}
758
2760984f 759static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 760{
93f0822d 761 struct cpudata *cpu;
52e0a509 762 int rc;
dd5fbf70 763 u64 misc_en;
93f0822d
DB
764
765 rc = intel_pstate_init_cpu(policy->cpu);
766 if (rc)
767 return rc;
768
769 cpu = all_cpu_data[policy->cpu];
770
dd5fbf70
DB
771 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
772 if (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
c410833a 773 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate) {
dd5fbf70
DB
774 limits.turbo_disabled = 1;
775 limits.no_turbo = 1;
776 }
777 if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100)
93f0822d
DB
778 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
779 else
780 policy->policy = CPUFREQ_POLICY_POWERSAVE;
781
52e0a509
DB
782 policy->min = cpu->pstate.min_pstate * 100000;
783 policy->max = cpu->pstate.turbo_pstate * 100000;
93f0822d
DB
784
785 /* cpuinfo and default policy values */
786 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000;
787 policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000;
788 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
789 cpumask_set_cpu(policy->cpu, policy->cpus);
790
791 return 0;
792}
793
794static struct cpufreq_driver intel_pstate_driver = {
795 .flags = CPUFREQ_CONST_LOOPS,
796 .verify = intel_pstate_verify_policy,
797 .setpolicy = intel_pstate_set_policy,
798 .get = intel_pstate_get,
799 .init = intel_pstate_cpu_init,
bb18008f 800 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 801 .name = "intel_pstate",
93f0822d
DB
802};
803
6be26498
DB
804static int __initdata no_load;
805
b563b4e3
DB
806static int intel_pstate_msrs_not_valid(void)
807{
808 /* Check that all the msr's we are using are valid. */
809 u64 aperf, mperf, tmp;
810
811 rdmsrl(MSR_IA32_APERF, aperf);
812 rdmsrl(MSR_IA32_MPERF, mperf);
813
016c8150 814 if (!pstate_funcs.get_max() ||
c410833a
SK
815 !pstate_funcs.get_min() ||
816 !pstate_funcs.get_turbo())
b563b4e3
DB
817 return -ENODEV;
818
819 rdmsrl(MSR_IA32_APERF, tmp);
820 if (!(tmp - aperf))
821 return -ENODEV;
822
823 rdmsrl(MSR_IA32_MPERF, tmp);
824 if (!(tmp - mperf))
825 return -ENODEV;
826
827 return 0;
828}
016c8150 829
e0a261a2 830static void copy_pid_params(struct pstate_adjust_policy *policy)
016c8150
DB
831{
832 pid_params.sample_rate_ms = policy->sample_rate_ms;
833 pid_params.p_gain_pct = policy->p_gain_pct;
834 pid_params.i_gain_pct = policy->i_gain_pct;
835 pid_params.d_gain_pct = policy->d_gain_pct;
836 pid_params.deadband = policy->deadband;
837 pid_params.setpoint = policy->setpoint;
838}
839
e0a261a2 840static void copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB
841{
842 pstate_funcs.get_max = funcs->get_max;
843 pstate_funcs.get_min = funcs->get_min;
844 pstate_funcs.get_turbo = funcs->get_turbo;
845 pstate_funcs.set = funcs->set;
007bea09 846 pstate_funcs.get_vid = funcs->get_vid;
016c8150
DB
847}
848
fbbcdc07
AH
849#if IS_ENABLED(CONFIG_ACPI)
850#include <acpi/processor.h>
851
852static bool intel_pstate_no_acpi_pss(void)
853{
854 int i;
855
856 for_each_possible_cpu(i) {
857 acpi_status status;
858 union acpi_object *pss;
859 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
860 struct acpi_processor *pr = per_cpu(processors, i);
861
862 if (!pr)
863 continue;
864
865 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
866 if (ACPI_FAILURE(status))
867 continue;
868
869 pss = buffer.pointer;
870 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
871 kfree(pss);
872 return false;
873 }
874
875 kfree(pss);
876 }
877
878 return true;
879}
880
881struct hw_vendor_info {
882 u16 valid;
883 char oem_id[ACPI_OEM_ID_SIZE];
884 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
885};
886
887/* Hardware vendor-specific info that has its own power management modes */
888static struct hw_vendor_info vendor_info[] = {
889 {1, "HP ", "ProLiant"},
890 {0, "", ""},
891};
892
893static bool intel_pstate_platform_pwr_mgmt_exists(void)
894{
895 struct acpi_table_header hdr;
896 struct hw_vendor_info *v_info;
897
c410833a
SK
898 if (acpi_disabled ||
899 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
fbbcdc07
AH
900 return false;
901
902 for (v_info = vendor_info; v_info->valid; v_info++) {
c410833a
SK
903 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
904 !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
905 intel_pstate_no_acpi_pss())
fbbcdc07
AH
906 return true;
907 }
908
909 return false;
910}
911#else /* CONFIG_ACPI not enabled */
912static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
913#endif /* CONFIG_ACPI */
914
93f0822d
DB
915static int __init intel_pstate_init(void)
916{
907cc908 917 int cpu, rc = 0;
93f0822d 918 const struct x86_cpu_id *id;
016c8150 919 struct cpu_defaults *cpu_info;
93f0822d 920
6be26498
DB
921 if (no_load)
922 return -ENODEV;
923
93f0822d
DB
924 id = x86_match_cpu(intel_pstate_cpu_ids);
925 if (!id)
926 return -ENODEV;
927
fbbcdc07
AH
928 /*
929 * The Intel pstate driver will be ignored if the platform
930 * firmware has its own power management modes.
931 */
932 if (intel_pstate_platform_pwr_mgmt_exists())
933 return -ENODEV;
934
016c8150
DB
935 cpu_info = (struct cpu_defaults *)id->driver_data;
936
937 copy_pid_params(&cpu_info->pid_policy);
938 copy_cpu_funcs(&cpu_info->funcs);
939
b563b4e3
DB
940 if (intel_pstate_msrs_not_valid())
941 return -ENODEV;
942
93f0822d
DB
943 pr_info("Intel P-state driver initializing.\n");
944
b57ffac5 945 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
93f0822d
DB
946 if (!all_cpu_data)
947 return -ENOMEM;
93f0822d
DB
948
949 rc = cpufreq_register_driver(&intel_pstate_driver);
950 if (rc)
951 goto out;
952
953 intel_pstate_debug_expose_params();
954 intel_pstate_sysfs_expose_params();
b69880f9 955
93f0822d
DB
956 return rc;
957out:
907cc908
DB
958 get_online_cpus();
959 for_each_online_cpu(cpu) {
960 if (all_cpu_data[cpu]) {
961 del_timer_sync(&all_cpu_data[cpu]->timer);
962 kfree(all_cpu_data[cpu]);
963 }
964 }
965
966 put_online_cpus();
967 vfree(all_cpu_data);
93f0822d
DB
968 return -ENODEV;
969}
970device_initcall(intel_pstate_init);
971
6be26498
DB
972static int __init intel_pstate_setup(char *str)
973{
974 if (!str)
975 return -EINVAL;
976
977 if (!strcmp(str, "disable"))
978 no_load = 1;
979 return 0;
980}
981early_param("intel_pstate", intel_pstate_setup);
982
93f0822d
DB
983MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
984MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
985MODULE_LICENSE("GPL");
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