Commit | Line | Data |
---|---|---|
ec6bced6 | 1 | /* |
ffe4f0f1 | 2 | * CPU frequency scaling for OMAP using OPP information |
ec6bced6 TL |
3 | * |
4 | * Copyright (C) 2005 Nokia Corporation | |
5 | * Written by Tony Lindgren <tony@atomide.com> | |
6 | * | |
7 | * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King | |
8 | * | |
731e0cc6 SS |
9 | * Copyright (C) 2007-2011 Texas Instruments, Inc. |
10 | * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar | |
11 | * | |
ec6bced6 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/cpufreq.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/err.h> | |
f8ce2547 | 23 | #include <linux/clk.h> |
fced80c7 | 24 | #include <linux/io.h> |
731e0cc6 | 25 | #include <linux/opp.h> |
46c12216 | 26 | #include <linux/cpu.h> |
c1b547bc | 27 | #include <linux/module.h> |
49ded525 | 28 | #include <linux/platform_device.h> |
53dfe8a8 | 29 | #include <linux/regulator/consumer.h> |
ec6bced6 | 30 | |
731e0cc6 | 31 | #include <asm/smp_plat.h> |
46c12216 | 32 | #include <asm/cpu.h> |
ec6bced6 | 33 | |
42daffd2 AM |
34 | /* OPP tolerance in percentage */ |
35 | #define OPP_TOLERANCE 4 | |
36 | ||
731e0cc6 | 37 | static struct cpufreq_frequency_table *freq_table; |
1c78217f | 38 | static atomic_t freq_table_users = ATOMIC_INIT(0); |
b8488fbe | 39 | static struct clk *mpu_clk; |
a820ffa8 | 40 | static struct device *mpu_dev; |
53dfe8a8 | 41 | static struct regulator *mpu_reg; |
b8488fbe | 42 | |
b0a330dc | 43 | static int omap_verify_speed(struct cpufreq_policy *policy) |
ec6bced6 | 44 | { |
bf2a359d | 45 | if (!freq_table) |
ec6bced6 | 46 | return -EINVAL; |
bf2a359d | 47 | return cpufreq_frequency_table_verify(policy, freq_table); |
ec6bced6 TL |
48 | } |
49 | ||
b0a330dc | 50 | static unsigned int omap_getspeed(unsigned int cpu) |
ec6bced6 | 51 | { |
ec6bced6 TL |
52 | unsigned long rate; |
53 | ||
46c12216 | 54 | if (cpu >= NR_CPUS) |
ec6bced6 TL |
55 | return 0; |
56 | ||
ec6bced6 | 57 | rate = clk_get_rate(mpu_clk) / 1000; |
ec6bced6 TL |
58 | return rate; |
59 | } | |
60 | ||
61 | static int omap_target(struct cpufreq_policy *policy, | |
62 | unsigned int target_freq, | |
63 | unsigned int relation) | |
64 | { | |
bf2a359d | 65 | unsigned int i; |
53dfe8a8 | 66 | int r, ret = 0; |
731e0cc6 | 67 | struct cpufreq_freqs freqs; |
53dfe8a8 | 68 | struct opp *opp; |
42daffd2 | 69 | unsigned long freq, volt = 0, volt_old = 0, tol = 0; |
ec6bced6 | 70 | |
bf2a359d NM |
71 | if (!freq_table) { |
72 | dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__, | |
73 | policy->cpu); | |
74 | return -EINVAL; | |
75 | } | |
76 | ||
77 | ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, | |
78 | relation, &i); | |
79 | if (ret) { | |
80 | dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n", | |
81 | __func__, policy->cpu, target_freq, ret); | |
82 | return ret; | |
83 | } | |
84 | freqs.new = freq_table[i].frequency; | |
85 | if (!freqs.new) { | |
86 | dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__, | |
87 | policy->cpu, target_freq); | |
88 | return -EINVAL; | |
89 | } | |
aeec2990 | 90 | |
46c12216 | 91 | freqs.old = omap_getspeed(policy->cpu); |
ec6bced6 | 92 | |
022ac03b | 93 | if (freqs.old == freqs.new && policy->cur == freqs.new) |
aeec2990 KH |
94 | return ret; |
95 | ||
53dfe8a8 | 96 | freq = freqs.new * 1000; |
8df0a663 KH |
97 | ret = clk_round_rate(mpu_clk, freq); |
98 | if (IS_ERR_VALUE(ret)) { | |
99 | dev_warn(mpu_dev, | |
100 | "CPUfreq: Cannot find matching frequency for %lu\n", | |
101 | freq); | |
102 | return ret; | |
103 | } | |
104 | freq = ret; | |
53dfe8a8 KH |
105 | |
106 | if (mpu_reg) { | |
f44d188a | 107 | rcu_read_lock(); |
53dfe8a8 KH |
108 | opp = opp_find_freq_ceil(mpu_dev, &freq); |
109 | if (IS_ERR(opp)) { | |
f44d188a | 110 | rcu_read_unlock(); |
53dfe8a8 KH |
111 | dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n", |
112 | __func__, freqs.new); | |
113 | return -EINVAL; | |
114 | } | |
115 | volt = opp_get_voltage(opp); | |
f44d188a | 116 | rcu_read_unlock(); |
42daffd2 | 117 | tol = volt * OPP_TOLERANCE / 100; |
53dfe8a8 KH |
118 | volt_old = regulator_get_voltage(mpu_reg); |
119 | } | |
120 | ||
121 | dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n", | |
122 | freqs.old / 1000, volt_old ? volt_old / 1000 : -1, | |
123 | freqs.new / 1000, volt ? volt / 1000 : -1); | |
124 | ||
44a49a23 VK |
125 | /* notifiers */ |
126 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); | |
127 | ||
53dfe8a8 KH |
128 | /* scaling up? scale voltage before frequency */ |
129 | if (mpu_reg && (freqs.new > freqs.old)) { | |
42daffd2 | 130 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
131 | if (r < 0) { |
132 | dev_warn(mpu_dev, "%s: unable to scale voltage up.\n", | |
133 | __func__); | |
134 | freqs.new = freqs.old; | |
135 | goto done; | |
136 | } | |
137 | } | |
731e0cc6 | 138 | |
aeec2990 | 139 | ret = clk_set_rate(mpu_clk, freqs.new * 1000); |
46c12216 | 140 | |
53dfe8a8 KH |
141 | /* scaling down? scale voltage after frequency */ |
142 | if (mpu_reg && (freqs.new < freqs.old)) { | |
42daffd2 | 143 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
144 | if (r < 0) { |
145 | dev_warn(mpu_dev, "%s: unable to scale voltage down.\n", | |
146 | __func__); | |
147 | ret = clk_set_rate(mpu_clk, freqs.old * 1000); | |
148 | freqs.new = freqs.old; | |
149 | goto done; | |
150 | } | |
151 | } | |
152 | ||
153 | freqs.new = omap_getspeed(policy->cpu); | |
46c12216 | 154 | |
53dfe8a8 | 155 | done: |
46c12216 | 156 | /* notifiers */ |
b43a7ffb | 157 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); |
ec6bced6 TL |
158 | |
159 | return ret; | |
160 | } | |
161 | ||
1c78217f NM |
162 | static inline void freq_table_free(void) |
163 | { | |
164 | if (atomic_dec_and_test(&freq_table_users)) | |
165 | opp_free_cpufreq_table(mpu_dev, &freq_table); | |
166 | } | |
167 | ||
2760984f | 168 | static int omap_cpu_init(struct cpufreq_policy *policy) |
ec6bced6 | 169 | { |
aeec2990 | 170 | int result = 0; |
731e0cc6 | 171 | |
e2ee1b4d | 172 | mpu_clk = clk_get(NULL, "cpufreq_ck"); |
ec6bced6 TL |
173 | if (IS_ERR(mpu_clk)) |
174 | return PTR_ERR(mpu_clk); | |
175 | ||
11e04fdd NM |
176 | if (policy->cpu >= NR_CPUS) { |
177 | result = -EINVAL; | |
178 | goto fail_ck; | |
179 | } | |
aeec2990 | 180 | |
eb2f50ff | 181 | policy->cur = omap_getspeed(policy->cpu); |
1c78217f | 182 | |
1b865214 | 183 | if (!freq_table) |
1c78217f | 184 | result = opp_init_cpufreq_table(mpu_dev, &freq_table); |
bf2a359d NM |
185 | |
186 | if (result) { | |
187 | dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n", | |
188 | __func__, policy->cpu, result); | |
11e04fdd | 189 | goto fail_ck; |
aeec2990 KH |
190 | } |
191 | ||
1b865214 RN |
192 | atomic_inc_return(&freq_table_users); |
193 | ||
bf2a359d | 194 | result = cpufreq_frequency_table_cpuinfo(policy, freq_table); |
1c78217f NM |
195 | if (result) |
196 | goto fail_table; | |
197 | ||
198 | cpufreq_frequency_table_get_attr(freq_table, policy->cpu); | |
bf2a359d | 199 | |
46c12216 RK |
200 | policy->cur = omap_getspeed(policy->cpu); |
201 | ||
202 | /* | |
203 | * On OMAP SMP configuartion, both processors share the voltage | |
204 | * and clock. So both CPUs needs to be scaled together and hence | |
205 | * needs software co-ordination. Use cpufreq affected_cpus | |
206 | * interface to handle this scenario. Additional is_smp() check | |
207 | * is to keep SMP_ON_UP build working. | |
208 | */ | |
62b36cc1 | 209 | if (is_smp()) |
ed8ce00c | 210 | cpumask_setall(policy->cpus); |
731e0cc6 | 211 | |
aeec2990 | 212 | /* FIXME: what's the actual transition time? */ |
b029839c | 213 | policy->cpuinfo.transition_latency = 300 * 1000; |
ec6bced6 TL |
214 | |
215 | return 0; | |
11e04fdd | 216 | |
1c78217f NM |
217 | fail_table: |
218 | freq_table_free(); | |
11e04fdd NM |
219 | fail_ck: |
220 | clk_put(mpu_clk); | |
221 | return result; | |
ec6bced6 TL |
222 | } |
223 | ||
b8488fbe HD |
224 | static int omap_cpu_exit(struct cpufreq_policy *policy) |
225 | { | |
1c78217f | 226 | freq_table_free(); |
b8488fbe HD |
227 | clk_put(mpu_clk); |
228 | return 0; | |
229 | } | |
230 | ||
aeec2990 KH |
231 | static struct freq_attr *omap_cpufreq_attr[] = { |
232 | &cpufreq_freq_attr_scaling_available_freqs, | |
233 | NULL, | |
234 | }; | |
235 | ||
ec6bced6 TL |
236 | static struct cpufreq_driver omap_driver = { |
237 | .flags = CPUFREQ_STICKY, | |
238 | .verify = omap_verify_speed, | |
239 | .target = omap_target, | |
240 | .get = omap_getspeed, | |
241 | .init = omap_cpu_init, | |
b8488fbe | 242 | .exit = omap_cpu_exit, |
ec6bced6 | 243 | .name = "omap", |
aeec2990 | 244 | .attr = omap_cpufreq_attr, |
ec6bced6 TL |
245 | }; |
246 | ||
49ded525 | 247 | static int omap_cpufreq_probe(struct platform_device *pdev) |
ec6bced6 | 248 | { |
747a7f64 KH |
249 | mpu_dev = get_cpu_device(0); |
250 | if (!mpu_dev) { | |
a820ffa8 | 251 | pr_warning("%s: unable to get the mpu device\n", __func__); |
747a7f64 | 252 | return -EINVAL; |
a820ffa8 NM |
253 | } |
254 | ||
53dfe8a8 KH |
255 | mpu_reg = regulator_get(mpu_dev, "vcc"); |
256 | if (IS_ERR(mpu_reg)) { | |
257 | pr_warning("%s: unable to get MPU regulator\n", __func__); | |
258 | mpu_reg = NULL; | |
259 | } else { | |
260 | /* | |
261 | * Ensure physical regulator is present. | |
262 | * (e.g. could be dummy regulator.) | |
263 | */ | |
264 | if (regulator_get_voltage(mpu_reg) < 0) { | |
265 | pr_warn("%s: physical regulator not present for MPU\n", | |
266 | __func__); | |
267 | regulator_put(mpu_reg); | |
268 | mpu_reg = NULL; | |
269 | } | |
270 | } | |
271 | ||
ec6bced6 TL |
272 | return cpufreq_register_driver(&omap_driver); |
273 | } | |
274 | ||
49ded525 | 275 | static int omap_cpufreq_remove(struct platform_device *pdev) |
731e0cc6 | 276 | { |
49ded525 | 277 | return cpufreq_unregister_driver(&omap_driver); |
731e0cc6 | 278 | } |
aeec2990 | 279 | |
49ded525 NM |
280 | static struct platform_driver omap_cpufreq_platdrv = { |
281 | .driver = { | |
282 | .name = "omap-cpufreq", | |
283 | .owner = THIS_MODULE, | |
284 | }, | |
285 | .probe = omap_cpufreq_probe, | |
286 | .remove = omap_cpufreq_remove, | |
287 | }; | |
288 | module_platform_driver(omap_cpufreq_platdrv); | |
289 | ||
731e0cc6 SS |
290 | MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs"); |
291 | MODULE_LICENSE("GPL"); |