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1da177e4 LT |
1 | /* us2e_cpufreq.c: UltraSPARC-IIe cpu frequency support |
2 | * | |
3 | * Copyright (C) 2003 David S. Miller (davem@redhat.com) | |
4 | * | |
5 | * Many thanks to Dominik Brodowski for fixing up the cpufreq | |
6 | * infrastructure in order to make this driver easier to implement. | |
7 | */ | |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/smp.h> | |
13 | #include <linux/cpufreq.h> | |
14 | #include <linux/threads.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/init.h> | |
18 | ||
19 | #include <asm/asi.h> | |
20 | #include <asm/timer.h> | |
21 | ||
22 | static struct cpufreq_driver *cpufreq_us2e_driver; | |
23 | ||
24 | struct us2e_freq_percpu_info { | |
25 | struct cpufreq_frequency_table table[6]; | |
26 | }; | |
27 | ||
28 | /* Indexed by cpu number. */ | |
29 | static struct us2e_freq_percpu_info *us2e_freq_table; | |
30 | ||
31 | #define HBIRD_MEM_CNTL0_ADDR 0x1fe0000f010UL | |
32 | #define HBIRD_ESTAR_MODE_ADDR 0x1fe0000f080UL | |
33 | ||
34 | /* UltraSPARC-IIe has five dividers: 1, 2, 4, 6, and 8. These are controlled | |
35 | * in the ESTAR mode control register. | |
36 | */ | |
37 | #define ESTAR_MODE_DIV_1 0x0000000000000000UL | |
38 | #define ESTAR_MODE_DIV_2 0x0000000000000001UL | |
39 | #define ESTAR_MODE_DIV_4 0x0000000000000003UL | |
40 | #define ESTAR_MODE_DIV_6 0x0000000000000002UL | |
41 | #define ESTAR_MODE_DIV_8 0x0000000000000004UL | |
42 | #define ESTAR_MODE_DIV_MASK 0x0000000000000007UL | |
43 | ||
44 | #define MCTRL0_SREFRESH_ENAB 0x0000000000010000UL | |
45 | #define MCTRL0_REFR_COUNT_MASK 0x0000000000007f00UL | |
46 | #define MCTRL0_REFR_COUNT_SHIFT 8 | |
47 | #define MCTRL0_REFR_INTERVAL 7800 | |
48 | #define MCTRL0_REFR_CLKS_P_CNT 64 | |
49 | ||
50 | static unsigned long read_hbreg(unsigned long addr) | |
51 | { | |
52 | unsigned long ret; | |
53 | ||
54 | __asm__ __volatile__("ldxa [%1] %2, %0" | |
55 | : "=&r" (ret) | |
56 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | |
57 | return ret; | |
58 | } | |
59 | ||
60 | static void write_hbreg(unsigned long addr, unsigned long val) | |
61 | { | |
62 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
63 | "membar #Sync" | |
64 | : /* no outputs */ | |
65 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E) | |
66 | : "memory"); | |
67 | if (addr == HBIRD_ESTAR_MODE_ADDR) { | |
68 | /* Need to wait 16 clock cycles for the PLL to lock. */ | |
69 | udelay(1); | |
70 | } | |
71 | } | |
72 | ||
73 | static void self_refresh_ctl(int enable) | |
74 | { | |
75 | unsigned long mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR); | |
76 | ||
77 | if (enable) | |
78 | mctrl |= MCTRL0_SREFRESH_ENAB; | |
79 | else | |
80 | mctrl &= ~MCTRL0_SREFRESH_ENAB; | |
81 | write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl); | |
82 | (void) read_hbreg(HBIRD_MEM_CNTL0_ADDR); | |
83 | } | |
84 | ||
85 | static void frob_mem_refresh(int cpu_slowing_down, | |
86 | unsigned long clock_tick, | |
87 | unsigned long old_divisor, unsigned long divisor) | |
88 | { | |
89 | unsigned long old_refr_count, refr_count, mctrl; | |
90 | ||
1da177e4 LT |
91 | refr_count = (clock_tick * MCTRL0_REFR_INTERVAL); |
92 | refr_count /= (MCTRL0_REFR_CLKS_P_CNT * divisor * 1000000000UL); | |
93 | ||
94 | mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR); | |
95 | old_refr_count = (mctrl & MCTRL0_REFR_COUNT_MASK) | |
96 | >> MCTRL0_REFR_COUNT_SHIFT; | |
97 | ||
98 | mctrl &= ~MCTRL0_REFR_COUNT_MASK; | |
99 | mctrl |= refr_count << MCTRL0_REFR_COUNT_SHIFT; | |
100 | write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl); | |
101 | mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR); | |
102 | ||
103 | if (cpu_slowing_down && !(mctrl & MCTRL0_SREFRESH_ENAB)) { | |
104 | unsigned long usecs; | |
105 | ||
106 | /* We have to wait for both refresh counts (old | |
107 | * and new) to go to zero. | |
108 | */ | |
109 | usecs = (MCTRL0_REFR_CLKS_P_CNT * | |
110 | (refr_count + old_refr_count) * | |
111 | 1000000UL * | |
112 | old_divisor) / clock_tick; | |
113 | udelay(usecs + 1UL); | |
114 | } | |
115 | } | |
116 | ||
117 | static void us2e_transition(unsigned long estar, unsigned long new_bits, | |
118 | unsigned long clock_tick, | |
119 | unsigned long old_divisor, unsigned long divisor) | |
120 | { | |
121 | unsigned long flags; | |
122 | ||
123 | local_irq_save(flags); | |
124 | ||
125 | estar &= ~ESTAR_MODE_DIV_MASK; | |
126 | ||
127 | /* This is based upon the state transition diagram in the IIe manual. */ | |
128 | if (old_divisor == 2 && divisor == 1) { | |
129 | self_refresh_ctl(0); | |
130 | write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits); | |
131 | frob_mem_refresh(0, clock_tick, old_divisor, divisor); | |
132 | } else if (old_divisor == 1 && divisor == 2) { | |
133 | frob_mem_refresh(1, clock_tick, old_divisor, divisor); | |
134 | write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits); | |
135 | self_refresh_ctl(1); | |
136 | } else if (old_divisor == 1 && divisor > 2) { | |
137 | us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick, | |
138 | 1, 2); | |
139 | us2e_transition(estar, new_bits, clock_tick, | |
140 | 2, divisor); | |
141 | } else if (old_divisor > 2 && divisor == 1) { | |
142 | us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick, | |
143 | old_divisor, 2); | |
144 | us2e_transition(estar, new_bits, clock_tick, | |
145 | 2, divisor); | |
146 | } else if (old_divisor < divisor) { | |
147 | frob_mem_refresh(0, clock_tick, old_divisor, divisor); | |
148 | write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits); | |
149 | } else if (old_divisor > divisor) { | |
150 | write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits); | |
151 | frob_mem_refresh(1, clock_tick, old_divisor, divisor); | |
152 | } else { | |
153 | BUG(); | |
154 | } | |
155 | ||
156 | local_irq_restore(flags); | |
157 | } | |
158 | ||
159 | static unsigned long index_to_estar_mode(unsigned int index) | |
160 | { | |
161 | switch (index) { | |
162 | case 0: | |
163 | return ESTAR_MODE_DIV_1; | |
164 | ||
165 | case 1: | |
166 | return ESTAR_MODE_DIV_2; | |
167 | ||
168 | case 2: | |
169 | return ESTAR_MODE_DIV_4; | |
170 | ||
171 | case 3: | |
172 | return ESTAR_MODE_DIV_6; | |
173 | ||
174 | case 4: | |
175 | return ESTAR_MODE_DIV_8; | |
176 | ||
177 | default: | |
178 | BUG(); | |
6cb79b3f | 179 | } |
1da177e4 LT |
180 | } |
181 | ||
182 | static unsigned long index_to_divisor(unsigned int index) | |
183 | { | |
184 | switch (index) { | |
185 | case 0: | |
186 | return 1; | |
187 | ||
188 | case 1: | |
189 | return 2; | |
190 | ||
191 | case 2: | |
192 | return 4; | |
193 | ||
194 | case 3: | |
195 | return 6; | |
196 | ||
197 | case 4: | |
198 | return 8; | |
199 | ||
200 | default: | |
201 | BUG(); | |
6cb79b3f | 202 | } |
1da177e4 LT |
203 | } |
204 | ||
205 | static unsigned long estar_to_divisor(unsigned long estar) | |
206 | { | |
207 | unsigned long ret; | |
208 | ||
209 | switch (estar & ESTAR_MODE_DIV_MASK) { | |
210 | case ESTAR_MODE_DIV_1: | |
211 | ret = 1; | |
212 | break; | |
213 | case ESTAR_MODE_DIV_2: | |
214 | ret = 2; | |
215 | break; | |
216 | case ESTAR_MODE_DIV_4: | |
217 | ret = 4; | |
218 | break; | |
219 | case ESTAR_MODE_DIV_6: | |
220 | ret = 6; | |
221 | break; | |
222 | case ESTAR_MODE_DIV_8: | |
223 | ret = 8; | |
224 | break; | |
225 | default: | |
226 | BUG(); | |
6cb79b3f | 227 | } |
1da177e4 LT |
228 | |
229 | return ret; | |
230 | } | |
231 | ||
2cab224d DM |
232 | static unsigned int us2e_freq_get(unsigned int cpu) |
233 | { | |
234 | cpumask_t cpus_allowed; | |
235 | unsigned long clock_tick, estar; | |
236 | ||
fb1fece5 | 237 | cpumask_copy(&cpus_allowed, tsk_cpus_allowed(current)); |
d2566af8 | 238 | set_cpus_allowed_ptr(current, cpumask_of(cpu)); |
2cab224d DM |
239 | |
240 | clock_tick = sparc64_get_clock_tick(cpu) / 1000; | |
241 | estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR); | |
242 | ||
d2566af8 | 243 | set_cpus_allowed_ptr(current, &cpus_allowed); |
2cab224d DM |
244 | |
245 | return clock_tick / estar_to_divisor(estar); | |
246 | } | |
247 | ||
b43a7ffb VK |
248 | static void us2e_set_cpu_divider_index(struct cpufreq_policy *policy, |
249 | unsigned int index) | |
1da177e4 | 250 | { |
b43a7ffb | 251 | unsigned int cpu = policy->cpu; |
1da177e4 LT |
252 | unsigned long new_bits, new_freq; |
253 | unsigned long clock_tick, divisor, old_divisor, estar; | |
254 | cpumask_t cpus_allowed; | |
255 | struct cpufreq_freqs freqs; | |
256 | ||
fb1fece5 | 257 | cpumask_copy(&cpus_allowed, tsk_cpus_allowed(current)); |
d2566af8 | 258 | set_cpus_allowed_ptr(current, cpumask_of(cpu)); |
1da177e4 | 259 | |
2cab224d | 260 | new_freq = clock_tick = sparc64_get_clock_tick(cpu) / 1000; |
1da177e4 LT |
261 | new_bits = index_to_estar_mode(index); |
262 | divisor = index_to_divisor(index); | |
263 | new_freq /= divisor; | |
264 | ||
265 | estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR); | |
266 | ||
267 | old_divisor = estar_to_divisor(estar); | |
268 | ||
269 | freqs.old = clock_tick / old_divisor; | |
270 | freqs.new = new_freq; | |
b43a7ffb | 271 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); |
1da177e4 LT |
272 | |
273 | if (old_divisor != divisor) | |
2cab224d DM |
274 | us2e_transition(estar, new_bits, clock_tick * 1000, |
275 | old_divisor, divisor); | |
1da177e4 | 276 | |
b43a7ffb | 277 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); |
1da177e4 | 278 | |
d2566af8 | 279 | set_cpus_allowed_ptr(current, &cpus_allowed); |
1da177e4 LT |
280 | } |
281 | ||
282 | static int us2e_freq_target(struct cpufreq_policy *policy, | |
283 | unsigned int target_freq, | |
284 | unsigned int relation) | |
285 | { | |
286 | unsigned int new_index = 0; | |
287 | ||
288 | if (cpufreq_frequency_table_target(policy, | |
2cab224d DM |
289 | &us2e_freq_table[policy->cpu].table[0], |
290 | target_freq, relation, &new_index)) | |
1da177e4 LT |
291 | return -EINVAL; |
292 | ||
b43a7ffb | 293 | us2e_set_cpu_divider_index(policy, new_index); |
1da177e4 LT |
294 | |
295 | return 0; | |
296 | } | |
297 | ||
298 | static int us2e_freq_verify(struct cpufreq_policy *policy) | |
299 | { | |
300 | return cpufreq_frequency_table_verify(policy, | |
301 | &us2e_freq_table[policy->cpu].table[0]); | |
302 | } | |
303 | ||
304 | static int __init us2e_freq_cpu_init(struct cpufreq_policy *policy) | |
305 | { | |
306 | unsigned int cpu = policy->cpu; | |
2cab224d | 307 | unsigned long clock_tick = sparc64_get_clock_tick(cpu) / 1000; |
1da177e4 LT |
308 | struct cpufreq_frequency_table *table = |
309 | &us2e_freq_table[cpu].table[0]; | |
18f130ed | 310 | int ret; |
1da177e4 | 311 | |
50701588 | 312 | table[0].driver_data = 0; |
1da177e4 | 313 | table[0].frequency = clock_tick / 1; |
50701588 | 314 | table[1].driver_data = 1; |
1da177e4 | 315 | table[1].frequency = clock_tick / 2; |
50701588 | 316 | table[2].driver_data = 2; |
1da177e4 | 317 | table[2].frequency = clock_tick / 4; |
50701588 | 318 | table[2].driver_data = 3; |
1da177e4 | 319 | table[2].frequency = clock_tick / 6; |
50701588 | 320 | table[2].driver_data = 4; |
1da177e4 | 321 | table[2].frequency = clock_tick / 8; |
50701588 | 322 | table[2].driver_data = 5; |
1da177e4 LT |
323 | table[3].frequency = CPUFREQ_TABLE_END; |
324 | ||
1da177e4 LT |
325 | policy->cpuinfo.transition_latency = 0; |
326 | policy->cur = clock_tick; | |
327 | ||
18f130ed VK |
328 | ret = cpufreq_frequency_table_cpuinfo(policy, table); |
329 | if (!ret) | |
330 | cpufreq_frequency_table_get_attr(table, policy->cpu); | |
331 | return ret; | |
1da177e4 LT |
332 | } |
333 | ||
334 | static int us2e_freq_cpu_exit(struct cpufreq_policy *policy) | |
335 | { | |
18f130ed VK |
336 | if (cpufreq_us2e_driver) { |
337 | cpufreq_frequency_table_put_attr(policy->cpu); | |
b43a7ffb | 338 | us2e_set_cpu_divider_index(policy, 0); |
18f130ed | 339 | } |
1da177e4 LT |
340 | |
341 | return 0; | |
342 | } | |
343 | ||
344 | static int __init us2e_freq_init(void) | |
345 | { | |
346 | unsigned long manuf, impl, ver; | |
347 | int ret; | |
348 | ||
d82ace7d DM |
349 | if (tlb_type != spitfire) |
350 | return -ENODEV; | |
351 | ||
1da177e4 LT |
352 | __asm__("rdpr %%ver, %0" : "=r" (ver)); |
353 | manuf = ((ver >> 48) & 0xffff); | |
354 | impl = ((ver >> 32) & 0xffff); | |
355 | ||
356 | if (manuf == 0x17 && impl == 0x13) { | |
357 | struct cpufreq_driver *driver; | |
358 | ||
359 | ret = -ENOMEM; | |
d5b73cd8 | 360 | driver = kzalloc(sizeof(*driver), GFP_KERNEL); |
1da177e4 LT |
361 | if (!driver) |
362 | goto err_out; | |
1da177e4 | 363 | |
d5b73cd8 | 364 | us2e_freq_table = kzalloc((NR_CPUS * sizeof(*us2e_freq_table)), |
1da177e4 LT |
365 | GFP_KERNEL); |
366 | if (!us2e_freq_table) | |
367 | goto err_out; | |
368 | ||
2cab224d | 369 | driver->init = us2e_freq_cpu_init; |
1da177e4 LT |
370 | driver->verify = us2e_freq_verify; |
371 | driver->target = us2e_freq_target; | |
2cab224d | 372 | driver->get = us2e_freq_get; |
1da177e4 | 373 | driver->exit = us2e_freq_cpu_exit; |
1da177e4 LT |
374 | strcpy(driver->name, "UltraSPARC-IIe"); |
375 | ||
376 | cpufreq_us2e_driver = driver; | |
377 | ret = cpufreq_register_driver(driver); | |
378 | if (ret) | |
379 | goto err_out; | |
380 | ||
381 | return 0; | |
382 | ||
383 | err_out: | |
384 | if (driver) { | |
385 | kfree(driver); | |
386 | cpufreq_us2e_driver = NULL; | |
387 | } | |
b2325fe1 JJ |
388 | kfree(us2e_freq_table); |
389 | us2e_freq_table = NULL; | |
1da177e4 LT |
390 | return ret; |
391 | } | |
392 | ||
393 | return -ENODEV; | |
394 | } | |
395 | ||
396 | static void __exit us2e_freq_exit(void) | |
397 | { | |
398 | if (cpufreq_us2e_driver) { | |
399 | cpufreq_unregister_driver(cpufreq_us2e_driver); | |
1da177e4 LT |
400 | kfree(cpufreq_us2e_driver); |
401 | cpufreq_us2e_driver = NULL; | |
402 | kfree(us2e_freq_table); | |
403 | us2e_freq_table = NULL; | |
404 | } | |
405 | } | |
406 | ||
407 | MODULE_AUTHOR("David S. Miller <davem@redhat.com>"); | |
408 | MODULE_DESCRIPTION("cpufreq driver for UltraSPARC-IIe"); | |
409 | MODULE_LICENSE("GPL"); | |
410 | ||
411 | module_init(us2e_freq_init); | |
412 | module_exit(us2e_freq_exit); |