Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium | |
3 | * M (part of the Centrino chipset). | |
4 | * | |
491b07c9 JF |
5 | * Since the original Pentium M, most new Intel CPUs support Enhanced |
6 | * SpeedStep. | |
7 | * | |
1da177e4 LT |
8 | * Despite the "SpeedStep" in the name, this is almost entirely unlike |
9 | * traditional SpeedStep. | |
10 | * | |
11 | * Modelled on speedstep.c | |
12 | * | |
13 | * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org> | |
1da177e4 LT |
14 | */ |
15 | ||
1c5864e2 JP |
16 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
17 | ||
1da177e4 LT |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/cpufreq.h> | |
4e57b681 | 22 | #include <linux/sched.h> /* current */ |
1da177e4 LT |
23 | #include <linux/delay.h> |
24 | #include <linux/compiler.h> | |
5a0e3ad6 | 25 | #include <linux/gfp.h> |
1da177e4 | 26 | |
1da177e4 LT |
27 | #include <asm/msr.h> |
28 | #include <asm/processor.h> | |
29 | #include <asm/cpufeature.h> | |
fa8031ae | 30 | #include <asm/cpu_device_id.h> |
1da177e4 | 31 | |
dec102aa | 32 | #define MAINTAINER "linux-pm@vger.kernel.org" |
1da177e4 | 33 | |
8b9c6671 | 34 | #define INTEL_MSR_RANGE (0xffff) |
1da177e4 LT |
35 | |
36 | struct cpu_id | |
37 | { | |
38 | __u8 x86; /* CPU family */ | |
39 | __u8 x86_model; /* model */ | |
40 | __u8 x86_mask; /* stepping */ | |
41 | }; | |
42 | ||
43 | enum { | |
44 | CPU_BANIAS, | |
45 | CPU_DOTHAN_A1, | |
46 | CPU_DOTHAN_A2, | |
47 | CPU_DOTHAN_B0, | |
8282864a DJ |
48 | CPU_MP4HT_D0, |
49 | CPU_MP4HT_E0, | |
1da177e4 LT |
50 | }; |
51 | ||
52 | static const struct cpu_id cpu_ids[] = { | |
53 | [CPU_BANIAS] = { 6, 9, 5 }, | |
54 | [CPU_DOTHAN_A1] = { 6, 13, 1 }, | |
55 | [CPU_DOTHAN_A2] = { 6, 13, 2 }, | |
56 | [CPU_DOTHAN_B0] = { 6, 13, 6 }, | |
8282864a DJ |
57 | [CPU_MP4HT_D0] = {15, 3, 4 }, |
58 | [CPU_MP4HT_E0] = {15, 4, 1 }, | |
1da177e4 | 59 | }; |
38e548ee | 60 | #define N_IDS ARRAY_SIZE(cpu_ids) |
1da177e4 LT |
61 | |
62 | struct cpu_model | |
63 | { | |
64 | const struct cpu_id *cpu_id; | |
65 | const char *model_name; | |
66 | unsigned max_freq; /* max clock in kHz */ | |
67 | ||
68 | struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */ | |
69 | }; | |
c4762aba MT |
70 | static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, |
71 | const struct cpu_id *x); | |
1da177e4 LT |
72 | |
73 | /* Operating points for current CPU */ | |
c4762aba MT |
74 | static DEFINE_PER_CPU(struct cpu_model *, centrino_model); |
75 | static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu); | |
1da177e4 LT |
76 | |
77 | static struct cpufreq_driver centrino_driver; | |
78 | ||
79 | #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE | |
80 | ||
81 | /* Computes the correct form for IA32_PERF_CTL MSR for a particular | |
82 | frequency/voltage operating point; frequency in MHz, volts in mV. | |
50701588 | 83 | This is stored as "driver_data" in the structure. */ |
1da177e4 LT |
84 | #define OP(mhz, mv) \ |
85 | { \ | |
86 | .frequency = (mhz) * 1000, \ | |
50701588 | 87 | .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \ |
1da177e4 LT |
88 | } |
89 | ||
90 | /* | |
91 | * These voltage tables were derived from the Intel Pentium M | |
92 | * datasheet, document 25261202.pdf, Table 5. I have verified they | |
93 | * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium | |
94 | * M. | |
95 | */ | |
96 | ||
97 | /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */ | |
98 | static struct cpufreq_frequency_table banias_900[] = | |
99 | { | |
100 | OP(600, 844), | |
101 | OP(800, 988), | |
102 | OP(900, 1004), | |
103 | { .frequency = CPUFREQ_TABLE_END } | |
104 | }; | |
105 | ||
106 | /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */ | |
107 | static struct cpufreq_frequency_table banias_1000[] = | |
108 | { | |
109 | OP(600, 844), | |
110 | OP(800, 972), | |
111 | OP(900, 988), | |
112 | OP(1000, 1004), | |
113 | { .frequency = CPUFREQ_TABLE_END } | |
114 | }; | |
115 | ||
116 | /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */ | |
117 | static struct cpufreq_frequency_table banias_1100[] = | |
118 | { | |
119 | OP( 600, 956), | |
120 | OP( 800, 1020), | |
121 | OP( 900, 1100), | |
122 | OP(1000, 1164), | |
123 | OP(1100, 1180), | |
124 | { .frequency = CPUFREQ_TABLE_END } | |
125 | }; | |
126 | ||
127 | ||
128 | /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */ | |
129 | static struct cpufreq_frequency_table banias_1200[] = | |
130 | { | |
131 | OP( 600, 956), | |
132 | OP( 800, 1004), | |
133 | OP( 900, 1020), | |
134 | OP(1000, 1100), | |
135 | OP(1100, 1164), | |
136 | OP(1200, 1180), | |
137 | { .frequency = CPUFREQ_TABLE_END } | |
138 | }; | |
139 | ||
140 | /* Intel Pentium M processor 1.30GHz (Banias) */ | |
141 | static struct cpufreq_frequency_table banias_1300[] = | |
142 | { | |
143 | OP( 600, 956), | |
144 | OP( 800, 1260), | |
145 | OP(1000, 1292), | |
146 | OP(1200, 1356), | |
147 | OP(1300, 1388), | |
148 | { .frequency = CPUFREQ_TABLE_END } | |
149 | }; | |
150 | ||
151 | /* Intel Pentium M processor 1.40GHz (Banias) */ | |
152 | static struct cpufreq_frequency_table banias_1400[] = | |
153 | { | |
154 | OP( 600, 956), | |
155 | OP( 800, 1180), | |
156 | OP(1000, 1308), | |
157 | OP(1200, 1436), | |
158 | OP(1400, 1484), | |
159 | { .frequency = CPUFREQ_TABLE_END } | |
160 | }; | |
161 | ||
162 | /* Intel Pentium M processor 1.50GHz (Banias) */ | |
163 | static struct cpufreq_frequency_table banias_1500[] = | |
164 | { | |
165 | OP( 600, 956), | |
166 | OP( 800, 1116), | |
167 | OP(1000, 1228), | |
168 | OP(1200, 1356), | |
169 | OP(1400, 1452), | |
170 | OP(1500, 1484), | |
171 | { .frequency = CPUFREQ_TABLE_END } | |
172 | }; | |
173 | ||
174 | /* Intel Pentium M processor 1.60GHz (Banias) */ | |
175 | static struct cpufreq_frequency_table banias_1600[] = | |
176 | { | |
177 | OP( 600, 956), | |
178 | OP( 800, 1036), | |
179 | OP(1000, 1164), | |
180 | OP(1200, 1276), | |
181 | OP(1400, 1420), | |
182 | OP(1600, 1484), | |
183 | { .frequency = CPUFREQ_TABLE_END } | |
184 | }; | |
185 | ||
186 | /* Intel Pentium M processor 1.70GHz (Banias) */ | |
187 | static struct cpufreq_frequency_table banias_1700[] = | |
188 | { | |
189 | OP( 600, 956), | |
190 | OP( 800, 1004), | |
191 | OP(1000, 1116), | |
192 | OP(1200, 1228), | |
193 | OP(1400, 1308), | |
194 | OP(1700, 1484), | |
195 | { .frequency = CPUFREQ_TABLE_END } | |
196 | }; | |
197 | #undef OP | |
198 | ||
199 | #define _BANIAS(cpuid, max, name) \ | |
200 | { .cpu_id = cpuid, \ | |
201 | .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \ | |
202 | .max_freq = (max)*1000, \ | |
203 | .op_points = banias_##max, \ | |
204 | } | |
205 | #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max) | |
206 | ||
207 | /* CPU models, their operating frequency range, and freq/voltage | |
208 | operating points */ | |
209 | static struct cpu_model models[] = | |
210 | { | |
211 | _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"), | |
212 | BANIAS(1000), | |
213 | BANIAS(1100), | |
214 | BANIAS(1200), | |
215 | BANIAS(1300), | |
216 | BANIAS(1400), | |
217 | BANIAS(1500), | |
218 | BANIAS(1600), | |
219 | BANIAS(1700), | |
220 | ||
221 | /* NULL model_name is a wildcard */ | |
222 | { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL }, | |
223 | { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL }, | |
224 | { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL }, | |
8282864a DJ |
225 | { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL }, |
226 | { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL }, | |
1da177e4 LT |
227 | |
228 | { NULL, } | |
229 | }; | |
230 | #undef _BANIAS | |
231 | #undef BANIAS | |
232 | ||
233 | static int centrino_cpu_init_table(struct cpufreq_policy *policy) | |
234 | { | |
92cb7612 | 235 | struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu); |
1da177e4 LT |
236 | struct cpu_model *model; |
237 | ||
238 | for(model = models; model->cpu_id != NULL; model++) | |
239 | if (centrino_verify_cpu_id(cpu, model->cpu_id) && | |
240 | (model->model_name == NULL || | |
241 | strcmp(cpu->x86_model_id, model->model_name) == 0)) | |
242 | break; | |
243 | ||
244 | if (model->cpu_id == NULL) { | |
245 | /* No match at all */ | |
2d06d8c4 | 246 | pr_debug("no support for CPU model \"%s\": " |
1da177e4 LT |
247 | "send /proc/cpuinfo to " MAINTAINER "\n", |
248 | cpu->x86_model_id); | |
249 | return -ENOENT; | |
250 | } | |
251 | ||
252 | if (model->op_points == NULL) { | |
253 | /* Matched a non-match */ | |
2d06d8c4 | 254 | pr_debug("no table support for CPU model \"%s\"\n", |
1da177e4 | 255 | cpu->x86_model_id); |
2d06d8c4 | 256 | pr_debug("try using the acpi-cpufreq driver\n"); |
1da177e4 LT |
257 | return -ENOENT; |
258 | } | |
259 | ||
c4762aba | 260 | per_cpu(centrino_model, policy->cpu) = model; |
1da177e4 | 261 | |
2d06d8c4 | 262 | pr_debug("found \"%s\": max frequency: %dkHz\n", |
1da177e4 LT |
263 | model->model_name, model->max_freq); |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
268 | #else | |
c4762aba MT |
269 | static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) |
270 | { | |
271 | return -ENODEV; | |
272 | } | |
1da177e4 LT |
273 | #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */ |
274 | ||
c4762aba MT |
275 | static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, |
276 | const struct cpu_id *x) | |
1da177e4 LT |
277 | { |
278 | if ((c->x86 == x->x86) && | |
279 | (c->x86_model == x->x86_model) && | |
280 | (c->x86_mask == x->x86_mask)) | |
281 | return 1; | |
282 | return 0; | |
283 | } | |
284 | ||
285 | /* To be called only after centrino_model is initialized */ | |
286 | static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe) | |
287 | { | |
288 | int i; | |
289 | ||
290 | /* | |
291 | * Extract clock in kHz from PERF_CTL value | |
292 | * for centrino, as some DSDTs are buggy. | |
293 | * Ideally, this can be done using the acpi_data structure. | |
294 | */ | |
c4762aba MT |
295 | if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) || |
296 | (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) || | |
297 | (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) { | |
1da177e4 LT |
298 | msr = (msr >> 8) & 0xff; |
299 | return msr * 100000; | |
300 | } | |
301 | ||
c4762aba MT |
302 | if ((!per_cpu(centrino_model, cpu)) || |
303 | (!per_cpu(centrino_model, cpu)->op_points)) | |
1da177e4 LT |
304 | return 0; |
305 | ||
306 | msr &= 0xffff; | |
c4762aba MT |
307 | for (i = 0; |
308 | per_cpu(centrino_model, cpu)->op_points[i].frequency | |
309 | != CPUFREQ_TABLE_END; | |
310 | i++) { | |
50701588 | 311 | if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data) |
c4762aba MT |
312 | return per_cpu(centrino_model, cpu)-> |
313 | op_points[i].frequency; | |
1da177e4 LT |
314 | } |
315 | if (failsafe) | |
c4762aba | 316 | return per_cpu(centrino_model, cpu)->op_points[i-1].frequency; |
1da177e4 LT |
317 | else |
318 | return 0; | |
319 | } | |
320 | ||
321 | /* Return the current CPU frequency in kHz */ | |
322 | static unsigned int get_cur_freq(unsigned int cpu) | |
323 | { | |
324 | unsigned l, h; | |
325 | unsigned clock_freq; | |
1da177e4 | 326 | |
e3f996c2 | 327 | rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h); |
1da177e4 LT |
328 | clock_freq = extract_clock(l, cpu, 0); |
329 | ||
330 | if (unlikely(clock_freq == 0)) { | |
331 | /* | |
332 | * On some CPUs, we can see transient MSR values (which are | |
333 | * not present in _PSS), while CPU is doing some automatic | |
334 | * P-state transition (like TM2). Get the last freq set | |
335 | * in PERF_CTL. | |
336 | */ | |
e3f996c2 | 337 | rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h); |
1da177e4 LT |
338 | clock_freq = extract_clock(l, cpu, 1); |
339 | } | |
1da177e4 LT |
340 | return clock_freq; |
341 | } | |
342 | ||
343 | ||
1da177e4 LT |
344 | static int centrino_cpu_init(struct cpufreq_policy *policy) |
345 | { | |
92cb7612 | 346 | struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu); |
1da177e4 | 347 | unsigned l, h; |
1da177e4 LT |
348 | int i; |
349 | ||
350 | /* Only Intel makes Enhanced Speedstep-capable CPUs */ | |
c4762aba MT |
351 | if (cpu->x86_vendor != X86_VENDOR_INTEL || |
352 | !cpu_has(cpu, X86_FEATURE_EST)) | |
1da177e4 LT |
353 | return -ENODEV; |
354 | ||
8ad5496d | 355 | if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC)) |
1da177e4 | 356 | centrino_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 357 | |
68485695 AB |
358 | if (policy->cpu != 0) |
359 | return -ENODEV; | |
1da177e4 | 360 | |
68485695 AB |
361 | for (i = 0; i < N_IDS; i++) |
362 | if (centrino_verify_cpu_id(cpu, &cpu_ids[i])) | |
363 | break; | |
f914be79 | 364 | |
68485695 | 365 | if (i != N_IDS) |
c4762aba | 366 | per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i]; |
f914be79 | 367 | |
c4762aba | 368 | if (!per_cpu(centrino_cpu, policy->cpu)) { |
2d06d8c4 | 369 | pr_debug("found unsupported CPU with " |
68485695 AB |
370 | "Enhanced SpeedStep: send /proc/cpuinfo to " |
371 | MAINTAINER "\n"); | |
372 | return -ENODEV; | |
373 | } | |
1da177e4 | 374 | |
7b6f38f0 | 375 | if (centrino_cpu_init_table(policy)) |
68485695 | 376 | return -ENODEV; |
1da177e4 LT |
377 | |
378 | /* Check to see if Enhanced SpeedStep is enabled, and try to | |
379 | enable it if not. */ | |
380 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
381 | ||
ecab22aa VN |
382 | if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) { |
383 | l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP; | |
2d06d8c4 | 384 | pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l); |
1da177e4 LT |
385 | wrmsr(MSR_IA32_MISC_ENABLE, l, h); |
386 | ||
387 | /* check to see if it stuck */ | |
388 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
ecab22aa | 389 | if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) { |
1c5864e2 | 390 | pr_info("couldn't enable Enhanced SpeedStep\n"); |
1da177e4 LT |
391 | return -ENODEV; |
392 | } | |
393 | } | |
394 | ||
c4762aba MT |
395 | policy->cpuinfo.transition_latency = 10000; |
396 | /* 10uS transition latency */ | |
1da177e4 | 397 | |
5f3a2d39 | 398 | return cpufreq_table_validate_and_show(policy, |
c4762aba | 399 | per_cpu(centrino_model, policy->cpu)->op_points); |
1da177e4 LT |
400 | } |
401 | ||
402 | static int centrino_cpu_exit(struct cpufreq_policy *policy) | |
403 | { | |
404 | unsigned int cpu = policy->cpu; | |
405 | ||
c4762aba | 406 | if (!per_cpu(centrino_model, cpu)) |
1da177e4 LT |
407 | return -ENODEV; |
408 | ||
c4762aba | 409 | per_cpu(centrino_model, cpu) = NULL; |
1da177e4 LT |
410 | |
411 | return 0; | |
412 | } | |
413 | ||
1da177e4 LT |
414 | /** |
415 | * centrino_setpolicy - set a new CPUFreq policy | |
416 | * @policy: new policy | |
9c0ebcf7 | 417 | * @index: index of target frequency |
1da177e4 LT |
418 | * |
419 | * Sets a new CPUFreq policy. | |
420 | */ | |
9c0ebcf7 | 421 | static int centrino_target(struct cpufreq_policy *policy, unsigned int index) |
1da177e4 | 422 | { |
c52851b6 | 423 | unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu; |
c52851b6 | 424 | int retval = 0; |
d4019f0a | 425 | unsigned int j, first_cpu; |
9c0ebcf7 | 426 | struct cpufreq_frequency_table *op_points; |
e3f996c2 | 427 | cpumask_var_t covered_cpus; |
eb53fac5 | 428 | |
e3f996c2 | 429 | if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))) |
5cb0535f | 430 | return -ENOMEM; |
eb53fac5 | 431 | |
c4762aba | 432 | if (unlikely(per_cpu(centrino_model, cpu) == NULL)) { |
eb53fac5 MT |
433 | retval = -ENODEV; |
434 | goto out; | |
435 | } | |
1da177e4 | 436 | |
c52851b6 | 437 | first_cpu = 1; |
9c0ebcf7 | 438 | op_points = &per_cpu(centrino_model, cpu)->op_points[index]; |
835481d9 | 439 | for_each_cpu(j, policy->cpus) { |
e3f996c2 | 440 | int good_cpu; |
9963d1aa | 441 | |
c52851b6 VP |
442 | /* |
443 | * Support for SMP systems. | |
444 | * Make sure we are running on CPU that wants to change freq | |
445 | */ | |
c52851b6 | 446 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) |
e3f996c2 RR |
447 | good_cpu = cpumask_any_and(policy->cpus, |
448 | cpu_online_mask); | |
c52851b6 | 449 | else |
e3f996c2 | 450 | good_cpu = j; |
c52851b6 | 451 | |
e3f996c2 | 452 | if (good_cpu >= nr_cpu_ids) { |
2d06d8c4 | 453 | pr_debug("couldn't limit to CPUs in this domain\n"); |
c52851b6 VP |
454 | retval = -EAGAIN; |
455 | if (first_cpu) { | |
456 | /* We haven't started the transition yet. */ | |
e3f996c2 | 457 | goto out; |
c52851b6 VP |
458 | } |
459 | break; | |
460 | } | |
1da177e4 | 461 | |
9c0ebcf7 | 462 | msr = op_points->driver_data; |
c52851b6 VP |
463 | |
464 | if (first_cpu) { | |
e3f996c2 | 465 | rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h); |
c52851b6 | 466 | if (msr == (oldmsr & 0xffff)) { |
2d06d8c4 | 467 | pr_debug("no change needed - msr was and needs " |
c52851b6 VP |
468 | "to be %x\n", oldmsr); |
469 | retval = 0; | |
e3f996c2 | 470 | goto out; |
c52851b6 VP |
471 | } |
472 | ||
c52851b6 VP |
473 | first_cpu = 0; |
474 | /* all but 16 LSB are reserved, treat them with care */ | |
475 | oldmsr &= ~0xffff; | |
476 | msr &= 0xffff; | |
477 | oldmsr |= msr; | |
478 | } | |
1da177e4 | 479 | |
e3f996c2 RR |
480 | wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h); |
481 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) | |
c52851b6 | 482 | break; |
1da177e4 | 483 | |
e3f996c2 | 484 | cpumask_set_cpu(j, covered_cpus); |
c52851b6 | 485 | } |
1da177e4 | 486 | |
c52851b6 VP |
487 | if (unlikely(retval)) { |
488 | /* | |
489 | * We have failed halfway through the frequency change. | |
490 | * We have sent callbacks to policy->cpus and | |
491 | * MSRs have already been written on coverd_cpus. | |
492 | * Best effort undo.. | |
493 | */ | |
1da177e4 | 494 | |
e3f996c2 RR |
495 | for_each_cpu(j, covered_cpus) |
496 | wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h); | |
c52851b6 | 497 | } |
eb53fac5 | 498 | retval = 0; |
1da177e4 | 499 | |
eb53fac5 | 500 | out: |
5cb0535f | 501 | free_cpumask_var(covered_cpus); |
eb53fac5 | 502 | return retval; |
1da177e4 LT |
503 | } |
504 | ||
1da177e4 LT |
505 | static struct cpufreq_driver centrino_driver = { |
506 | .name = "centrino", /* should be speedstep-centrino, | |
507 | but there's a 16 char limit */ | |
508 | .init = centrino_cpu_init, | |
509 | .exit = centrino_cpu_exit, | |
3be1394a | 510 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 511 | .target_index = centrino_target, |
1da177e4 | 512 | .get = get_cur_freq, |
3be1394a | 513 | .attr = cpufreq_generic_attr, |
1da177e4 LT |
514 | }; |
515 | ||
fa8031ae AK |
516 | /* |
517 | * This doesn't replace the detailed checks above because | |
518 | * the generic CPU IDs don't have a way to match for steppings | |
519 | * or ASCII model IDs. | |
520 | */ | |
521 | static const struct x86_cpu_id centrino_ids[] = { | |
522 | { X86_VENDOR_INTEL, 6, 9, X86_FEATURE_EST }, | |
523 | { X86_VENDOR_INTEL, 6, 13, X86_FEATURE_EST }, | |
524 | { X86_VENDOR_INTEL, 6, 13, X86_FEATURE_EST }, | |
525 | { X86_VENDOR_INTEL, 6, 13, X86_FEATURE_EST }, | |
526 | { X86_VENDOR_INTEL, 15, 3, X86_FEATURE_EST }, | |
527 | { X86_VENDOR_INTEL, 15, 4, X86_FEATURE_EST }, | |
528 | {} | |
529 | }; | |
530 | #if 0 | |
531 | /* Autoload or not? Do not for now. */ | |
532 | MODULE_DEVICE_TABLE(x86cpu, centrino_ids); | |
533 | #endif | |
1da177e4 LT |
534 | |
535 | /** | |
536 | * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver | |
537 | * | |
538 | * Initializes the Enhanced SpeedStep support. Returns -ENODEV on | |
539 | * unsupported devices, -ENOENT if there's no voltage table for this | |
540 | * particular CPU model, -EINVAL on problems during initiatization, | |
541 | * and zero on success. | |
542 | * | |
543 | * This is quite picky. Not only does the CPU have to advertise the | |
544 | * "est" flag in the cpuid capability flags, we look for a specific | |
545 | * CPU model and stepping, and we need to have the exact model name in | |
546 | * our voltage tables. That is, be paranoid about not releasing | |
547 | * someone's valuable magic smoke. | |
548 | */ | |
549 | static int __init centrino_init(void) | |
550 | { | |
fa8031ae | 551 | if (!x86_match_cpu(centrino_ids)) |
1da177e4 | 552 | return -ENODEV; |
1da177e4 LT |
553 | return cpufreq_register_driver(¢rino_driver); |
554 | } | |
555 | ||
556 | static void __exit centrino_exit(void) | |
557 | { | |
558 | cpufreq_unregister_driver(¢rino_driver); | |
559 | } | |
560 | ||
561 | MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>"); | |
562 | MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors."); | |
563 | MODULE_LICENSE ("GPL"); | |
564 | ||
565 | late_initcall(centrino_init); | |
566 | module_exit(centrino_exit); |