Commit | Line | Data |
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7056d423 | 1 | /* |
7056d423 CC |
2 | * Copyright (C) 2010 Google, Inc. |
3 | * | |
4 | * Author: | |
5 | * Colin Cross <ccross@google.com> | |
6 | * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/types.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/io.h> | |
1eb2ecf1 | 29 | #include <linux/suspend.h> |
7056d423 | 30 | |
7056d423 | 31 | static struct cpufreq_frequency_table freq_table[] = { |
5d69030d VK |
32 | { .frequency = 216000 }, |
33 | { .frequency = 312000 }, | |
34 | { .frequency = 456000 }, | |
35 | { .frequency = 608000 }, | |
36 | { .frequency = 760000 }, | |
37 | { .frequency = 816000 }, | |
38 | { .frequency = 912000 }, | |
39 | { .frequency = 1000000 }, | |
40 | { .frequency = CPUFREQ_TABLE_END }, | |
7056d423 CC |
41 | }; |
42 | ||
43 | #define NUM_CPUS 2 | |
44 | ||
45 | static struct clk *cpu_clk; | |
ce32ddaa SW |
46 | static struct clk *pll_x_clk; |
47 | static struct clk *pll_p_clk; | |
7a281284 | 48 | static struct clk *emc_clk; |
7056d423 CC |
49 | |
50 | static unsigned long target_cpu_speed[NUM_CPUS]; | |
1eb2ecf1 CC |
51 | static DEFINE_MUTEX(tegra_cpu_lock); |
52 | static bool is_suspended; | |
7056d423 | 53 | |
6686c733 | 54 | static unsigned int tegra_getspeed(unsigned int cpu) |
7056d423 CC |
55 | { |
56 | unsigned long rate; | |
57 | ||
58 | if (cpu >= NUM_CPUS) | |
59 | return 0; | |
60 | ||
61 | rate = clk_get_rate(cpu_clk) / 1000; | |
62 | return rate; | |
63 | } | |
64 | ||
ce32ddaa SW |
65 | static int tegra_cpu_clk_set_rate(unsigned long rate) |
66 | { | |
67 | int ret; | |
68 | ||
69 | /* | |
70 | * Take an extra reference to the main pll so it doesn't turn | |
71 | * off when we move the cpu off of it | |
72 | */ | |
73 | clk_prepare_enable(pll_x_clk); | |
74 | ||
75 | ret = clk_set_parent(cpu_clk, pll_p_clk); | |
76 | if (ret) { | |
77 | pr_err("Failed to switch cpu to clock pll_p\n"); | |
78 | goto out; | |
79 | } | |
80 | ||
81 | if (rate == clk_get_rate(pll_p_clk)) | |
82 | goto out; | |
83 | ||
84 | ret = clk_set_rate(pll_x_clk, rate); | |
85 | if (ret) { | |
86 | pr_err("Failed to change pll_x to %lu\n", rate); | |
87 | goto out; | |
88 | } | |
89 | ||
90 | ret = clk_set_parent(cpu_clk, pll_x_clk); | |
91 | if (ret) { | |
92 | pr_err("Failed to switch cpu to clock pll_x\n"); | |
93 | goto out; | |
94 | } | |
95 | ||
96 | out: | |
97 | clk_disable_unprepare(pll_x_clk); | |
98 | return ret; | |
99 | } | |
100 | ||
b43a7ffb VK |
101 | static int tegra_update_cpu_speed(struct cpufreq_policy *policy, |
102 | unsigned long rate) | |
7056d423 | 103 | { |
7056d423 | 104 | int ret = 0; |
7056d423 | 105 | |
d4019f0a | 106 | if (tegra_getspeed(0) == rate) |
7056d423 CC |
107 | return ret; |
108 | ||
7a281284 CC |
109 | /* |
110 | * Vote on memory bus frequency based on cpu frequency | |
111 | * This sets the minimum frequency, display or avp may request higher | |
112 | */ | |
113 | if (rate >= 816000) | |
114 | clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */ | |
115 | else if (rate >= 456000) | |
116 | clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */ | |
117 | else | |
118 | clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */ | |
119 | ||
d4019f0a VK |
120 | ret = tegra_cpu_clk_set_rate(rate * 1000); |
121 | if (ret) | |
122 | pr_err("cpu-tegra: Failed to set cpu frequency to %lu kHz\n", | |
123 | rate); | |
7056d423 | 124 | |
f56cc99e | 125 | return ret; |
7056d423 CC |
126 | } |
127 | ||
1eb2ecf1 CC |
128 | static unsigned long tegra_cpu_highest_speed(void) |
129 | { | |
130 | unsigned long rate = 0; | |
131 | int i; | |
132 | ||
133 | for_each_online_cpu(i) | |
134 | rate = max(rate, target_cpu_speed[i]); | |
135 | return rate; | |
136 | } | |
137 | ||
9c0ebcf7 | 138 | static int tegra_target(struct cpufreq_policy *policy, unsigned int index) |
7056d423 | 139 | { |
7056d423 | 140 | unsigned int freq; |
1eb2ecf1 CC |
141 | int ret = 0; |
142 | ||
143 | mutex_lock(&tegra_cpu_lock); | |
144 | ||
2239aa3d | 145 | if (is_suspended) |
1eb2ecf1 | 146 | goto out; |
7056d423 | 147 | |
9c0ebcf7 | 148 | freq = freq_table[index].frequency; |
7056d423 CC |
149 | |
150 | target_cpu_speed[policy->cpu] = freq; | |
151 | ||
b43a7ffb | 152 | ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed()); |
1eb2ecf1 CC |
153 | |
154 | out: | |
155 | mutex_unlock(&tegra_cpu_lock); | |
156 | return ret; | |
7056d423 CC |
157 | } |
158 | ||
1eb2ecf1 CC |
159 | static int tegra_pm_notify(struct notifier_block *nb, unsigned long event, |
160 | void *dummy) | |
161 | { | |
162 | mutex_lock(&tegra_cpu_lock); | |
163 | if (event == PM_SUSPEND_PREPARE) { | |
b43a7ffb | 164 | struct cpufreq_policy *policy = cpufreq_cpu_get(0); |
1eb2ecf1 CC |
165 | is_suspended = true; |
166 | pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n", | |
167 | freq_table[0].frequency); | |
b43a7ffb VK |
168 | tegra_update_cpu_speed(policy, freq_table[0].frequency); |
169 | cpufreq_cpu_put(policy); | |
1eb2ecf1 CC |
170 | } else if (event == PM_POST_SUSPEND) { |
171 | is_suspended = false; | |
172 | } | |
173 | mutex_unlock(&tegra_cpu_lock); | |
174 | ||
175 | return NOTIFY_OK; | |
176 | } | |
177 | ||
178 | static struct notifier_block tegra_cpu_pm_notifier = { | |
179 | .notifier_call = tegra_pm_notify, | |
180 | }; | |
181 | ||
7056d423 CC |
182 | static int tegra_cpu_init(struct cpufreq_policy *policy) |
183 | { | |
99d428cf VK |
184 | int ret; |
185 | ||
7056d423 CC |
186 | if (policy->cpu >= NUM_CPUS) |
187 | return -EINVAL; | |
188 | ||
6a5278d0 PG |
189 | clk_prepare_enable(emc_clk); |
190 | clk_prepare_enable(cpu_clk); | |
89a5fb84 | 191 | |
21c895ce | 192 | target_cpu_speed[policy->cpu] = tegra_getspeed(policy->cpu); |
7056d423 CC |
193 | |
194 | /* FIXME: what's the actual transition time? */ | |
99d428cf VK |
195 | ret = cpufreq_generic_init(policy, freq_table, 300 * 1000); |
196 | if (ret) { | |
197 | clk_disable_unprepare(cpu_clk); | |
198 | clk_disable_unprepare(emc_clk); | |
199 | return ret; | |
200 | } | |
7056d423 | 201 | |
1eb2ecf1 CC |
202 | if (policy->cpu == 0) |
203 | register_pm_notifier(&tegra_cpu_pm_notifier); | |
204 | ||
7056d423 CC |
205 | return 0; |
206 | } | |
207 | ||
208 | static int tegra_cpu_exit(struct cpufreq_policy *policy) | |
209 | { | |
2e6a5c80 | 210 | cpufreq_frequency_table_put_attr(policy->cpu); |
99d428cf | 211 | clk_disable_unprepare(cpu_clk); |
6a5278d0 | 212 | clk_disable_unprepare(emc_clk); |
7056d423 CC |
213 | return 0; |
214 | } | |
215 | ||
7056d423 | 216 | static struct cpufreq_driver tegra_cpufreq_driver = { |
ae6b4271 | 217 | .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
8e08cf03 | 218 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 219 | .target_index = tegra_target, |
7056d423 CC |
220 | .get = tegra_getspeed, |
221 | .init = tegra_cpu_init, | |
222 | .exit = tegra_cpu_exit, | |
223 | .name = "tegra", | |
8e08cf03 | 224 | .attr = cpufreq_generic_attr, |
7056d423 CC |
225 | }; |
226 | ||
227 | static int __init tegra_cpufreq_init(void) | |
228 | { | |
b192b910 | 229 | cpu_clk = clk_get_sys(NULL, "cclk"); |
c26cefd0 RZ |
230 | if (IS_ERR(cpu_clk)) |
231 | return PTR_ERR(cpu_clk); | |
232 | ||
233 | pll_x_clk = clk_get_sys(NULL, "pll_x"); | |
234 | if (IS_ERR(pll_x_clk)) | |
235 | return PTR_ERR(pll_x_clk); | |
236 | ||
b192b910 | 237 | pll_p_clk = clk_get_sys(NULL, "pll_p"); |
c26cefd0 RZ |
238 | if (IS_ERR(pll_p_clk)) |
239 | return PTR_ERR(pll_p_clk); | |
240 | ||
241 | emc_clk = clk_get_sys("cpu", "emc"); | |
242 | if (IS_ERR(emc_clk)) { | |
243 | clk_put(cpu_clk); | |
244 | return PTR_ERR(emc_clk); | |
245 | } | |
246 | ||
7056d423 CC |
247 | return cpufreq_register_driver(&tegra_cpufreq_driver); |
248 | } | |
249 | ||
250 | static void __exit tegra_cpufreq_exit(void) | |
251 | { | |
252 | cpufreq_unregister_driver(&tegra_cpufreq_driver); | |
c26cefd0 RZ |
253 | clk_put(emc_clk); |
254 | clk_put(cpu_clk); | |
7056d423 CC |
255 | } |
256 | ||
257 | ||
258 | MODULE_AUTHOR("Colin Cross <ccross@android.com>"); | |
259 | MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2"); | |
260 | MODULE_LICENSE("GPL"); | |
261 | module_init(tegra_cpufreq_init); | |
262 | module_exit(tegra_cpufreq_exit); |