[deliverable/linux.git] / drivers / crypto / caam / ctrl.c

/*
 * CAAM control-plane driver backend
 * Controller-level driver, kernel property detection, initialization
 *
 * Copyright 2008-2012 Freescale Semiconductor, Inc.
 */

#include "compat.h"
#include "regs.h"
#include "intern.h"
#include "jr.h"
#include "desc_constr.h"
#include "error.h"
#include "ctrl.h"

static int caam_remove(struct platform_device *pdev)
{
	struct device *ctrldev;
	struct caam_drv_private *ctrlpriv;
	struct caam_drv_private_jr *jrpriv;
	struct caam_full __iomem *topregs;
	int ring, ret = 0;

	ctrldev = &pdev->dev;
	ctrlpriv = dev_get_drvdata(ctrldev);
	topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;

	/* shut down JobRs */
	for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
		ret |= caam_jr_shutdown(ctrlpriv->jrdev[ring]);
		jrpriv = dev_get_drvdata(ctrlpriv->jrdev[ring]);
		irq_dispose_mapping(jrpriv->irq);
	}

	/* Shut down debug views */
#ifdef CONFIG_DEBUG_FS
	debugfs_remove_recursive(ctrlpriv->dfs_root);
#endif

	/* Unmap controller region */
	iounmap(&topregs->ctrl);

	kfree(ctrlpriv->jrdev);
	kfree(ctrlpriv);

	return ret;
}

/*
 * Descriptor to instantiate RNG State Handle 0 in normal mode and
 * load the JDKEK, TDKEK and TDSK registers
 */
static void build_instantiation_desc(u32 *desc)
{
	u32 *jump_cmd;

	init_job_desc(desc, 0);

	/* INIT RNG in non-test mode */
	append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
			 OP_ALG_AS_INIT);

	/* wait for done */
	jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
	set_jump_tgt_here(desc, jump_cmd);

	/*
	 * load 1 to clear written reg:
	 * resets the done interrupt and returns the RNG to idle.
	 */
	append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);

	/* generate secure keys (non-test) */
	append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
			 OP_ALG_RNG4_SK);
}

static int instantiate_rng(struct device *ctrldev)
{
	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
	struct caam_full __iomem *topregs;
	unsigned int timeout = 100000;
	u32 *desc;
	int i, ret = 0;

	desc = kmalloc(CAAM_CMD_SZ * 6, GFP_KERNEL | GFP_DMA);
	if (!desc) {
		dev_err(ctrldev, "can't allocate RNG init descriptor memory\n");
		return -ENOMEM;
	}
	build_instantiation_desc(desc);

	/* Set the bit to request direct access to DECO0 */
	topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
	setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);

	while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) &&
								 --timeout)
		cpu_relax();

	if (!timeout) {
		dev_err(ctrldev, "failed to acquire DECO 0\n");
		ret = -EIO;
		goto out;
	}

	for (i = 0; i < desc_len(desc); i++)
		topregs->deco.descbuf[i] = *(desc + i);

	wr_reg32(&topregs->deco.jr_ctl_hi, DECO_JQCR_WHL | DECO_JQCR_FOUR);

	timeout = 10000000;
	while ((rd_reg32(&topregs->deco.desc_dbg) & DECO_DBG_VALID) &&
								 --timeout)
		cpu_relax();

	if (!timeout) {
		dev_err(ctrldev, "failed to instantiate RNG\n");
		ret = -EIO;
	}

	clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
out:
	kfree(desc);
	return ret;
}

/*
 * By default, the TRNG runs for 200 clocks per sample;
 * 1600 clocks per sample generates better entropy.
 */
static void kick_trng(struct platform_device *pdev)
{
	struct device *ctrldev = &pdev->dev;
	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
	struct caam_full __iomem *topregs;
	struct rng4tst __iomem *r4tst;
	u32 val;

	topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
	r4tst = &topregs->ctrl.r4tst[0];

	/* put RNG4 into program mode */
	setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
	/* 1600 clocks per sample */
	val = rd_reg32(&r4tst->rtsdctl);
	val = (val & ~RTSDCTL_ENT_DLY_MASK) | (1600 << RTSDCTL_ENT_DLY_SHIFT);
	wr_reg32(&r4tst->rtsdctl, val);
	/* min. freq. count */
	wr_reg32(&r4tst->rtfrqmin, 400);
	/* max. freq. count */
	wr_reg32(&r4tst->rtfrqmax, 6400);
	/* put RNG4 into run mode */
	clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
}

/**
 * caam_get_era() - Return the ERA of the SEC on SoC, based
 * on the SEC_VID register.
 * Returns the ERA number (1..4) or -ENOTSUPP if the ERA is unknown.
 * @caam_id - the value of the SEC_VID register
 **/
int caam_get_era(u64 caam_id)
{
	struct sec_vid *sec_vid = (struct sec_vid *)&caam_id;
	static const struct {
		u16 ip_id;
		u8 maj_rev;
		u8 era;
	} caam_eras[] = {
		{0x0A10, 1, 1},
		{0x0A10, 2, 2},
		{0x0A12, 1, 3},
		{0x0A14, 1, 3},
		{0x0A14, 2, 4},
		{0x0A16, 1, 4},
		{0x0A11, 1, 4}
	};
	int i;

	for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
		if (caam_eras[i].ip_id == sec_vid->ip_id &&
			caam_eras[i].maj_rev == sec_vid->maj_rev)
				return caam_eras[i].era;

	return -ENOTSUPP;
}
EXPORT_SYMBOL(caam_get_era);

/* Probe routine for CAAM top (controller) level */
static int caam_probe(struct platform_device *pdev)
{
	int ret, ring, rspec;
	u64 caam_id;
	struct device *dev;
	struct device_node *nprop, *np;
	struct caam_ctrl __iomem *ctrl;
	struct caam_full __iomem *topregs;
	struct caam_drv_private *ctrlpriv;
#ifdef CONFIG_DEBUG_FS
	struct caam_perfmon *perfmon;
#endif
	u64 cha_vid;

	ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
	if (!ctrlpriv)
		return -ENOMEM;

	dev = &pdev->dev;
	dev_set_drvdata(dev, ctrlpriv);
	ctrlpriv->pdev = pdev;
	nprop = pdev->dev.of_node;

	/* Get configuration properties from device tree */
	/* First, get register page */
	ctrl = of_iomap(nprop, 0);
	if (ctrl == NULL) {
		dev_err(dev, "caam: of_iomap() failed\n");
		return -ENOMEM;
	}
	ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;

	/* topregs used to derive pointers to CAAM sub-blocks only */
	topregs = (struct caam_full __iomem *)ctrl;

	/* Get the IRQ of the controller (for security violations only) */
	ctrlpriv->secvio_irq = of_irq_to_resource(nprop, 0, NULL);

	/*
	 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
	 * long pointers in master configuration register
	 */
	setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
		  (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));

	if (sizeof(dma_addr_t) == sizeof(u64))
		if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
			dma_set_mask(dev, DMA_BIT_MASK(40));
		else
			dma_set_mask(dev, DMA_BIT_MASK(36));
	else
		dma_set_mask(dev, DMA_BIT_MASK(32));

	/*
	 * Detect and enable JobRs
	 * First, find out how many ring spec'ed, allocate references
	 * for all, then go probe each one.
	 */
	rspec = 0;
	for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring")
		rspec++;
	if (!rspec) {
		/* for backward compatible with device trees */
		for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring")
			rspec++;
	}

	ctrlpriv->jrdev = kzalloc(sizeof(struct device *) * rspec, GFP_KERNEL);
	if (ctrlpriv->jrdev == NULL) {
		iounmap(&topregs->ctrl);
		return -ENOMEM;
	}

	ring = 0;
	ctrlpriv->total_jobrs = 0;
	for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") {
		caam_jr_probe(pdev, np, ring);
		ctrlpriv->total_jobrs++;
		ring++;
	}
	if (!ring) {
		for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") {
			caam_jr_probe(pdev, np, ring);
			ctrlpriv->total_jobrs++;
			ring++;
		}
	}

	/* Check to see if QI present. If so, enable */
	ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
				  CTPR_QI_MASK);
	if (ctrlpriv->qi_present) {
		ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
		/* This is all that's required to physically enable QI */
		wr_reg32(&topregs->qi.qi_control_lo, QICTL_DQEN);
	}

	/* If no QI and no rings specified, quit and go home */
	if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
		dev_err(dev, "no queues configured, terminating\n");
		caam_remove(pdev);
		return -ENOMEM;
	}

	cha_vid = rd_reg64(&topregs->ctrl.perfmon.cha_id);

	/*
	 * If SEC has RNG version >= 4 and RNG state handle has not been
	 * already instantiated ,do RNG instantiation
	 */
	if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4 &&
	    !(rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & RDSTA_IF0)) {
		kick_trng(pdev);
		ret = instantiate_rng(dev);
		if (ret) {
			caam_remove(pdev);
			return ret;
		}

		/* Enable RDB bit so that RNG works faster */
		setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
	}

	/* NOTE: RTIC detection ought to go here, around Si time */

	caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);

	/* Report "alive" for developer to see */
	dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
		 caam_get_era(caam_id));
	dev_info(dev, "job rings = %d, qi = %d\n",
		 ctrlpriv->total_jobrs, ctrlpriv->qi_present);

#ifdef CONFIG_DEBUG_FS
	/*
	 * FIXME: needs better naming distinction, as some amalgamation of
	 * "caam" and nprop->full_name. The OF name isn't distinctive,
	 * but does separate instances
	 */
	perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;

	ctrlpriv->dfs_root = debugfs_create_dir("caam", NULL);
	ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);

	/* Controller-level - performance monitor counters */
	ctrlpriv->ctl_rq_dequeued =
		debugfs_create_u64("rq_dequeued",
				   S_IRUSR | S_IRGRP | S_IROTH,
				   ctrlpriv->ctl, &perfmon->req_dequeued);
	ctrlpriv->ctl_ob_enc_req =
		debugfs_create_u64("ob_rq_encrypted",
				   S_IRUSR | S_IRGRP | S_IROTH,
				   ctrlpriv->ctl, &perfmon->ob_enc_req);
	ctrlpriv->ctl_ib_dec_req =
		debugfs_create_u64("ib_rq_decrypted",
				   S_IRUSR | S_IRGRP | S_IROTH,
				   ctrlpriv->ctl, &perfmon->ib_dec_req);
	ctrlpriv->ctl_ob_enc_bytes =
		debugfs_create_u64("ob_bytes_encrypted",
				   S_IRUSR | S_IRGRP | S_IROTH,
				   ctrlpriv->ctl, &perfmon->ob_enc_bytes);
	ctrlpriv->ctl_ob_prot_bytes =
		debugfs_create_u64("ob_bytes_protected",
				   S_IRUSR | S_IRGRP | S_IROTH,
				   ctrlpriv->ctl, &perfmon->ob_prot_bytes);
	ctrlpriv->ctl_ib_dec_bytes =
		debugfs_create_u64("ib_bytes_decrypted",
				   S_IRUSR | S_IRGRP | S_IROTH,
				   ctrlpriv->ctl, &perfmon->ib_dec_bytes);
	ctrlpriv->ctl_ib_valid_bytes =
		debugfs_create_u64("ib_bytes_validated",
				   S_IRUSR | S_IRGRP | S_IROTH,
				   ctrlpriv->ctl, &perfmon->ib_valid_bytes);

	/* Controller level - global status values */
	ctrlpriv->ctl_faultaddr =
		debugfs_create_u64("fault_addr",
				   S_IRUSR | S_IRGRP | S_IROTH,
				   ctrlpriv->ctl, &perfmon->faultaddr);
	ctrlpriv->ctl_faultdetail =
		debugfs_create_u32("fault_detail",
				   S_IRUSR | S_IRGRP | S_IROTH,
				   ctrlpriv->ctl, &perfmon->faultdetail);
	ctrlpriv->ctl_faultstatus =
		debugfs_create_u32("fault_status",
				   S_IRUSR | S_IRGRP | S_IROTH,
				   ctrlpriv->ctl, &perfmon->status);

	/* Internal covering keys (useful in non-secure mode only) */
	ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
	ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
	ctrlpriv->ctl_kek = debugfs_create_blob("kek",
						S_IRUSR |
						S_IRGRP | S_IROTH,
						ctrlpriv->ctl,
						&ctrlpriv->ctl_kek_wrap);

	ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
	ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
	ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
						 S_IRUSR |
						 S_IRGRP | S_IROTH,
						 ctrlpriv->ctl,
						 &ctrlpriv->ctl_tkek_wrap);

	ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
	ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
	ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
						 S_IRUSR |
						 S_IRGRP | S_IROTH,
						 ctrlpriv->ctl,
						 &ctrlpriv->ctl_tdsk_wrap);
#endif
	return 0;
}

static struct of_device_id caam_match[] = {
	{
		.compatible = "fsl,sec-v4.0",
	},
	{
		.compatible = "fsl,sec4.0",
	},
	{},
};
MODULE_DEVICE_TABLE(of, caam_match);

static struct platform_driver caam_driver = {
	.driver = {
		.name = "caam",
		.owner = THIS_MODULE,
		.of_match_table = caam_match,
	},
	.probe       = caam_probe,
	.remove      = caam_remove,
};

module_platform_driver(caam_driver);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("FSL CAAM request backend");
MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
Commit	Line	Data
8e8ec596 KP	1	/*
	2	* CAAM control-plane driver backend
	3	* Controller-level driver, kernel property detection, initialization
	4	*
281922a1	5	* Copyright 2008-2012 Freescale Semiconductor, Inc.
8e8ec596 KP	6	*/
	7
	8	#include "compat.h"
	9	#include "regs.h"
	10	#include "intern.h"
	11	#include "jr.h"
281922a1 KP	12	#include "desc_constr.h"
281922a1 KP	13	#include "error.h"
82c2f960	14	#include "ctrl.h"
8e8ec596 KP	15
	16	static int caam_remove(struct platform_device *pdev)
	17	{
	18	struct device *ctrldev;
	19	struct caam_drv_private *ctrlpriv;
	20	struct caam_drv_private_jr *jrpriv;
	21	struct caam_full __iomem *topregs;
	22	int ring, ret = 0;
	23
	24	ctrldev = &pdev->dev;
	25	ctrlpriv = dev_get_drvdata(ctrldev);
	26	topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
	27
	28	/* shut down JobRs */
	29	for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
	30	ret \|= caam_jr_shutdown(ctrlpriv->jrdev[ring]);
	31	jrpriv = dev_get_drvdata(ctrlpriv->jrdev[ring]);
	32	irq_dispose_mapping(jrpriv->irq);
	33	}
	34
	35	/* Shut down debug views */
	36	#ifdef CONFIG_DEBUG_FS
	37	debugfs_remove_recursive(ctrlpriv->dfs_root);
	38	#endif
	39
	40	/* Unmap controller region */
	41	iounmap(&topregs->ctrl);
	42
	43	kfree(ctrlpriv->jrdev);
	44	kfree(ctrlpriv);
	45
	46	return ret;
	47	}
	48
281922a1 KP	49	/*
	50	* Descriptor to instantiate RNG State Handle 0 in normal mode and
	51	* load the JDKEK, TDKEK and TDSK registers
	52	*/
	53	static void build_instantiation_desc(u32 *desc)
	54	{
	55	u32 *jump_cmd;
	56
	57	init_job_desc(desc, 0);
	58
	59	/* INIT RNG in non-test mode */
	60	append_operation(desc, OP_TYPE_CLASS1_ALG \| OP_ALG_ALGSEL_RNG \|
	61	OP_ALG_AS_INIT);
	62
	63	/* wait for done */
	64	jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
	65	set_jump_tgt_here(desc, jump_cmd);
	66
	67	/*
	68	* load 1 to clear written reg:
cf2fbdd2	69	* resets the done interrupt and returns the RNG to idle.
281922a1 KP	70	*/
	71	append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
	72
	73	/* generate secure keys (non-test) */
	74	append_operation(desc, OP_TYPE_CLASS1_ALG \| OP_ALG_ALGSEL_RNG \|
	75	OP_ALG_RNG4_SK);
	76	}
	77
997ad290	78	static int instantiate_rng(struct device *ctrldev)
281922a1	79	{
997ad290 RG	80	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
	81	struct caam_full __iomem *topregs;
	82	unsigned int timeout = 100000;
281922a1	83	u32 *desc;
997ad290	84	int i, ret = 0;
281922a1 KP	85
	86	desc = kmalloc(CAAM_CMD_SZ * 6, GFP_KERNEL \| GFP_DMA);
	87	if (!desc) {
997ad290	88	dev_err(ctrldev, "can't allocate RNG init descriptor memory\n");
281922a1 KP	89	return -ENOMEM;
281922a1 KP	90	}
281922a1	91	build_instantiation_desc(desc);
997ad290 RG	92
	93	/* Set the bit to request direct access to DECO0 */
	94	topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
	95	setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
	96
	97	while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) &&
	98	--timeout)
	99	cpu_relax();
	100
	101	if (!timeout) {
	102	dev_err(ctrldev, "failed to acquire DECO 0\n");
	103	ret = -EIO;
	104	goto out;
281922a1 KP	105	}
281922a1 KP	106
997ad290 RG	107	for (i = 0; i < desc_len(desc); i++)
997ad290 RG	108	topregs->deco.descbuf[i] = *(desc + i);
281922a1	109
997ad290 RG	110	wr_reg32(&topregs->deco.jr_ctl_hi, DECO_JQCR_WHL \| DECO_JQCR_FOUR);
	111
	112	timeout = 10000000;
	113	while ((rd_reg32(&topregs->deco.desc_dbg) & DECO_DBG_VALID) &&
	114	--timeout)
	115	cpu_relax();
281922a1	116
997ad290 RG	117	if (!timeout) {
	118	dev_err(ctrldev, "failed to instantiate RNG\n");
	119	ret = -EIO;
	120	}
	121
	122	clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
	123	out:
	124	kfree(desc);
281922a1 KP	125	return ret;
	126	}
	127
	128	/*
	129	* By default, the TRNG runs for 200 clocks per sample;
a5bbf6fa	130	* 1600 clocks per sample generates better entropy.
281922a1 KP	131	*/
	132	static void kick_trng(struct platform_device *pdev)
	133	{
	134	struct device *ctrldev = &pdev->dev;
	135	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
	136	struct caam_full __iomem *topregs;
	137	struct rng4tst __iomem *r4tst;
	138	u32 val;
	139
	140	topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
	141	r4tst = &topregs->ctrl.r4tst[0];
	142
	143	/* put RNG4 into program mode */
	144	setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
a5bbf6fa	145	/* 1600 clocks per sample */
281922a1	146	val = rd_reg32(&r4tst->rtsdctl);
a5bbf6fa	147	val = (val & ~RTSDCTL_ENT_DLY_MASK) \| (1600 << RTSDCTL_ENT_DLY_SHIFT);
281922a1 KP	148	wr_reg32(&r4tst->rtsdctl, val);
	149	/* min. freq. count */
	150	wr_reg32(&r4tst->rtfrqmin, 400);
	151	/* max. freq. count */
	152	wr_reg32(&r4tst->rtfrqmax, 6400);
	153	/* put RNG4 into run mode */
	154	clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
	155	}
	156
82c2f960 AP	157	/**
	158	* caam_get_era() - Return the ERA of the SEC on SoC, based
	159	* on the SEC_VID register.
	160	* Returns the ERA number (1..4) or -ENOTSUPP if the ERA is unknown.
	161	* @caam_id - the value of the SEC_VID register
	162	**/
	163	int caam_get_era(u64 caam_id)
	164	{
	165	struct sec_vid sec_vid = (struct sec_vid )&caam_id;
	166	static const struct {
	167	u16 ip_id;
	168	u8 maj_rev;
	169	u8 era;
	170	} caam_eras[] = {
	171	{0x0A10, 1, 1},
	172	{0x0A10, 2, 2},
	173	{0x0A12, 1, 3},
	174	{0x0A14, 1, 3},
	175	{0x0A14, 2, 4},
	176	{0x0A16, 1, 4},
	177	{0x0A11, 1, 4}
	178	};
	179	int i;
	180
	181	for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
	182	if (caam_eras[i].ip_id == sec_vid->ip_id &&
	183	caam_eras[i].maj_rev == sec_vid->maj_rev)
	184	return caam_eras[i].era;
	185
	186	return -ENOTSUPP;
	187	}
	188	EXPORT_SYMBOL(caam_get_era);
	189
8e8ec596	190	/* Probe routine for CAAM top (controller) level */
2930d497	191	static int caam_probe(struct platform_device *pdev)
8e8ec596	192	{
281922a1	193	int ret, ring, rspec;
82c2f960	194	u64 caam_id;
8e8ec596 KP	195	struct device *dev;
	196	struct device_node nprop, np;
	197	struct caam_ctrl __iomem *ctrl;
	198	struct caam_full __iomem *topregs;
	199	struct caam_drv_private *ctrlpriv;
23457bc9 KP	200	#ifdef CONFIG_DEBUG_FS
	201	struct caam_perfmon *perfmon;
	202	#endif
986dfbcf	203	u64 cha_vid;
8e8ec596 KP	204
	205	ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
	206	if (!ctrlpriv)
	207	return -ENOMEM;
	208
	209	dev = &pdev->dev;
	210	dev_set_drvdata(dev, ctrlpriv);
	211	ctrlpriv->pdev = pdev;
	212	nprop = pdev->dev.of_node;
	213
	214	/* Get configuration properties from device tree */
	215	/* First, get register page */
	216	ctrl = of_iomap(nprop, 0);
	217	if (ctrl == NULL) {
	218	dev_err(dev, "caam: of_iomap() failed\n");
	219	return -ENOMEM;
	220	}
	221	ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
	222
	223	/* topregs used to derive pointers to CAAM sub-blocks only */
	224	topregs = (struct caam_full __iomem *)ctrl;
	225
	226	/* Get the IRQ of the controller (for security violations only) */
	227	ctrlpriv->secvio_irq = of_irq_to_resource(nprop, 0, NULL);
	228
	229	/*
	230	* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
e13af18a	231	* long pointers in master configuration register
8e8ec596 KP	232	*/
	233	setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE \|
	234	(sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
	235
	236	if (sizeof(dma_addr_t) == sizeof(u64))
e13af18a KP	237	if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
	238	dma_set_mask(dev, DMA_BIT_MASK(40));
	239	else
	240	dma_set_mask(dev, DMA_BIT_MASK(36));
	241	else
	242	dma_set_mask(dev, DMA_BIT_MASK(32));
8e8ec596	243
8e8ec596 KP	244	/*
	245	* Detect and enable JobRs
	246	* First, find out how many ring spec'ed, allocate references
	247	* for all, then go probe each one.
	248	*/
	249	rspec = 0;
54e198d4	250	for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring")
8e8ec596	251	rspec++;
a0ea0f6d SL	252	if (!rspec) {
	253	/* for backward compatible with device trees */
	254	for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring")
	255	rspec++;
	256	}
	257
8e8ec596 KP	258	ctrlpriv->jrdev = kzalloc(sizeof(struct device ) rspec, GFP_KERNEL);
	259	if (ctrlpriv->jrdev == NULL) {
	260	iounmap(&topregs->ctrl);
	261	return -ENOMEM;
	262	}
	263
	264	ring = 0;
	265	ctrlpriv->total_jobrs = 0;
54e198d4	266	for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") {
8e8ec596 KP	267	caam_jr_probe(pdev, np, ring);
	268	ctrlpriv->total_jobrs++;
	269	ring++;
	270	}
a0ea0f6d SL	271	if (!ring) {
	272	for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") {
	273	caam_jr_probe(pdev, np, ring);
	274	ctrlpriv->total_jobrs++;
	275	ring++;
	276	}
	277	}
8e8ec596 KP	278
	279	/* Check to see if QI present. If so, enable */
	280	ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
	281	CTPR_QI_MASK);
	282	if (ctrlpriv->qi_present) {
	283	ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
	284	/* This is all that's required to physically enable QI */
	285	wr_reg32(&topregs->qi.qi_control_lo, QICTL_DQEN);
	286	}
	287
	288	/* If no QI and no rings specified, quit and go home */
	289	if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
	290	dev_err(dev, "no queues configured, terminating\n");
	291	caam_remove(pdev);
	292	return -ENOMEM;
	293	}
	294
986dfbcf RG	295	cha_vid = rd_reg64(&topregs->ctrl.perfmon.cha_id);
986dfbcf RG	296
281922a1	297	/*
986dfbcf RG	298	* If SEC has RNG version >= 4 and RNG state handle has not been
986dfbcf RG	299	* already instantiated ,do RNG instantiation
281922a1	300	*/
986dfbcf RG	301	if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4 &&
986dfbcf RG	302	!(rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & RDSTA_IF0)) {
281922a1	303	kick_trng(pdev);
997ad290	304	ret = instantiate_rng(dev);
281922a1 KP	305	if (ret) {
	306	caam_remove(pdev);
	307	return ret;
	308	}
575c1bd5 VG	309
	310	/* Enable RDB bit so that RNG works faster */
	311	setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
281922a1 KP	312	}
281922a1 KP	313
8e8ec596 KP	314	/* NOTE: RTIC detection ought to go here, around Si time */
8e8ec596 KP	315
82c2f960 AP	316	caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);
82c2f960 AP	317
8e8ec596	318	/* Report "alive" for developer to see */
82c2f960 AP	319	dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
82c2f960 AP	320	caam_get_era(caam_id));
8e8ec596 KP	321	dev_info(dev, "job rings = %d, qi = %d\n",
	322	ctrlpriv->total_jobrs, ctrlpriv->qi_present);
	323
	324	#ifdef CONFIG_DEBUG_FS
	325	/*
	326	* FIXME: needs better naming distinction, as some amalgamation of
	327	* "caam" and nprop->full_name. The OF name isn't distinctive,
	328	* but does separate instances
	329	*/
	330	perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
	331
	332	ctrlpriv->dfs_root = debugfs_create_dir("caam", NULL);
	333	ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
	334
	335	/* Controller-level - performance monitor counters */
	336	ctrlpriv->ctl_rq_dequeued =
	337	debugfs_create_u64("rq_dequeued",
eda65cc6	338	S_IRUSR \| S_IRGRP \| S_IROTH,
8e8ec596 KP	339	ctrlpriv->ctl, &perfmon->req_dequeued);
	340	ctrlpriv->ctl_ob_enc_req =
	341	debugfs_create_u64("ob_rq_encrypted",
eda65cc6	342	S_IRUSR \| S_IRGRP \| S_IROTH,
8e8ec596 KP	343	ctrlpriv->ctl, &perfmon->ob_enc_req);
	344	ctrlpriv->ctl_ib_dec_req =
	345	debugfs_create_u64("ib_rq_decrypted",
eda65cc6	346	S_IRUSR \| S_IRGRP \| S_IROTH,
8e8ec596 KP	347	ctrlpriv->ctl, &perfmon->ib_dec_req);
	348	ctrlpriv->ctl_ob_enc_bytes =
	349	debugfs_create_u64("ob_bytes_encrypted",
eda65cc6	350	S_IRUSR \| S_IRGRP \| S_IROTH,
8e8ec596 KP	351	ctrlpriv->ctl, &perfmon->ob_enc_bytes);
	352	ctrlpriv->ctl_ob_prot_bytes =
	353	debugfs_create_u64("ob_bytes_protected",
eda65cc6	354	S_IRUSR \| S_IRGRP \| S_IROTH,
8e8ec596 KP	355	ctrlpriv->ctl, &perfmon->ob_prot_bytes);
	356	ctrlpriv->ctl_ib_dec_bytes =
	357	debugfs_create_u64("ib_bytes_decrypted",
eda65cc6	358	S_IRUSR \| S_IRGRP \| S_IROTH,
8e8ec596 KP	359	ctrlpriv->ctl, &perfmon->ib_dec_bytes);
	360	ctrlpriv->ctl_ib_valid_bytes =
	361	debugfs_create_u64("ib_bytes_validated",
eda65cc6	362	S_IRUSR \| S_IRGRP \| S_IROTH,
8e8ec596 KP	363	ctrlpriv->ctl, &perfmon->ib_valid_bytes);
	364
	365	/* Controller level - global status values */
	366	ctrlpriv->ctl_faultaddr =
	367	debugfs_create_u64("fault_addr",
eda65cc6	368	S_IRUSR \| S_IRGRP \| S_IROTH,
8e8ec596 KP	369	ctrlpriv->ctl, &perfmon->faultaddr);
	370	ctrlpriv->ctl_faultdetail =
	371	debugfs_create_u32("fault_detail",
eda65cc6	372	S_IRUSR \| S_IRGRP \| S_IROTH,
8e8ec596 KP	373	ctrlpriv->ctl, &perfmon->faultdetail);
	374	ctrlpriv->ctl_faultstatus =
	375	debugfs_create_u32("fault_status",
eda65cc6	376	S_IRUSR \| S_IRGRP \| S_IROTH,
8e8ec596 KP	377	ctrlpriv->ctl, &perfmon->status);
	378
	379	/* Internal covering keys (useful in non-secure mode only) */
	380	ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
	381	ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
	382	ctrlpriv->ctl_kek = debugfs_create_blob("kek",
eda65cc6	383	S_IRUSR \|
8e8ec596 KP	384	S_IRGRP \| S_IROTH,
	385	ctrlpriv->ctl,
	386	&ctrlpriv->ctl_kek_wrap);
	387
	388	ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
	389	ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
	390	ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
eda65cc6	391	S_IRUSR \|
8e8ec596 KP	392	S_IRGRP \| S_IROTH,
	393	ctrlpriv->ctl,
	394	&ctrlpriv->ctl_tkek_wrap);
	395
	396	ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
	397	ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
	398	ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
eda65cc6	399	S_IRUSR \|
8e8ec596 KP	400	S_IRGRP \| S_IROTH,
	401	ctrlpriv->ctl,
	402	&ctrlpriv->ctl_tdsk_wrap);
	403	#endif
	404	return 0;
	405	}
	406
	407	static struct of_device_id caam_match[] = {
	408	{
54e198d4	409	.compatible = "fsl,sec-v4.0",
8e8ec596	410	},
a0ea0f6d SL	411	{
	412	.compatible = "fsl,sec4.0",
	413	},
8e8ec596 KP	414	{},
	415	};
	416	MODULE_DEVICE_TABLE(of, caam_match);
	417
2930d497	418	static struct platform_driver caam_driver = {
8e8ec596 KP	419	.driver = {
	420	.name = "caam",
	421	.owner = THIS_MODULE,
	422	.of_match_table = caam_match,
	423	},
	424	.probe = caam_probe,
49cfe4db	425	.remove = caam_remove,
8e8ec596 KP	426	};
8e8ec596 KP	427
741e8c2d	428	module_platform_driver(caam_driver);
8e8ec596 KP	429
	430	MODULE_LICENSE("GPL");
	431	MODULE_DESCRIPTION("FSL CAAM request backend");
	432	MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");